SPRUJD4A December 2024 – November 2025 AM62D-Q1
Write multiple (page) access in asynchronous mode is not supported for address/data-multiplexed devices.
If the GPMC_CONFIG1_i[28] WRITEMULTIPLE bit is enabled (0x1) with the GPMC_CONFIG1_i[27] WRITETYPE bit as asynchronous (0x0), the GPMC processes single asynchronous accesses.
For accesses on non-multiplexed devices, see Section 12.4.3.4.9.3, Asynchronous and Synchronous Accesses in non-multiplexed Mode.