SPRUJD4A December 2024 – November 2025 AM62D-Q1
I/O only + DDR minimizes processor power by turning off all processor power supplies except the LVCMOS I/O power supply while keeping LPDDR4 in self-refresh. System power state transitions, including power supply control, can be performed by a single interface signal (PMIC_LPM_EN signal) with PMIC register programming. The implementation of I/O only + DDR mode is shown in Figure 6-4
I/O Only + DDR Self Refresh Features: