SPRUJD4A December 2024 – November 2025 AM62D-Q1
All the A53 cores use the common 36b SoC memory map shown in MAIN Memory Map for their physical address map. Since A53 natively supports up to 44b physical address, if A53 issues any transaction with non-zero upper 8 physical address bits, those upper 8 address bits are ignored by SoC address decoding logic.
Sitara’s SoC memory map is constructed to allow software utilizing bigger MMU page. The majority of the peripherals are put at 64KB aligned boundary. This is to allow A53 software to use 64KB MMU page to manage individual peripherals instead of using 4KB MMU page. There are a few exceptions.
Main domain GPIO is implemented by using two GPIO modules. However, these two GPIO modules are placed together. Software needs to manage two GPIO modules using a single MMU page. Since each GPIO pin is managed by a single bit inside GPIO registers, there is no virtual machine or OS isolation implemented.
The SoC also contains multiple DCC modules that are located at 4KB boundaries instead of 64KB. The A53 software can still use 64KB MMU page to manage these DCC modules. If any of the DCC needs to be allocated for other processors, the region-based firewall can provide the additional isolation needed. The firewall boundary granularity is 4KB, which allows each DDC to be assigned individually.
Firewall, QoS, ISC configurations are not on 64KB boundary. And each individual firewall module, QoS module, and ISC module is placed at 1KB boundaries.