SPRUJD4A December 2024 – November 2025 AM62D-Q1
Table 14-11117 lists the memory-mapped registers for the R5FSS_VIM module. All register offset addresses not listed in Table 14-11117 should be considered as reserved locations and the register contents should not be modified.
| Instance | WKUP Base Address | MCU Base Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0000h(1) | 07FF 0000h(1) |
| Offset | Acronym | Register Name | WKUP_R5FSS_VIC_CFG Physical Address |
MCU_R5FSS_VIC_CFG Physical Address |
|---|---|---|---|---|
| 0h | R5FSS_VIM_PID | Revision register | 2FFF 0000h | 07FF 0000h |
| 4h | R5FSS_VIM_INFO | Info register | 2FFF 0004h | 07FF 0004h |
| 8h | R5FSS_VIM_PRIIRQ | Prioritized IRQ register | 2FFF 0008h | 07FF 0008h |
| Ch | R5FSS_VIM_PRIFIQ | Prioritized FIQ register | 2FFF 000Ch | 07FF 000Ch |
| 10h | R5FSS_VIM_IRQGSTS | IRQ group status register | 2FFF 0010h | 07FF 0010h |
| 14h | R5FSS_VIM_FIQGSTS | FIQ group status register | 2FFF 0014h | 07FF 0014h |
| 18h | R5FSS_VIM_IRQVEC | IRQ vector address register | 2FFF 0018h | 07FF 0018h |
| 1Ch | R5FSS_VIM_FIQVEC | FIQ vector address register | 2FFF 001Ch | 07FF 001Ch |
| 20h | R5FSS_VIM_ACTIRQ | Active IRQ register | 2FFF 0020h | 07FF 0020h |
| 24h | R5FSS_VIM_ACTFIQ | Active FIQ register | 2FFF 0024h | 07FF 0024h |
| 30h | R5FSS_VIM_DEDVEC | DED vector address register | 2FFF 0030h | 07FF 0030h |
| 400h + formula | R5FSS_VIM_RAW_j | Raw status/set register | 2FFF 0400h + formula | 07FF 0400h + formula |
| 404h + formula | R5FSS_VIM_STS_j | Interrupt enable status/clear register | 2FFF 0404h + formula | 07FF 0404h + formula |
| 408h + formula | R5FSS_VIM_INTR_EN_SET_j | Interrupt enable set register | 2FFF 0408h + formula | 07FF 0408h + formula |
| 40Ch + formula | R5FSS_VIM_INTR_EN_CLR_j | Interrupt enabled clear register | 2FFF 040Ch + formula | 07FF 040Ch + formula |
| 410h + formula | R5FSS_VIM_IRQSTS_j | IRQ interrupt enable status/clear register | 2FFF 0410h + formula | 07FF 0410h + formula |
| 414h + formula | R5FSS_VIM_FIQSTS_j | FIQ interrupt enable status/clear register | 2FFF 0414h + formula | 07FF 0414h + formula |
| 418h + formula | R5FSS_VIM_INTMAP_j | Interrupt map register | 2FFF 0418h + formula | 07FF 0418h + formula |
| 41Ch + formula | R5FSS_VIM_INTTYPE_j | Interrupt type register | 2FFF 041Ch + formula | 07FF 041Ch + formula |
| 1000h + formula | R5FSS_VIM_PRI_INT_j | Interrupt priority register | 2FFF 1000h + formula | 07FF 1000h + formula |
| 2000h + formula | R5FSS_VIM_VEC_INT_j | Interrupt vector register | 2FFF 2000h + formula | 07FF 2000h + formula |
R5FSS_VIM_PID is shown in Figure 14-5527 and described in Table 14-11119.
Return to Summary Table.
This register contains the major and minor revisions for the module.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0000h | 07FF 0000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REV | |||||||||||||||||||||||||||||||
| R-60900001h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | REV | R | 60900001h | TI internal data. Identifies revision of peripheral. |
R5FSS_VIM_INFO is shown in Figure 14-5528 and described in Table 14-11121.
Return to Summary Table.
This contains information about the configuration of the R5FSS_VIM.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0004h | 07FF 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | INTERRUPTS | ||||||||||||||||||||||||||||||
| R-0h | R-200h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-11 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 10-0 | INTERRUPTS | R | 200h | Indicates the number of interrupts supported by the VIM. |
R5FSS_VIM_PRIIRQ is shown in Figure 14-5529 and described in Table 14-11123.
Return to Summary Table.
This register contains the number of the highest priority pending IRQ.
| Instance | WKUP Physical Address | WKUP Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0008h | 07FF 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| VALID | RESERVED | ||||||
| R-0h | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PRI | ||||||
| R-0h | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | NUM | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NUM | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | VALID | R | 0h | This field
indicates if the NUM field of this register is valid. |
| 30-20 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 19-16 | PRI | R | 0h | This field
indicates the priority of the pending IRQ interrupt. |
| 15-10 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 9-0 | NUM | R | 0h | This field
indicates the interrupt number of the pending IRQ interrupt with
the highest priority. |
R5FSS_VIM_PRIFIQ is shown in Figure 14-5530 and described in Table 14-11125.
Return to Summary Table.
This register contains the number of the highest priority pending FIQ.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 000Ch | 07FF 000Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| VALID | RESERVED | ||||||
| R-0h | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PRI | ||||||
| R-0h | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | NUM | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NUM | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | VALID | R | 0h | This field
indicates if the NUM field of this register is valid. |
| 30-20 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 19-16 | PRI | R | 0h | This field
indicates the priority of the pending FIQ interrupt. |
| 15-10 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 9-0 | NUM | R | 0h | This field
indicates the interrupt number of the pending FIQ interrupt with
the highest priority. |
R5FSS_VIM_IRQGSTS is shown in Figure 14-5531 and described in Table 14-11127.
Return to Summary Table.
This register indicates which groups of interrupts have pending, unmasked IRQ interrupts.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0010h | 07FF 0010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STS | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STS | R | 0h | This field indicates that one or more interrupts in group M are mapped to IRQ, unmasked, and pending. Bit 0 corresponds to group 0, bit 1 corresponds to group 1, etc. The interrupts associated with each group are [(M*32)+31:M*32] |
R5FSS_VIM_FIQGSTS is shown in Figure 14-5532 and described in Table 14-11129.
Return to Summary Table.
This register indicates which groups of interrupts have pending, unmasked FIQ interrupts.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0014h | 07FF 0014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STS | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STS | R | 0h | This field indicates that one or more interrupts in group M are mapped to FIQ, unmasked, and pending. Bit 0 corresponds to group 0, bit 1 corresponds to group 1, etc. The interrupts associated with each group are [(M*32)+31:M*32] |
R5FSS_VIM_IRQVEC is shown in Figure 14-5533 and described in Table 14-11131.
Return to Summary Table.
This register contains the 32-bit interrupt vector address of the currently pending IRQ.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0018h | 07FF 0018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | RESERVED | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | ADDR | R | 0h | This field
contains the upper 30 bits of the 32-bit interrupt vector
address (addresses must be 32-bit aligned) of the currently
pending highest priority IRQ (as indicated by the
R5FSS_VIM_PRIIRQ[9-0] NUM field). |
| 1-0 | RESERVED | R | 0h | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.) |
R5FSS_VIM_FIQVEC is shown in Figure 14-5534 and described in Table 14-11133.
Return to Summary Table.
This register contains the 32-bit interrupt vector address of the currently pending FIQ.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 001Ch | 07FF 001Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | RESERVED | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | ADDR | R | 0h | This field
contains the upper 30 bits of the 32-bit interrupt vector
address (addresses must be 32-bit aligned) of the currently
pending highest priority FIQ (as indicated by the
R5FSS_VIM_PRIFIQ[9-0] NUM field). |
| 1-0 | RESERVED | R | 0h | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.) |
R5FSS_VIM_ACTIRQ is shown in Figure 14-5535 and described in Table 14-11135.
Return to Summary Table.
This register contains the number of the active IRQ.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0020h | 07FF 0020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| VALID | RESERVED | ||||||
| R-0h | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PRI | ||||||
| R-0h | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | NUM | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NUM | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | VALID | R | 0h | This field
indicates if the NUM field of this register is valid. |
| 30-20 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 19-16 | PRI | R | 0h | This field
indicates the priority of the active IRQ interrupt. |
| 15-10 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 9-0 | NUM | R | 0h | This field
indicates the interrupt number of the active IRQ interrupt. |
R5FSS_VIM_ACTFIQ is shown in Figure 14-5536 and described in Table 14-11137.
Return to Summary Table.
This register contains the number of the active FIQ.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0024h | 07FF 0024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| VALID | RESERVED | ||||||
| R-0h | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PRI | ||||||
| R-0h | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | NUM | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NUM | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | VALID | R | 0h | This field
indicates if the NUM field of this register is valid. |
| 30-20 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 19-16 | PRI | R | 0h | This field
indicates the priority of the active FIQ interrupt. |
| 15-10 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 9-0 | NUM | R | 0h | This field
indicates the interrupt number of the active FIQ interrupt. |
R5FSS_VIM_DEDVEC is shown in Figure 14-5537 and described in Table 14-11139.
Return to Summary Table.
This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0030h | 07FF 0030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | RESERVED | ||||||||||||||||||||||||||||||
| R/W-0h | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | ADDR | R/W | 0h | This field
contains the upper 30 bits of the 32-bit interrupt vector
address (the address must be 32-bit aligned) of an interrupt to
be used if an uncorrectable double-bit error (DED) is detected
in any of the interrupt vector addresses. |
| 1-0 | RESERVED | R | 0h | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.) |
R5FSS_VIM_RAW_j is shown in Figure 14-5538 and described in Table 14-11141.
Return to Summary Table.
This register indicates the raw status of the events in group M.
Offset = 400h + (j * 20h); where j = 0h to Fh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0400h + formula | 07FF 0400h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STS | |||||||||||||||||||||||||||||||
| R/W1S-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STS | R/W1S | 0h | This is the raw
status of the events in group M. Each bit corresponds to event
Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is
M*32+1, etc). |
R5FSS_VIM_STS_j is shown in Figure 14-5539 and described in Table 14-11143.
Return to Summary Table.
This register indicates the masked status of the events in group M.
Offset = 404h + (j * 20h); where j = 0h to Fh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0404h + formula | 07FF 0404h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK | |||||||||||||||||||||||||||||||
| R/W1C-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MSK | R/W1C | 0h | This is the
masked status of the events in group M. Each bit corresponds to
event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit
1 is M*32+1, etc). |
R5FSS_VIM_INTR_EN_SET_j is shown in Figure 14-5540 and described in Table 14-11145.
Return to Summary Table.
This register is used to enable the mask for the events in group M.
Offset = 408h + (j * 20h); where j = 0h to Fh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0408h + formula | 07FF 0408h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK | |||||||||||||||||||||||||||||||
| R/W1S-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MSK | R/W1S | 0h | This field is
used to enable the mask of events in group M. Each bit
corresponds to event Q, where Q = M*32+bit (example: bit 0 is
event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_INTR_EN_CLR_j is shown in Figure 14-5541 and described in Table 14-11147.
Return to Summary Table.
This register is used to disable the mask for the events in group M.
Offset = 40Ch + (j * 20h); where j = 0h to Fh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 040Ch + formula | 07FF 040Ch + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK | |||||||||||||||||||||||||||||||
| R/W1C-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MSK | R/W1C | 0h | This field is
used to disable the mask of events in group M. Each bit
corresponds to event Q, where Q = M*32+bit (example: bit 0 is
event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_IRQSTS_j is shown in Figure 14-5542 and described in Table 14-11149.
Return to Summary Table.
This register indicates the masked status of the events in Group M that are also mapped as IRQs.
Offset = 410h + (j * 20h); where j = 0h to Fh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0410h + formula | 07FF 0410h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK | |||||||||||||||||||||||||||||||
| R/W1C-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MSK | R/W1C | 0h | This is the
masked status of the events in group M that are mapped to IRQ.
Each bit corresponds to event Q, where Q = M*32+bit (example:
bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_FIQSTS_j is shown in Figure 14-5543 and described in Table 14-11151.
Return to Summary Table.
This register indicates the masked status of the events in group M that are also mapped as FIQs.
Offset = 414h + (j * 20h); where j = 0h to Fh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0414h + formula | 07FF 0414h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK | |||||||||||||||||||||||||||||||
| R/W1C-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MSK | R/W1C | 0h | This is the
masked status of the events in group M that are mapped to FIQ.
Each bit corresponds to event Q, where Q = M*32+bit (example:
bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_INTMAP_j is shown in Figure 14-5544 and described in Table 14-11153.
Return to Summary Table.
This register is used to map interrupts as IRQ or FIQ.
Offset = 418h + (j * 20h); where j = 0h to Fh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 0418h + formula | 07FF 0418h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MSK | R/W | 0h | This field is
used to indicate which interrupt the corresponding event
influences (if enabled) for event group M. Each bit corresponds
to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0,
bit 1 is M*32+1, etc). |
R5FSS_VIM_INTTYPE_j is shown in Figure 14-5545 and described in Table 14-11155.
Return to Summary Table.
This register indicates whether an interrupt is a pulse or level source.
Offset = 41Ch + (j * 20h); where j = 0h to Fh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 041Ch + formula | 07FF 041Ch + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MSK | R/W | 0h | This field is
used to indicate whether the source of an interrupt is a level
(default) or a pulse for event group M. Each bit corresponds to
event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit
1 is M*32+1, etc). |
R5FSS_VIM_PRI_INT_j is shown in Figure 14-5546 and described in Table 14-11157.
Return to Summary Table.
This register is used to set the priority of interrupt Q.
Offset = 1000h + (j * 4h); where j = 0h to FFh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 1000h + formula | 07FF 1000h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VAL | ||||||||||||||||||||||||||||||
| R-0h | R/W-Fh | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
| 3-0 | VAL | R/W | Fh | This is the
priority for interrupt Q. If two interrupts have the same
priority, then whichever interrupt has the lower number Q wins
arbitration. |
R5FSS_VIM_VEC_INT_j is shown in Figure 14-5547 and described in Table 14-11159.
Return to Summary Table.
This register contains the vector address associated with interrupt Q.
Offset = 2000h + (j * 4h); where j = 0h to FFh.
| Instance | WKUP Physical Address | MCU Physical Address |
|---|---|---|
| R5FSS_VIC_CFG | 2FFF 2000h + formula | 07FF 2000h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VAL | RESERVED | ||||||||||||||||||||||||||||||
| R/W-0h | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | VAL | R/W | 0h | These are the
upper 30 bits of the 32-bit vector address associated with
interrupt Q. It is the address that will be reflected in the
R5FSS_VIM_IRQVEC or R5FSS_VIM_FIQVEC and the VECADDR output when
interrupt Q is the active interrupt. |
| 1-0 | RESERVED | R | 0h | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.) |