SPRUJD4A December 2024 – November 2025 AM62D-Q1
The IrDA function contains a programmable baud generator and a set of fixed dividers that divide the 48-MHz clock input down to the expected baud rate.
Figure 12-122 shows the baud rate generator and associated controls.
Figure 12-122 IrDA Baud Rate GeneratorBefore initializing or modifying clock parameter controls (UART_DLH, UART_DLL), MODE_SELECT=DISABLE (UART_MDR1[2-0] MODE_SELECT) must be set to 0x7). Failure to observe this rule can result in unpredictable module behavior.