SPRUJD4A December 2024 – November 2025 AM62D-Q1
Traffic monitoring bus probes are deployed at strategic points in the system interconnect and support the following capabilities:
Table 13-16 details the locations in the system interconnect that are probed:
| Probe Point | Bus Monitoring Details |
|---|---|
| A53SS0 Write Initiator | Provides visibility to all write requests initiated by A53SS0 |
| A53SS0 Read Initiator | Provides visibility to all read requests initiated by A53SS0 |
| A53SS0 ACP Target | Monitors traffic to the A53SS0 ACP port |
| DDR Target | Monitors RT and Non-RT traffic to DDR |
| GMPC Target | Monitors traffic to GPMC |
| FSS Target | Monitors traffic to FSS0 |
| Peripheral CBASS Targets |
Monitors traffic to these targets: ECAP# EQEP# I2C# MCAN# PDMA_SPI PDMA_UART SPI# UART# |
| McASP CBASS Targets |
Monitors traffic to these targets: EPWM# MCASP# |
| WKUP CBASS Targets |
Monitors traffic from MAIN to WKUP, including these targets: WKUP_GTC WKUP_R5F WKUP_TIMER# WKUP_RTI WKUP_I2C0 WKUP_CTRL_MMR0 WKUP_VTM0 |
| GPU Write Initiator | Provides visibility to all write requests initiated by GPU |
| GPU Read Initiator | Provides visibility to all read requests initiated by GPU |
| C7XSS0 MDMA Initiator | Provides visibility to access initiated by C7XSS0 MDMA port |
| C7XSS0 SDMA Target | Provides visibility to all requests to C7XSS0 SDMA port |
| C7XSS0 Memory Subsystem |
Monitors traffic within L2, including accesses: to CMMU From L2 to L1D$ From L1D$ to L2 From L1I$ to L2 Streaming Buffer to L2 |
| On-Chip SRAM | Monitors traffic to 64KB of MAIN OCSRAM |
| MCU SRAM | Monitors traffic to 512KB of MCU OCSRAM |
| MCU CBASS Targets |
Monitors traffic from MAIN to MCU, including these targets: MCU_R5F MCU_SPI# MCU_MCRC64 MCU_UART0 MCU_MCAN# MCU_TIMER# MCU_DCC0 MCU_RTI0 MCU_I2C0 |
| Infrastructure CBASS Targets |
Monitors traffic to these targets: CMP_EVENT_INTROUTER CTRL_MMR DCC# DDPA DFTSS ESM PSRAM# GPIO# EFUSE GPIOMUX_INTROUTER PADCFG_CTRL_MMR0 PLL_MMR0 PLLCTRL PSC TIMESYNC_EVENT_ROUTER |