In this mode, software can perform MMR writes at any time. The MMR synchronization
controller will wait until the next valid point in time for synchronizing the
written values between the two domains. The WR_PEND signal will indicate whether or
not synchronization is in progress.
- Identify the MMR writes to be performed and prepare a buffer of the writes to be
performed.
- (recommended) Poll RTC_SYNCPEND.WR_PEND until it is 0. WR_PEND must be zero
before writing the unlock values. Polling WR_PEND before unlock is the
higher-performance approach.
- If required, write RTC_KICK0 and RTC_KICK1 with the unlock values.
- (recommended) The host processor should execute a memory barrier
instruction in order to flush the unlock writes before proceeding with
the MMR writes to RTC.
- Perform each MMR write in sequence. MMR writes should be done in order of
increasing address offset.
- If required, write RTC_KICK0 with zeros to lock the functional lockout.
- (optional) Poll RTC_SYNCPEND.WR_PEND until it is 0 to ensure that the
writes are committed to the battery domain.
Once these steps are completed, RTC will synchronize the written values into the ON
domain. The synchronization should take a maximum of 61 microseconds.