SPRUJD4A December 2024 – November 2025 AM62D-Q1
For this combination the Tx Buffers section in the Message RAM is separated in two parts:
If the MCAN_TXBC[29-24] TFQS field is empty (zero) - only Dedicated Tx Buffers are used.
Tx prioritization:
Figure 12-291 shows Mixed Dedicated Tx Buffers/Tx FIFO example.
Figure 12-291 Mixed Dedicated Tx Buffers/Tx FIFO (example)