SPRUJD4A December 2024 – November 2025 AM62D-Q1
In Figure 12-102 the ECAP operating mode is almost the same as in the previous section except capture events are qualified as either rising or falling edge, this now gives both period and duty cycle information: Period1 = t3 – t1, Period2 = t5 – t3, …etc. Duty Cycle1 (on-time %) = (t2 – t1) / Period1 x 100%, etc. Duty Cycle1 (off-time %) = (t3 – t2) / Period1 x 100%, etc.
Figure 12-311 Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect| Register | Bit | Value |
|---|---|---|
| ECCTL1 | CAP1POL | EC_RISING |
| ECCTL1 | CAP2POL | EC_FALLING |
| ECCTL1 | CAP3POL | EC_RISING |
| ECCTL1 | CAP4POL | EC_FALLING |
| ECCTL1 | CTRRST1 | EC_ABS_MODE |
| ECCTL1 | CTRRST2 | EC_ABS_MODE |
| ECCTL1 | CTRRST3 | EC_ABS_MODE |
| ECCTL1 | CTRRST4 | EC_ABS_MODE |
| ECCTL1 | CAPLDEN | EC_ENABLE |
| ECCTL1 | PRESCALE | EC_DIV1 |
| ECCTL2 | CAP_APWM | EC_CAP_MODE |
| ECCTL2 | CONT_ONESHT | EC_CONTINUOUS |
| ECCTL2 | SYNCO_SEL | EC_SYNCO_DIS |
| ECCTL2 | SYNCI_EN | EC_DISABLE |
| ECCTL2 | TSCTRSTOP | EC_RUN |