SPRUJD4A December 2024 – November 2025 AM62D-Q1
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| FSS0_OSPI_0 | ✓ |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| FSS0_OSPI_0 | HCLK | MAIN_SYSCLK0 | data transfer clock | |
| FSS0_OSPI_0 | PCLK | MAIN_SYSCLK0 | configuration clock | |
| FSS0_OSPI_0 | RFCLK | MAIN_PLL0_HSDIV1_CLKOUT | MAIN_CTRL_MMR_CFG0_OSPI0_CLKSEL[0:0]=0 | functional reference clock |
| FSS0_OSPI_0 | RFCLK | MAIN_PLL1_HSDIV5_CLKOUT | MAIN_CTRL_MMR_CFG0_OSPI0_CLKSEL[0:0]=1 | functional reference clock |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| FSS0_OSPI_0 | FSS0_OSPI_0_ospi_ecc_corr_lvl_intr_0 | ESM0_esm_lvl_event_11 | ESM0 | FSS0_OSPI_0 interrupt request | level |
| FSS0_OSPI_0 | FSS0_OSPI_0_ospi_ecc_uncorr_lvl_intr_0 | ESM0_esm_lvl_event_74 | ESM0 | FSS0_OSPI_0 interrupt request | level |
| FSS0_OSPI_0 | FSS0_OSPI_0_ospi_lvl_intr_0 | GICSS0_spi_171 | GICSS0 | FSS0_OSPI_0 interrupt request | level |
| FSS0_OSPI_0 | FSS0_OSPI_0_ospi_lvl_intr_0 | WKUP_R5FSS0_CORE0_intr_171 | WKUP_R5FSS0_CORE0 | FSS0_OSPI_0 interrupt request | level |
| FSS0_OSPI_0 | FSS0_OSPI_0_ospi_lvl_intr_0 | MCU_R5FSS0_CORE0_cpu0_intr_171 | MCU_R5FSS0_CORE0 | FSS0_OSPI_0 interrupt request | level |