SPRUJD4A December 2024 – November 2025 AM62D-Q1
The RTC_SYNCPEND register can be accessed to determine if read or write synchronization between the DIG_CORE and DIG_ON domains is in progress. The RD_PEND bit will only be 1 if the register is read very early during boot, if it is very shortly after a module-level reset, or if the RELOAD_FROM_BBD feature has been used to re-run the on-reset MMR synchronization sequence. The WR_PEND bit will be 1 if writes to On Domain registers have been made to the Write Pending MMRs since the last falling edge of the 32KHz clock.
When RD_PEND is 0, the Shadow MMRs are in sync with the ON domain MMRs. As a slight exception to this rule, reads to the RTC_SUB_S_CNT, RTC_S_CNT_LSW, and RTC_S_CNT_MSW time counter registers are handled specially depending on the value of the CNT_FMODE field of the RTC_GENRAL_CTL register. This field controls the “freeze mode” of the aforementioned time counter registers. The use of “freeze mode” is to enable atomic read of the three time counter registers by preventing updates of more significant bits between the successive reads of those registers. Two “freeze modes” are available. In the first freeze mode, S_CNT_LSW, a read to RTC_S_CNT_LSW causes the MSW register to be frozen until read. In the second freeze mode, a read to RTC_SUB_S_CNT causes both RTC_S_CNT_LSW and RTC_S_CNT_MSW to freeze until they are read.
This “freeze mode” only affects read operations. Writes to the RTC_SUB_S_CNT, RTC_S_CNT_LSW, and RTC_S_CNT_MSW registers are always handled with atomic write protection. This atomic write protection must be invoked by writing SUB_S_CNT, S_CNT_LSW, and S_CNT_MSW in that order. Other write patterns to these registers not supported for RTC.