SPRUJD4A December 2024 – November 2025 AM62D-Q1
There are two SRAMs (each with size 4 KB - 512 words × 64-bit) in each MMCSD Subsystem. One SRAM dedicated for transmit and one SRAM dedicated for receive operations.
Figure 12-124 shows the ECC Aggregator block diagram.
Figure 12-231 ECC Aggregator Block DiagramFor more information about ECC Aggregator Registers, refer to MMCSD Registers.