SPRUJD4A December 2024 – November 2025 AM62D-Q1
The MMR values in the battery-backed domain are the “golden” copy of the RTC state. The RTC acts as though accesses to RTC read or write state which correspond to the values in the battery-backed domain. In order to reduce the complexity and scope of the synchronization logic, MMR accesses are only conditionally valid. Software needs to be aware of the state of certain MMRs which can indicate that certain MMR accesses would be invalid.
The RTC_SYNCPEND register needs to be read after device boot in order to ensure that the MMR Synchronization on Core Reset state machine has completed successfully. Doing any unlock or MMR writes before ensuring RD_PEND is 0 may cause a write error (signaled only by the WRT_ERR bit in the RTC_SYNCPEND register).
Generally, the MMRs stored in the battery-backed domain do not have deterministic reset values implemented in order to save area and power. On the first power-on, software will need to configure and initialize the time counter before using any RTC functionality.