SPRUJD4A December 2024 – November 2025 AM62D-Q1
An MMR write will be synchronized to the DIG_ON copy of the MMRs if the write is done while the functional lockout is currently unlocked. Depending on the value of O32K_OSC_DEP_EN, MMR writes to DIG_ON may be delayed until the next falling edge of the 32KHz clock. If O32K_OSC_DEP_EN is 0, then an MMR write should only be done when two successive reads to RTC_SYNCPEND demonstrate a falling edge of the main 32KHz clock and that the 32KHz clock is currently low.
If the functional lockout is currently locked, then if MMR writes to KICK0 and KICK1 are done before other MMR writes, the functional lockout will be unlocked for any ensuing writes. In principle, these MMR writes to open the functional lockout may be done at any time. Once these writes are done, further writes will be accepted and held pending in the CORE domain. A following MMR write to KICK0 or KICK1 will close the functional lockout for any subsequent writes. In order to support functionally correct operation, the functional lockout should be closed promptly once it’s open.
The RTC_SYNCPEND register’s WR_PEND status bit will be 1 while any writes are held in the CORE domain. The written value will be sent to the battery-backed domain to update the battery-backed domain’s register value. Once all pending write data has been sent to the battery-backed domain and all written values are saved there, then the WR_PEND status bit returns to 0.