| MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_commrx_level_0_0 |
MCU_R5FSS0_CORE0_cpu0_intr_90 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
| MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_commtx_level_0_0 |
MCU_R5FSS0_CORE0_cpu0_intr_91 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
| MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_cti_0 |
MCU_R5FSS0_CORE0_cpu0_intr_175 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
| MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_exp_intr_0 |
WKUP_ESM0_esm_lvl_event_30 |
WKUP_ESM0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
| MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_exp_intr_0 |
MCU_R5FSS0_CORE0_cpu0_intr_4 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
| MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_pmu_0 |
MCU_R5FSS0_CORE0_cpu0_intr_94 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
| MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_valfiq_0 |
MCU_R5FSS0_CORE0_cpu0_intr_95 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
| MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_valirq_0 |
MCU_R5FSS0_CORE0_cpu0_intr_96 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
| MCU_R5FSS0_COMMON0 |
MCU_R5FSS0_COMMON0_ecc_de_to_esm_0_0 |
WKUP_ESM0_esm_lvl_event_28 |
WKUP_ESM0 |
MCU_R5FSS0_COMMON0 interrupt request |
level |
| MCU_R5FSS0_COMMON0 |
MCU_R5FSS0_COMMON0_ecc_se_to_esm_0_0 |
WKUP_ESM0_esm_lvl_event_29 |
WKUP_ESM0 |
MCU_R5FSS0_COMMON0 interrupt request |
level |