SPRUJD4A December 2024 – November 2025 AM62D-Q1
External Debug Exception Catch Control Register
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| Instance Name | Physical Address |
|---|---|
| A53SS0 | 0007 3001 0098h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RES0_EDECCR_31_8 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RES0_EDECCR_31_8 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RES0_EDECCR_31_8 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NSE | SE | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RES0_EDECCR_31_8 | R/W | 0h | Reserved, RES0. |
| 7:4 | NSE | R/W | 0h | Coarse-grained Non-secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Non-secure exception levels. 0010 Exception catch debug event enabled for Non-secure EL1. 0100 Exception catch debug event enabled for Non-secure EL2. 0110 Exception catch debug event enabled for Non-secure EL1 and EL2. All other values are reserved. Bits [7,4] are reserved, RES0. |
| 3:0 | SE | R/W | 0h | Coarse-grained Secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Secure exception levels. 0010 Exception catch debug event enabled for Secure EL1. 1000 Exception catch debug event enabled for Secure EL3. 1010 Exception catch debug event enabled for Secure EL1 and EL3. All other values are reserved. Bits [2,0] are reserved. RES0. Ignored if ExternalSecureInvasiveDebugEnabled[] == FALSE. |