SPRUJD4A December 2024 – November 2025 AM62D-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| CTRL_MMR0 | 0011 0500h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL17 | RESERVED | |||||
| NONE | R/W | NONE | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL12 | RESERVED | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL8 | ||||
| NONE | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL7 | RESERVED | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL5 | RESERVED | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL2 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL1 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL0 | |
| R/W | NONE | R/W | NONE | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | NONE | 0h | Reserved |
| 17 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL17 | R/W | 0h | Selects the alternate clock source for MAIN PLL17 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin Reset Source: mod_por_rst_n |
| 16:13 | RESERVED | NONE | 0h | Reserved |
| 12 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL12 | R/W | 0h | Selects the alternate clock source for MAIN PLL12 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin Reset Source: mod_por_rst_n |
| 11:9 | RESERVED | NONE | 0h | Reserved |
| 8 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL8 | R/W | 0h | Selects the alternate clock source for MAIN PLL8 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin Reset Source: mod_por_rst_n |
| 7 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL7 | R/W | 0h | Selects the alternate clock source for MAIN PLL7 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin Reset Source: mod_por_rst_n |
| 6 | RESERVED | NONE | 0h | Reserved |
| 5 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL5 | R/W | 0h | Selects the alternate clock source for MAIN PLL5 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin Reset Source: mod_por_rst_n |
| 4:3 | RESERVED | NONE | 0h | Reserved |
| 2 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL2 | R/W | 0h | Selects the alternate clock source for MAIN PLL2 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin Reset Source: mod_por_rst_n |
| 1 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL1 | R/W | 0h | Selects the alternate clock source for MAIN PLL1 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin Reset Source: mod_por_rst_n |
| 0 | MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL0 | R/W | 0h | Selects the alternate clock source for MAIN PLL0 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin Reset Source: mod_por_rst_n |