SPRUJD4A December 2024 – November 2025 AM62D-Q1
When using synchronous interface protocols, the GPMC_CLK output only toggles during the read or write access cycle. In some applications, it may be desirable to have a continuous clock running at the GPMC interface clock frequency for clocking attached devices. This option is enabled by an optional clock path from the GPMC functional clock input (fclk) to the GPMC_CLKOUT pin. This clock output (GPMC_FCLK) can be selected through the standard MUXMODE selection of the GPMC_CLKOUT pin PADCONFIG control register
Note that when using synchronous interface protocols with the continuous clock option described above, the programmer should ensure that the GPMC outputs are timed to the same frequency. (GPMC_CONFIG1_x GPMCFCLKDIVIDER = 0).