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SPRUJD4A December 2024 – November 2025 AM62D-Q1

Table 6-31 lists the basic information of the MCU PLL.

Table 6-31 Basic Information of MCU_PLL0

PLL name	Type	HSDIV Available	Input clock	Comments
MCU_PLL0	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2, HSDIV3, HSDIV4	HFOSC0_CLKOUT	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾

(1) See Figure 6-41, Generic PLL Functional Diagram for PLLTS16FFCLAFRACF2 type for overview of the PLL.

(2) See Section 6.4.5.5.1 for synthesized clock parameters.

(3) See Section 6.4.5.5.2 for clock output parameters.

Table 6-32 lists the basic information of each of the MAIN PLLs.

Table 6-32 Basic Information of MAIN Domain PLLs

PLL name	Type	HSDIV Available	Input clock	Comments
PLL0	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2, HSDIV3, HSDIV4, HSDIV5, HSDIV6, HSDIV7, HSDIV8, HSDIV9		See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL1	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2, HSDIV3, HSDIV4, HSDIV5, HSDIV6		See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL2	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2, HSDIV3, HSDIV4, HSDIV5, HSDIV6, HSDIV7, HSDIV8, HSDIV9		See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL5	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2	MAIN_PLL5_REF_CLK	⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL7	PLLTS16FFCLAFRACF2	HSDIV0	MAIN_PLL7_REF_CLK	⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL8	PLLTS16FFCLAFRACF2	HSDIV0		See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL12	PLLTS16FFCLAFRACF2	HSDIV0		See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL15	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2		See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL17	PLLTS16FFCLAFRACF2	HSDIV0		See ⁽¹⁾, ⁽²⁾, and ⁽³⁾

(1) See Figure 6-41, Generic PLL Functional Diagram for PLLTS16FFCLAFRACF2 type for overview of the PLL.

(2) See Section 6.4.5.5.1 for synthesized clock parameters.

(3) See Section 6.4.5.5.2 for clock output parameters.