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时钟网络同步器

LMK5B33216

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具有集成式 2.5GHz 体声波 VCO、16 路输出、三个 DPLL 和 APLL 的网络同步器

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LMK5B33216

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产品详情

Function Clock network synchronizer Number of outputs 16 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 47 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Clock network synchronizer Number of outputs 16 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 47 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Number of input channels 2
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF)
    • 24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF
    • 42fs typical/ 60fs maximum RMS jitter at 312.5MHz
    • 47fs typical/ 65fs maximum RMS jitter at 156.25MHz
  • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
    • Programmable DPLL loop bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • Two differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • 16 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
    • Up to 20 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 14 differential outputs on OUT[15:0]_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 7 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • –40°C to 85°C operating temperature
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF)
    • 24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF
    • 42fs typical/ 60fs maximum RMS jitter at 312.5MHz
    • 47fs typical/ 65fs maximum RMS jitter at 156.25MHz
  • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
    • Programmable DPLL loop bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • Two differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • 16 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
    • Up to 20 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 14 differential outputs on OUT[15:0]_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 7 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • –40°C to 85°C operating temperature

The LMK5B33216 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5ns timing accuracy (ITU-T G.8273.2 Class D).

The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in the VCO and can generate 312.5MHz output clocks with 42fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 feature conventional LC VCOs to provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5B33216 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5ns timing accuracy (ITU-T G.8273.2 Class D).

The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in the VCO and can generate 312.5MHz output clocks with 42fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 feature conventional LC VCOs to provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 LMK5B33216 3-DPLL 3-APLL 2-IN 16-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications 数据表 (Rev. D) PDF | HTML 2026-8-14
应用手册 差分及单端信号的端接指南 PDF | HTML 英语版 PDF | HTML 2025-12-19
用户指南 LMK5B33216 编程人员指南 (Rev. C) PDF | HTML 英语版 (Rev.C) PDF | HTML 2025-11-25
应用手册 The Debug Guide for Network Synchronizers (Digital and Analog Phase-Locked Loops) PDF | HTML 2025-11-21
应用手册 PLL 器件的振荡器电源考虑因素 PDF | HTML 英语版 PDF | HTML 2025-11-19
应用手册 适用于快速数据中心交换机的 112G 和 224G PAM4 串行器/解 串器时钟 (Rev. A) PDF | HTML 英语版 (Rev.A) PDF | HTML 2025-1-24
应用手册 LMK5XXXXXS1 网络同步器针对 PTP 规范 G.8275.1 和 G.8275.2 的合规性测试报告 PDF | HTML 英语版 PDF | HTML 2024-6-25

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

LMK5B33216EVM — 适用于 LMK5B33216 具有 BAW VCO 的 16 路输出、3 个 DPLL 和 APLL 的网络同步器的评估模块

LMK5B33216 评估模块 (EVM) 平台用于开发 LMK5B33216 网络时钟发生器和同步器。该 EVM 可用于器件评估、合规性测试和系统原型设计。

LMK5B33216EVM 集成了三个模拟锁相环 (APLL) 和三个具有可编程环路带宽的数字 PLL (DPLL)。该 EVM 包含用于时钟输入、振荡器输入和时钟输出的超小型版本 A (SMA) 连接器，可将器件连接到 50Ω 测试设备。通过板载温度补偿晶体振荡器 (TCXO)，可在自由运行、锁定或保持模式下评估 LMK5B33216。

通过板载 USB 微控制器 (MCU) 接口，可在 PC 上使用 TI 时钟和合成器 (TICS) (...)

用户指南: PDF | HTML
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支持软件

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

德州仪器 (TI) 时钟和合成器 (TICS) 专业软件用于对具有以下前缀的产品编号的评估模块 (EVM) 进行编程：CDC、LMK 和 LMX。这些产品包括锁相环和电压控制振荡器 (PLL+VCO)、合成器和时钟器件。

支持的产品和硬件
仿真模型

LMK5B33216 Family IBIS model

SNAM295.ZIP (239 KB) - IBIS 模型
支持的产品和硬件
仿真模型

LMK5B33216 IBIS model

SNAM252.ZIP (167 KB) - IBIS 模型
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设计工具

CLOCK-PERFDATA-DESIGN — Clock performance data and register settings for clock generators, network synchronizers, jitter cleaners, and other clocking devices.

Configuration, raw phase noise data, noise plots, and register data for common use cases on clock generators, network synchronizers, jitter cleaners, and other clocking devices
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设计工具

CLOCK-TREE-ARCHITECT — 时钟树架构编程软件

时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。

支持的产品和硬件
设计工具

PLLATINUMSIM-SW — PLL 环路滤波器、相位噪声、锁定时间和杂散模拟工具

PLLATINUMSIM-SW 是一款仿真工具，允许用户创建我们 PLLatinum™ 集成电路的详细设计和仿真，其中包括 LMX 系列锁相环 (PLL) 和合成器。

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封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RGC) 64 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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