产品详情

Number of outputs 9 Output type LVDS, LVPECL Output frequency (max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
Number of outputs 9 Output type LVDS, LVPECL Output frequency (max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
    • Bypassable with VCO Mux When Not in 0-delay Mode
  • Channel Divider Values of 1, 2 to 510 (Even Divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • 0-delay Outputs
  • Internal or External Feedback of Output Clock
  • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock

All trademarks are the property of their respective owners.

  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
    • Bypassable with VCO Mux When Not in 0-delay Mode
  • Channel Divider Values of 1, 2 to 510 (Even Divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • 0-delay Outputs
  • Internal or External Feedback of Output Clock
  • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock

All trademarks are the property of their respective owners.

The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.


The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.


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* 数据表 LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO 数据表 (Rev. C) 2013年 4月 19日
设计指南 Clock Conditioner Owner's Manual 2006年 11月 10日

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软件编程工具

CODELOADER CodeLoader Device Register Programming v4.19.0

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

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The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

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TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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WQFN (RHS) 48 Ultra Librarian

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包含信息:
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  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 制造厂地点
  • 封装厂地点

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