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LMK03200

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具有集成 VCO 的精密 0 延迟时钟调节器

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数据表

LMK03200

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数据表 立即订购

产品详情

Function Clock generator Number of outputs 9 Output frequency (max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
Function Clock generator Number of outputs 9 Output frequency (max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
    • Bypassable with VCO Mux When Not in 0-delay Mode
  • Channel Divider Values of 1, 2 to 510 (Even Divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • 0-delay Outputs
  • Internal or External Feedback of Output Clock
  • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock

All trademarks are the property of their respective owners.

  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
    • Bypassable with VCO Mux When Not in 0-delay Mode
  • Channel Divider Values of 1, 2 to 510 (Even Divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • 0-delay Outputs
  • Internal or External Feedback of Output Clock
  • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock

All trademarks are the property of their respective owners.

The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.

The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.
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技术文档

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类型 项目标题 下载最新的英语版本 日期
* 数据表 LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO 数据表 (Rev. C) 2013年 4月 19日
技术文章 How to select an optimal clocking solution for your FPGA-based design 2015年 12月 9日
技术文章 Clocking sampled systems to minimize jitter 2014年 7月 31日
技术文章 Timing is Everything: How to optimize clock distribution in PCIe applications 2014年 3月 28日
EVM 用户指南 LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO Eval 2012年 1月 26日
设计指南 Clock Conditioner Owner's Manual 2006年 11月 10日

设计和开发

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评估板

LMK03200EVAL — 具有集成 VCO 的 LMK03200 系列精密 0 延迟时钟调节器评估板

LMK03200 评估板可简化对采用集成式 VCO 的 LMK03200 系列精密 0 延迟时钟调节器的评估。可使用德州仪器 (TI) 的 CodeLoader 软件对评估板进行配置和控制，该软件可从 TI 网站下载。

CodeLoader 软件可在 Windows 2000 或 Windows XP PC 上运行。CodeLoader 软件用于通过 MICROWIRETM 接口对 LMK03200 器件的内部寄存器进行编程。

用户指南: PDF
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应用软件和框架

CLOCKDESIGNTOOL — 时钟设计工具 - 环路滤波器和器件配置 + 仿真

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
用户指南: PDF
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IDE、配置、编译器或调试器

CODELOADER — CodeLoader 器件寄存器编程

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

Which software do I use?

Product

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设计工具

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模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
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WQFN (RHS) 48 了解详情

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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