产品详细信息

Function Differential Additive RMS jitter (Typ) (fs) 57 Output frequency (Max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout Operating temperature range (C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (Typ) (fs) 57 Output frequency (Max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout Operating temperature range (C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
VQFN (RHD) 28 25 mm² 5 x 5
  • 2:8 Differential Buffer
  • Selectable Clock Inputs Through Control terminal
  • Universal Inputs Accept LVPECL, LVDS, and
    LVCMOS/LVTTL
  • Eight LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 73 mA
  • Very Low Additive Jitter: <100 fs,rms in 10 kHz to
    20 MHz Offset Range:
    • 57 fs, rms (typical) at 122.88 MHz
    • 48 fs, rms (typical) at 156.25 MHz
    • 30 fs, rms (typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Output Skew: 20 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Supports 105°C PCB Temperature
    (Measured with a Thermal Pad)
  • ESD Protection Exceeds 2 kV (HBM)
  • Available in 5-mm × 5-mm QFN-28 (RHD)
    Package
  • 2:8 Differential Buffer
  • Selectable Clock Inputs Through Control terminal
  • Universal Inputs Accept LVPECL, LVDS, and
    LVCMOS/LVTTL
  • Eight LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 73 mA
  • Very Low Additive Jitter: <100 fs,rms in 10 kHz to
    20 MHz Offset Range:
    • 57 fs, rms (typical) at 122.88 MHz
    • 48 fs, rms (typical) at 156.25 MHz
    • 30 fs, rms (typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Output Skew: 20 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Supports 105°C PCB Temperature
    (Measured with a Thermal Pad)
  • ESD Protection Exceeds 2 kV (HBM)
  • Available in 5-mm × 5-mm QFN-28 (RHD)
    Package

The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1208 is packaged in a small 28-pin, 5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.

The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1208 is packaged in a small 28-pin, 5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.

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* 数据表 CDCLVP1208 Eight LVPECL Output, High-Performance Clock 2:8 Buffer 数据表 (Rev. E) PDF | HTML 23 Nov 2015
用户指南 CDCLVP1208 User's Guide 21 Oct 2009

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评估板

CDCLVP1208EVM — CDCLVP1208 评估模块

CDCLVP1208 是一款高性能、低附加相位噪声时钟缓冲器。它具有两个通用输入缓冲器,支持单端或差动时钟输入,可通过控制引脚进行选择。该器件还具有片上偏压发生器,它可以为器件输入提供 LVPECL 共模电压。此评估模块 (EVM) 旨在演示 CDCLVP1208 的电性能。这个完全组装且经过工厂测试的评估板允许对 CDCLVP1208 器件的所有功能进行全面验证。为达到最佳性能,该评估板配备有 50Ω SMA 连接器和受控良好的 50Ω 阻抗微带传输线。
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CDCLVPxxxx IBIS Model (Rev. B)

SLLM056B.ZIP (40 KB) - IBIS Model
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