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CDCLVP215

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双通道 1:5 高速 LVPECL 扇出缓冲器

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CDCLVP215

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产品详情

Number of outputs 10 Additive RMS jitter (typ) (fs) 300 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVPECL
Number of outputs 10 Additive RMS jitter (typ) (fs) 300 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVPECL
VQFN (RHB) 32 25 mm² 5 x 5
  • 2× One Differential Clock Input Pair LVPECL to 5 Differential LVPECL Clock Outputs
  • Fully Compatible With LVPECL/LVECL
  • Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
  • Open Input Default State
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in the QFN32 Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With the MC100 Series EP111, LVEP210, ES6111, LVEP111
  • APPLICATIONS
    • Designed for Driving 50- Transmission Lines High Performance Clock Distribution
  • 2× One Differential Clock Input Pair LVPECL to 5 Differential LVPECL Clock Outputs
  • Fully Compatible With LVPECL/LVECL
  • Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
  • Open Input Default State
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in the QFN32 Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With the MC100 Series EP111, LVEP210, ES6111, LVEP111
  • APPLICATIONS
    • Designed for Driving 50- Transmission Lines High Performance Clock Distribution

The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50- transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50 .

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLKA or CLKB and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP215 is characterized for operation from –40°C to 85°C.

The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50- transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50 .

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLKA or CLKB and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP215 is characterized for operation from –40°C to 85°C.
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* 数据表 Low-Voltage Dual Differential 1:5 LVPECL Clock Driver 数据表 (Rev. B) 2009年 11月 2日

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