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LMK02002

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具有集成 PLL 和 4 个 LVPECL 输出的 1 至 800MHz 精密时钟分配器

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数据表

LMK02002

正在供货
数据表 立即订购

产品详细信息

Function Clock generator Number of outputs 4 Output frequency (Max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVPECL Operating temperature range (C) -40 to 85 Features Integrated integer-N PLL, uWire Rating Catalog
Function Clock generator Number of outputs 4 Output frequency (Max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVPECL Operating temperature range (C) -40 to 85 Features Integrated integer-N PLL, uWire Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7

  • 20 fs additive jitter
  • Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz
  • Clock output frequency range of 1 to 800 MHz
  • 4 LVPECL clock outputs
  • Dedicated divider and delay blocks on each clock output
  • Pin compatible family of clocking devices
  • 3.15 to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

    • Target Applications

  • Data Converter Clocking
  • Networking, SONET/SDH, DSLAM
  • Wireless Infrastructure
  • Medical
  • Test and Measurement
  • Military / Aerospace

  • 20 fs additive jitter
  • Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz
  • Clock output frequency range of 1 to 800 MHz
  • 4 LVPECL clock outputs
  • Dedicated divider and delay blocks on each clock output
  • Pin compatible family of clocking devices
  • 3.15 to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

    • Target Applications

  • Data Converter Clocking
  • Networking, SONET/SDH, DSLAM
  • Wireless Infrastructure
  • Medical
  • Test and Measurement
  • Military / Aerospace

    • The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks.

    Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

    The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.

    The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks.

    Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

    The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.
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    技术文档

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    类型 项目标题 下载最新的英语版本 日期
    * 数据表 LMK02002 Precision Clock Conditioner with Integrated PLL 数据表 16 Aug 2007
    技术文章 How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
    技术文章 Clocking sampled systems to minimize jitter 31 Jul 2014
    技术文章 Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
    应用手册 AN-1821 CPRI Repeater System (Rev. A) 26 Apr 2013
    设计指南 Clock Conditioner Owner's Manual 10 Nov 2006

    设计和开发

    如需其他信息或资源，请查看下方列表，点击标题即可进入详情页面。

    应用软件和框架

    CLOCKDESIGNTOOL — 时钟设计工具 - 环路滤波器和器件配置 + 仿真

    The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
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    应用软件和框架

    TICSPRO-SW — 德州仪器 (TI) 时钟和合成器 (TICS) 专业软件

    德州仪器 (TI) 时钟和合成器 (TICS) 专业软件用于对具有以下前缀的产品编号的评估模块 (EVM) 进行编程：CDC、LMK 和 LMX。这些产品包括锁相环和电压控制振荡器 (PLL+VCO)、合成器和时钟器件。
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    IDE、配置、编译器或调试器

    CODELOADER — CodeLoader 器件寄存器编程

    The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

    Which software do I use?

    Product

    (...)
    document-pdfAcrobat 用户指南
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    模拟工具

    PSPICE-FOR-TI 适用于 TI 设计和模拟工具的 PSpice®

    PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

    借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

    在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
    发送申请
    设计工具

    CLOCK-TREE-ARCHITECT 时钟树架构编程软件

    时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。
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    封装 引脚数 下载
    WQFN (RHS) 48 了解详情

    订购和质量

    包含信息：
    • RoHS
    • REACH
    • 器件标识
    • 引脚镀层/焊球材料
    • MSL 等级/回流焊峰值温度
    • MTBF/时基故障估算
    • 材料成分
    • 认证摘要
    • 持续可靠性监测

    支持与培训

    视频