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CDCLVP1216

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低抖动 2 路输入可选 1:16 通用至 LVPECL 缓冲器

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数据表

CDCLVP1216

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产品详情

Number of outputs 16 Additive RMS jitter (typ) (fs) 57 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
Number of outputs 16 Additive RMS jitter (typ) (fs) 57 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
VQFN (RGZ) 48 49 mm² 7 x 7
  • 2:16 Differential Buffer
  • Selectable Clock Inputs Through Control Pin
  • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/
    LVTTL
  • 16 LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 110 mA
  • Very Low Additive Jitter: <100 fs, RMS in 10-kHz to
    20-MHz Offset Range:
    • 57 fs, RMS (Typical) at 122.88 MHz
    • 48 fs, RMS (Typical) at 156.25 MHz
    • 30 fs, RMS (Typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 550 ps
  • Maximum Output Skew: 30 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured with a
    Thermal Pad)
  • ESD Protection Exceeds 2000 V (HBM)
  • Available in 7-mm × 7-mm VQFN-48 (RGZ) Package
  • 2:16 Differential Buffer
  • Selectable Clock Inputs Through Control Pin
  • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/
    LVTTL
  • 16 LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 110 mA
  • Very Low Additive Jitter: <100 fs, RMS in 10-kHz to
    20-MHz Offset Range:
    • 57 fs, RMS (Typical) at 122.88 MHz
    • 48 fs, RMS (Typical) at 156.25 MHz
    • 30 fs, RMS (Typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 550 ps
  • Maximum Output Skew: 30 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured with a
    Thermal Pad)
  • ESD Protection Exceeds 2000 V (HBM)
  • Available in 7-mm × 7-mm VQFN-48 (RGZ) Package

The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1216 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVP1216 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1216 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1216 is packaged in a small 48-pin, 7-mm × 7-mm VQFN package and is characterized for operation from –40°C to +85°C.

The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1216 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVP1216 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1216 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1216 is packaged in a small 48-pin, 7-mm × 7-mm VQFN package and is characterized for operation from –40°C to +85°C.
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* 数据表 CDCLVP1216 16-LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. F) PDF | HTML 2015年 12月 7日

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评估板

CDCLVP1216EVM — CDCLVP1216 评估模块

CDCLVP1216EVM 是用于 CDCLVP1216 的评估模块。CDCLVP1216 是一款多用途、低附加抖动缓冲器，可从两个可选 LVPECL（LVDS 或 LVCMOS 输入）中生成 16 份 LVPECL 时钟输出。它的最大时钟频率高达 2GHz。低于 0.1ps 的总附加抖动、10kHz 至 20MHz 的 RMS 范围以及低至 30ps 的总输出偏移使该器件成为众多苛刻应用的理想选择。

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