CDCLVP1216
- 2:16 Differential Buffer
- Selectable Clock Inputs Through Control Pin
- Universal Inputs Accept LVPECL, LVDS, and LVCMOS/
LVTTL - 16 LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 110 mA
- Very Low Additive Jitter: <100 fs, RMS in 10-kHz to
20-MHz Offset Range:- 57 fs, RMS (Typical) at 122.88 MHz
- 48 fs, RMS (Typical) at 156.25 MHz
- 30 fs, RMS (Typical) at 312.5 MHz
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 550 ps
- Maximum Output Skew: 30 ps
- LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C to +85°C
- Supports 105°C PCB Temperature (Measured with a
Thermal Pad) - ESD Protection Exceeds 2000 V (HBM)
- Available in 7-mm × 7-mm VQFN-48 (RGZ) Package
The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1216 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVP1216 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1216 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1216 is packaged in a small 48-pin, 7-mm × 7-mm VQFN package and is characterized for operation from 40°C to +85°C.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | CDCLVP1216 16-LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. F) | PDF | HTML | 2015年 12月 7日 | ||
EVM 用户指南 | CDCLVP1216EVM User's Guide | 2009年 5月 27日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
CDCLVP1216EVM — CDCLVP1216 评估模块
CDCLVP1216EVM 是用于 CDCLVP1216 的评估模块。CDCLVP1216 是一款多用途、低附加抖动缓冲器,可从两个可选 LVPECL(LVDS 或 LVCMOS 输入)中生成 16 份 LVPECL 时钟输出。它的最大时钟频率高达 2GHz。低于 0.1ps 的总附加抖动、10kHz 至 20MHz 的 RMS 范围以及低至 30ps 的总输出偏移使该器件成为众多苛刻应用的理想选择。
CLOCK-TREE-ARCHITECT — 时钟树架构编程软件
PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®
借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。
在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
封装 | 引脚 | 下载 |
---|---|---|
VQFN (RGZ) | 48 | 查看选项 |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。