LMK04821
- JEDEC JESD204B Support
- Ultra-Low RMS
Jitter
- 88 fs RMS Jitter (12 kHz to 20 MHz)
- 91 fs RMS Jitter (100 Hz to 20 MHz)
- –162.5 dBc/Hz Noise Floor at 245.76 MHz
- Up to 14 Differential Device Clocks from
PLL2
- Up to 7 SYSREF Clocks
- Maximum Clock Output Frequency 3.1 GHz
- LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
- Up to 1 Buffered VCXO/Crystal Output from
PLL1
- LVPECL, LVDS, 2xLVCMOS Programmable
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- Up to 3 Redundant Input
Clocks
- Automatic and Manual Switch-Over Modes
- Hitless Switching and LOS
- Integrated Low-Noise Crystal Oscillator Circuit
- Holdover Mode When Input Clocks are Lost
- Up to 3 Redundant Input
Clocks
- PLL2
- Normalized [1 Hz] PLL Noise Floor of
–227 dBc/Hz - Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Two Integrated Low-Noise VCOs
- Normalized [1 Hz] PLL Noise Floor of
- 50% Duty Cycle Output Divides, 1 to 32
(even and odd) - Precision Digital Delay, Dynamically Adjustable
- 25-ps Step Analog Delay
- Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
- Industrial Temperature Range: –40 to 85°C
- Supports 105°C PCB Temperature (Measured at Thermal Pad)
- 3.15-V to 3.45-V Operation
- Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)
The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.
The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs 数据表 (Rev. AS) | PDF | HTML | 2017-9-27 | ||
| 应用手册 | LMK时钟 family LVDS输出交流耦合设计注意事项 | 2021-6-10 | ||||
| 应用手册 | Multi-Clock Synchronization | 2019-12-30 | ||||
| 技术文章 | Timing is Everything: Design JESD204B clocking using system reference modes | PDF | HTML | 2015-6-16 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
LMK04821EVM — 采用 122.88MHz VCXO 的 LMK04821EVM 双环路抖动清除器评估模块
LMK04821EVM 支持 LMK0482x 系列产品，该系列产品是支持 JEDEC JESD204B 且在业内具有超高性能的时钟调节器。双环路 PLLatinum™ 架构使用低噪声 VCXO 模块实现低于 100fs 的抖动（12kHz 至 20MHz）。双环路架构由两个高性能锁相环 (PLL)、一个低噪声晶体振荡器电路以及一个高性能压控振荡器 (VCO) 构成。
122.88MHz VCXO 已预安装。 用户可以将 VCXO 换成自己的定制 VCXO 或通过 SMA 连接器连接。
通常情况下，PLL2 中使用内部 VCO，但是也提供外部 VCO 空间，或者可以通过 SMA 连接器连接外部 (...)
CODELOADER — CodeLoader Device Register Programming v4.19.0
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | (...) |
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
德州仪器 (TI) 时钟和合成器 (TICS) 专业软件用于对具有以下前缀的产品编号的评估模块 (EVM) 进行编程：CDC、LMK 和 LMX。这些产品包括锁相环和电压控制振荡器 (PLL+VCO)、合成器和时钟器件。
CLOCK-TREE-ARCHITECT — 时钟树架构编程软件
时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。
PLLATINUMSIM-SW — PLL 环路滤波器、相位噪声、锁定时间和杂散模拟工具
PLLATINUMSIM-SW 是一款仿真工具，允许用户创建我们 PLLatinum™ 集成电路的详细设计和仿真，其中包括 LMX 系列锁相环 (PLL) 和合成器。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (NKD) | 64 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。