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时钟和计时
时钟缓冲器

LMK1D2102

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双组 2 通道输出 LVDS 1.8V、2.5V 和 3.3V 缓冲器

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LMK1D2102

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产品详情

Number of outputs 4 Additive RMS jitter (typ) (fs) 50 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Number of outputs 4 Additive RMS jitter (typ) (fs) 50 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RGT) 16 9 mm² 3 x 3
  • High-performance LVDS clock buffer family: up to 2GHz
    • Dual 1:2 differential buffer
    • Dual 1:4 differential buffer
  • Supply voltage: 1.71V to 3.465V
  • Fail-safe input operation
  • Low additive jitter: < max 60fs RMS in 12kHz to 20MHz at 156.25MHz
    • Very low phase noise floor: -164dBc/Hz (typical)
  • Very low propagation delay < 575ps max
  • Output skew of 20ps max
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels.
  • LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in
    • LMK1D2102: 3mm × 3mm, 16-Pin VQFN
    • LMK1D2104: 5mm × 5mm, 28-Pin VQFN
  • High-performance LVDS clock buffer family: up to 2GHz
    • Dual 1:2 differential buffer
    • Dual 1:4 differential buffer
  • Supply voltage: 1.71V to 3.465V
  • Fail-safe input operation
  • Low additive jitter: < max 60fs RMS in 12kHz to 20MHz at 156.25MHz
    • Very low phase noise floor: -164dBc/Hz (typical)
  • Very low propagation delay < 575ps max
  • Output skew of 20ps max
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels.
  • LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in
    • LMK1D2102: 3mm × 3mm, 16-Pin VQFN
    • LMK1D2104: 5mm × 5mm, 28-Pin VQFN

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of up to 8 pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to 4 LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML or LVCMOS.

The LMK1D210x is specifically designed for driving 50Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in 1.8V, 2.5V, 3.3V LVCMOS Clock Driver Connected to LMK1D210x Input must be applied to the unused negative input pin.

Using the control pin (EN), output banks can either be enabled or disabled. If this pin is left open, two buffers with all outputs are enabled, if switched to a logic "0", both banks with all outputs are disabled (static logic "0"), if switched to a logic "1", one bank and the outputs are disabled while another bank with the outputs are enabled. The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8V or 2.5V or 3.3V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D210x package variant is shown in the table below:

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of up to 8 pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to 4 LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML or LVCMOS.

The LMK1D210x is specifically designed for driving 50Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in 1.8V, 2.5V, 3.3V LVCMOS Clock Driver Connected to LMK1D210x Input must be applied to the unused negative input pin.

Using the control pin (EN), output banks can either be enabled or disabled. If this pin is left open, two buffers with all outputs are enabled, if switched to a logic "0", both banks with all outputs are disabled (static logic "0"), if switched to a logic "1", one bank and the outputs are disabled while another bank with the outputs are enabled. The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8V or 2.5V or 3.3V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D210x package variant is shown in the table below:
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* 数据表 LMK1D210x Low Additive Jitter LVDS Buffer 数据表 (Rev. C) PDF | HTML 2026年 2月 27日

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