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LMK1D1208

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8 通道输出 LVDS 1.8V、2.5V 和 3.3V 缓冲器

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8 通道输出 LVDS 1.8V、2.5V 和 3.3V 缓冲器

LMK1D1208

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数据表 立即订购

产品详细信息

Function Clock buffer, Differential Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout, Universal inputs Operating temperature range (C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Function Clock buffer, Differential Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout, Universal inputs Operating temperature range (C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
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VQFN (RHD) 28 25 mm² 5 x 5
open-in-new 查找其它 时钟缓冲器
  • High-performance LVDS clock buffer family with 2 inputs and 4 (2:4) or 8 (2:8) outputs.
  • Output frequency up to 2 GHz.
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < maximum 60 fs RMS in 12-kHz to 20-MHz at 156.25 MHz

    • Very low phase noise floor: –164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Universal inputs accept LVDS, LVPECL, LVCMOS, LP-HCSL, HCSL and CML inputs
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:

    • LMK1D1204: 3-mm × 3-mm, 16-pin VQFN (RGT)

    • LMK1D1208: 5-mm × 5-mm, 28-pin VQFN (RHD)
  • High-performance LVDS clock buffer family with 2 inputs and 4 (2:4) or 8 (2:8) outputs.
  • Output frequency up to 2 GHz.
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < maximum 60 fs RMS in 12-kHz to 20-MHz at 156.25 MHz

    • Very low phase noise floor: –164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Universal inputs accept LVDS, LVPECL, LVCMOS, LP-HCSL, HCSL and CML inputs
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:

    • LMK1D1204: 3-mm × 3-mm, 16-pin VQFN (RGT)

    • LMK1D1208: 5-mm × 5-mm, 28-pin VQFN (RHD)

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The LMK1D120x clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 or 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The LMK1D12x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS.

The LMK1D12x is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (logic low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D12x package variant is shown in the table below:

The LMK1D120x clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 or 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The LMK1D12x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS.

The LMK1D12x is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (logic low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D12x package variant is shown in the table below:

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类型 标题 下载最新的英文版本 日期
* 数据表 LMK1D120x Low Additive Jitter LVDS Buffer 数据表 (Rev. A) 2021年 8月 10日
用户指南 LMK1D1208EVM User's Guide 2021年 8月 4日

设计与开发

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评估板

LMK1D1208EVM — 适用于 LMK1D1208 低抖动 2:8 LVDS 扇出缓冲器的评估模块

LMK1D1208 是一款高性能、低附加抖动 LVDS 时钟缓冲器，具有两个差分输入和八个 LVDS 输出。该评估模块 (EVM) 旨在演示 LMK1D1208 的电气性能，还可用于评估 LMK1Dxxxx 系列中的其他 28 引脚器件。为了实现出色性能，LMK1D1208EVM 配备了 50Ω SMA 连接器和阻抗控制 50Ω 微带传输线。
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LMK1DX IBIS Model (Rev. A)

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  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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