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CDCLVP2102

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低抖动双通道 1:2 通用至 LVPECL 缓冲器

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CDCLVP2102

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产品详情

Number of outputs 4 Additive RMS jitter (typ) (fs) 89 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 10 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
Number of outputs 4 Additive RMS jitter (typ) (fs) 89 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 10 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
VQFN (RGT) 16 9 mm² 3 x 3
  • Dual 1:2 Differential Buffer
  • Two Clock Inputs
  • Universal Inputs Can Accept LVPECL,
    LVDS, LVCMOS/LVTTL
  • Four LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption:
    48 mA
  • Very Low Additive Jitter: <100 fs,
    RMS in 10-kHz to 20-MHz Offset Range
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Within Bank Output Skew: 10 ps
  • LVPECL Reference Voltage, VAC_REF,
    Available for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C
    to +85°C
  • Supports 105°C PCB Temperature
    (Measured with a Thermal Pad)
  • Available in 3-mm × 3-mm, 16-Pin
    VQFN (RGT) Package
  • ESD Protection Exceeds 2000 V (HBM)
  • Dual 1:2 Differential Buffer
  • Two Clock Inputs
  • Universal Inputs Can Accept LVPECL,
    LVDS, LVCMOS/LVTTL
  • Four LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption:
    48 mA
  • Very Low Additive Jitter: <100 fs,
    RMS in 10-kHz to 20-MHz Offset Range
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Within Bank Output Skew: 10 ps
  • LVPECL Reference Voltage, VAC_REF,
    Available for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C
    to +85°C
  • Supports 105°C PCB Temperature
    (Measured with a Thermal Pad)
  • Available in 3-mm × 3-mm, 16-Pin
    VQFN (RGT) Package
  • ESD Protection Exceeds 2000 V (HBM)

The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2102 clock buffer distributes two clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2102 is characterized for operation from –40°C to +85°C and is available in a 3-mm × 3-mm, VQFN-16 package.

The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2102 clock buffer distributes two clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2102 is characterized for operation from –40°C to +85°C and is available in a 3-mm × 3-mm, VQFN-16 package.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. C) PDF | HTML 2013年 10月 25日
用户指南 CDCLVP2102 User's Guide 2009年 7月 9日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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