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微控制器 (MCU) 和处理器
微处理器和 DSP
音频和雷达 DSP SoC

DRA790

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适用于音频放大器且具有 500MHz C66x DSP 的 300MHz Arm Cortex-A15 SoC 处理器

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数据表
用户指南

DRA790

正在供货
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产品详情

CPU 1 Arm Cortex-A15 Frequency (MHz) 300 Coprocessors 4 Arm Cortex-M4 Display type 1 HDMI, 2 LCD Protocols Ethernet, ICSS, Profibus PCIe 2 PCIe Gen 2 Hardware accelerators Audio tracking logic, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 1 Arm Cortex-A15 Frequency (MHz) 300 Coprocessors 4 Arm Cortex-M4 Display type 1 HDMI, 2 LCD Protocols Ethernet, ICSS, Profibus PCIe 2 PCIe Gen 2 Hardware accelerators Audio tracking logic, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCCSP (CBD) 538 289 mm² (17 mm × 17 mm)
  • Architecture designed for infotainment co-processor applications, hybrid radio and amplifier applications
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • DDR3/DDR3L Memory Interface (EMIF) module
    • Supports up to DDR-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Display subsystem
    • Display controller With DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Six high-speed inter-integrated circuit (I2C) ports
  • HDQ™/1-Wire® Interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High-speed USB 2.0 dual-role device
  • High-speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® CSI-2 camera serial interface
  • Up to 186 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)
  • Architecture designed for infotainment co-processor applications, hybrid radio and amplifier applications
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • DDR3/DDR3L Memory Interface (EMIF) module
    • Supports up to DDR-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Display subsystem
    • Display controller With DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Six high-speed inter-integrated circuit (I2C) ports
  • HDQ™/1-Wire® Interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High-speed USB 2.0 dual-role device
  • High-speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® CSI-2 camera serial interface
  • Up to 186 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)

The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA79x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA79x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA79x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA79x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 DRA79x Infotainment Applications Processor 数据表 (Rev. F) PDF | HTML 2019-11-25
* 用户指南 DRA79x J6 RSP - SoC for Automotive Infotainment Technical Reference Manual (Rev. C) 2019-5-21
* 勘误表 DRA79x Silicon Errata 2016-12-12
应用手册 Jacinto6 SoC 上 VISION SDK 和 PSDKLA 之间的 IVA-HD 共 享 PDF | HTML 英语版 PDF | HTML 2021-11-18
应用手册 在 Jacinot6 SOC 上集成 VISION SDK 和 PSDK 之间的虚拟 DRM PDF | HTML 英语版 PDF | HTML 2021-10-13
应用手册 AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020-1-6
应用手册 Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019-6-11
应用手册 Achieving Early CAN Response on DRA7xx Devices 2018-11-28
应用手册 DRA74x_75x/DRA72x Performance (Rev. A) 2018-10-31
应用手册 Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 2018-9-14
应用手册 The Implementation of YUV422 Output for SRV 2018-8-2
应用手册 MMC DLL Tuning (Rev. B) 2018-7-31
应用手册 Integrating AUTOSAR on TI SoC: Fundamentals 2018-6-18
应用手册 ECC/EDC on TDAxx (Rev. B) 2018-6-13
应用手册 Tools and Techniques to Root Case Failures in Video Capture Subsystem 2018-6-12
应用手册 Sharing VPE Between VISIONSDK and PSDKLA 2018-5-4
应用手册 Android Boot Optimization on DRA7xx Devices (Rev. A) 2018-2-13
应用手册 Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 2017-11-30
应用手册 Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 2017-11-27
应用手册 Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017-11-7
应用手册 A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017-11-3
应用手册 Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017-9-12
应用手册 Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 2017-8-14
应用手册 Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 2017-7-12
应用手册 Linux Boot Time Optimizations on DRA7xx Devices 2017-3-31
应用手册 Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 2017-2-17
应用手册 Early Splash Screen on DRA7x Devices 2017-1-31
应用手册 Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016-12-15
应用手册 Gstreamer Migration Guidelines 2016-4-26
用户指南 Jacinto6 Android Video Encoder Software Design Specification User's Guide 2016-4-21
用户指南 Jacinto6 Android Video Decoder Software Design Specification User's Guide 2016-4-21
应用手册 Flashing Binaries to DRA7xx Factory Boards Using DFU 2016-4-14
应用手册 Tools and Techniques for Audio Debugging 2016-4-13
应用手册 Debugging Tools and Techniques With IPC3.x 2016-3-30
应用手册 Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 2016-1-15
白皮书 Informational ADAS as Software Upgrade to Today’s Infotainment Systems 2014-10-14
应用手册 Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014-8-13
白皮书 Today’s high-end infotainment soon becoming mainstream 2014-6-2

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

软件开发套件 (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive 是用于 TI Jacinto™ DRAx 系列信息娱乐系统 SoC 的基础软件开发平台。使用此软件框架，用户可以为下一代汽车开发功能丰富的信息娱乐系统解决方案，例如可重新配置的数字仪表组、集成式驾驶舱、车载信息娱乐系统、远程信息处理系统、后排娱乐系统等等。该 SDK 基于通用的 Processor SDK 平台。

亮点
  • 长期稳定 (LTS) 主线 Linux 内核支持
  • U-Boot 引导加载程序支持
  • Linaro GNU Compiler Collection (GCC) 工具链
  • (...)
支持的产品和硬件
软件开发套件 (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive 是用于 TI Jacinto™ DRAx 系列信息娱乐系统 SoC 的基础软件开发平台。使用此软件框架，用户可以为下一代汽车开发功能丰富的信息娱乐系统解决方案，例如可重新配置的数字仪表组、集成式驾驶舱、车载信息娱乐系统、远程信息处理系统、后排娱乐系统等等。该 SDK 基于通用的 Processor SDK 平台。

亮点
  • 长期稳定 (LTS) 主线 Linux 内核支持
  • U-Boot 引导加载程序支持
  • Linaro GNU Compiler Collection (GCC) 工具链
  • (...)
支持的产品和硬件
软件开发套件 (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive 是用于 TI Jacinto™ DRAx 系列信息娱乐系统 SoC 的基础软件开发平台。使用此软件框架，用户可以为下一代汽车开发功能丰富的信息娱乐系统解决方案，例如可重新配置的数字仪表组、集成式驾驶舱、车载信息娱乐系统、远程信息处理系统、后排娱乐系统等等。该 SDK 基于通用的 Processor SDK 平台。

亮点
  • 长期稳定 (LTS) 主线 Linux 内核支持
  • U-Boot 引导加载程序支持
  • Linaro GNU Compiler Collection (GCC) 工具链
  • (...)
支持的产品和硬件
IDE、配置、编译器或调试器

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

支持的产品和硬件
操作系统 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
支持的产品和硬件
支持软件

VCTR-3P-MICROSAR — 适用于微控制器和高性能计算机 (HPC) 的 Vector MICROSAR AUTOSAR 软件

MICROSAR 和 DaVinci 产品系列凭借适用于微控制器和 HPC 的先进嵌入式软件和强大的开发工具简化了 ECU 开发。利用先进的基础设施软件，即可为 ECU 奠定良好基础，并使用相关工具简化所有配套开发任务。MICROSAR 嵌入式软件是按照 AUTOSAR classic 和 adaptive 等相关标准开发的。根据 ISO 26262 高达 ASIL D 的安全标准，该软件还适用于安全相关应用。此外，智能网络安全功能可保护控制单元免受未经授权的访问和操纵。Vector 涵盖汽车和其他工业应用的所有用例。对于具有高性能计算机的软件定义车辆 (...)

来源：Vector Informatik GmbH
支持的产品和硬件
仿真模型

DRA71x and DRA79x BSDL Model (Rev. A)

SPRM695A.ZIP (15 KB) - BSDL 模型
支持的产品和硬件
仿真模型

DRA71x and DRA79x IBIS Model

SPRM697.ZIP (9618 KB) - IBIS 模型
支持的产品和硬件
仿真模型

DRA71x and DRA79x Thermal Model

SPRM696.ZIP (2 KB) - 热模型
支持的产品和硬件
计算工具

CLOCKTREETOOL — Clock Tree Tool for Sitara™ ARM® Processors

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
FCCSP (CBD) 538 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

支持和培训

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如果您对质量、包装或订购 TI 产品有疑问，请参阅 TI 支持。​​​​​​​​​​​​​​

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