SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

1.4.2 FLNONMAINECC Registers

Table 1-5 lists the memory-mapped registers for the FLNONMAINECC registers. All register offset addresses not listed in Table 1-5 should be considered as reserved locations and the register contents should not be modified.

Table 1-5 FLNONMAINECC Registers
OffsetAcronymRegister NameSection
60100800hBCR_CONFIG_IDPredetermined Bootcode config signature IDSection 1.4.2.1
60100804hBOOTCFG0Controls enable/disable of AHB-AP, ET-AP, PWR-AP.
Values: DEBUG_EN, DEBUG_EN_PW, DEBUG_NS_EN, DEBUG_NS_EN_PW, DEBUG_DIS; Serial Wire Debug Port mode.
Disabling this will disable all Debug ports including CFG_AP, SEC_AP.
When disabled no DSSM commands are serviced		Section 1.4.2.2
60100808hBOOTCFG1Controls BSL pin invocation capability.
Values: BSL_PIN_INVOKE_EN, BSL_PIN_INVOKE_DIS; Controls debug access release until INITDONE is issued		Section 1.4.2.3
6010080ChBOOTCFG2Controls CSC policy in SYSCTL.
YES enables CSC policy checking; Controls flash bank swap policy in SYSCTL		Section 1.4.2.4
60100810hBOOTCFG3Fast boot mode configuration - Skips certain boot time checks when enabled; Bootloader mode enable/disable control.
Must be enabled for BSL functionality		Section 1.4.2.5
60100814hBOOTCFG4Mass erase mode configuration.
Values: BC_CFG_MASS_ERASE_EN(0xAABB), BC_CFG_MASS_ERASE_EN_PW(0xCCDD), BC_CFG_MASS_ERASE_DIS(0x5522); Factory reset mode configuration.
Values: BC_CFG_FACTORY_RESET_EN(0xAABB), BC_CFG_FACTORY_RESET_EN_PW(0xCCDD), BC_CFG_FACTORY_RESET_DIS(0x5522)		Section 1.4.2.6
60100818hMASS_ERASE_0Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 0Section 1.4.2.7
6010081ChMASS_ERASE_1Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 1Section 1.4.2.8
60100820hMASS_ERASE_2Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 2Section 1.4.2.9
60100824hMASS_ERASE_3Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 3Section 1.4.2.10
60100828hMASS_ERASE_4Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 4Section 1.4.2.11
6010082ChMASS_ERASE_5Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 5Section 1.4.2.12
60100830hMASS_ERASE_6Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 6Section 1.4.2.13
60100834hMASS_ERASE_7Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 7Section 1.4.2.14
60100838hFACTORY_RESET_0Password for factory reset command - Word 0Section 1.4.2.15
6010083ChFACTORY_RESET_1Password for factory reset command - Word 1Section 1.4.2.16
60100840hFACTORY_RESET_2Password for factory reset command - Word 2Section 1.4.2.17
60100844hFACTORY_RESET_3Password for factory reset command - Word 3Section 1.4.2.18
60100848hFACTORY_RESET_4Password for factory reset command - Word 4Section 1.4.2.19
6010084ChFACTORY_RESET_5Password for factory reset command - Word 5Section 1.4.2.20
60100850hFACTORY_RESET_6Password for factory reset command - Word 6Section 1.4.2.21
60100854hFACTORY_RESET_7Password for factory reset command - Word 7Section 1.4.2.22
60100858hDEBUG_LOCK_0Password for debug access authentication - Word 0Section 1.4.2.23
6010085ChDEBUG_LOCK_1Password for debug access authentication - Word 1Section 1.4.2.24
60100860hDEBUG_LOCK_2Password for debug access authentication - Word 2Section 1.4.2.25
60100864hDEBUG_LOCK_3Password for debug access authentication - Word 3Section 1.4.2.26
60100868hDEBUG_LOCK_4Password for debug access authentication - Word 4Section 1.4.2.27
6010086ChDEBUG_LOCK_5Password for debug access authentication - Word 5Section 1.4.2.28
60100870hDEBUG_LOCK_6Password for debug access authentication - Word 6Section 1.4.2.29
60100874hDEBUG_LOCK_7Password for debug access authentication - Word 7Section 1.4.2.30
60100878hDEBUG_NS_LOCK_0Password for non-secure debug access - Word 0Section 1.4.2.31
6010087ChDEBUG_NS_LOCK_1Password for non-secure debug access - Word 1Section 1.4.2.32
60100880hDEBUG_NS_LOCK_2Password for non-secure debug access - Word 2Section 1.4.2.33
60100884hDEBUG_NS_LOCK_3Password for non-secure debug access - Word 3Section 1.4.2.34
60100888hDEBUG_NS_LOCK_4Password for non-secure debug access - Word 4Section 1.4.2.35
6010088ChDEBUG_NS_LOCK_5Password for non-secure debug access - Word 5Section 1.4.2.36
60100890hDEBUG_NS_LOCK_6Password for non-secure debug access - Word 6Section 1.4.2.37
60100894hDEBUG_NS_LOCK_7Password for non-secure debug access - Word 7Section 1.4.2.38
60100898hRESERVED_REG0
6010089ChRESERVED_REG1
601008A0hRESERVED_REG2
601008A4hRESERVED_REG3
601008A8hRESERVED_REG4
601008AChRESERVED_REG5Reserved - Word 5
601008B0hRESERVED_REG6Reserved - Word 6
601008B4hRESERVED_REG7Reserved - Word 7
601008B8hSECURE_BOOT_MODEControls application authentication; Reserved field
601008BChUSER_SECURE_APP_START_ADDRStarting address for secure applicationSection 1.4.2.40
601008C0hUSER_SECURE_APP_LENGTHLength of secure applicationSection 1.4.2.41
601008C4hUSER_SECURE_APP_CRC_0Secure application CRC - Word 0Section 1.4.2.42
601008C8hRESERVED_REG8Reserved field - Word 1
601008CChRESERVED_REG9Reserved field - Word 2
601008D0hRESERVED_REG10Reserved field - Word 3
601008D4hRESERVED_REG11Reserved field - Word 4
601008D8hRESERVED_REG12Reserved field - Word 5
601008DChRESERVED_REG13Reserved field - Word 6
601008E0hRESERVED_REG14Reserved field - Word 7
601008E4hBANK0_NM_USER_CONFIGUser Config Non Main Flash Static Write Protection.
WEP_DISABLE=0xAABB; Reserved field
601008E8hBANK0_WRITE_ERASE_PROTECTION_AWrite protection for first 32 sectorsSection 1.4.2.44
601008EChBANK0_WRITE_ERASE_PROTECTION_BWrite Protection for 512KB-64KBSection 1.4.2.45
601008F0hBANK0_SECURITY_PROTECTION_ASecurity protection for first 32 sectorsSection 1.4.2.46
601008F4hBANK0_SECURITY_PROTECTION_BSecurity protection for 512KB-64KBSection 1.4.2.47
601008F8hBANK0_PRIVILEGE_PROTECTION_APrivilege protection for first 32 sectorsSection 1.4.2.48
601008FChBANK0_PRIVILEGE_PROTECTION_BPrivilege protection for 512KB-64KBSection 1.4.2.49
60100900hBANK0_RESERVEDReserved field for BANK0 alignment
60100904hBANK1_WRITE_ERASE_PROTECTION_AWrite protection for first 32 sectorsSection 1.4.2.50
60100908hBANK1_WRITE_ERASE_PROTECTION_BWrite Protection for 512KB-64KBSection 1.4.2.51
6010090ChBANK1_SECURITY_PROTECTION_ASecurity protection for first 32 sectorsSection 1.4.2.52
60100910hBANK1_SECURITY_PROTECTION_BSecurity protection for 512KB-64KBSection 1.4.2.53
60100914hBANK1_PRIVILEGE_PROTECTION_APrivilege protection for first 32 sectorsSection 1.4.2.54
60100918hBANK1_PRIVILEGE_PROTECTION_BPrivilege protection for 512KB-64KBSection 1.4.2.55
6010091ChBANK1_RESERVEDReserved field for BANK1
60100920hRESERVED_REG15Reserved field
60100924hRESERVED_REG16Reserved field
60100928hRESERVED_REG17Reserved field
6010092ChRESERVED_REG18Reserved field
60100930hBOOTCLK0Clock configuration; PLL multiplier value; PLL divider value; PLL clock source configurationSection 1.4.2.56
60100934hBOOTCLK1CPU delay cycles for PLL settling time; CPU delay cycles for XTAL monitoring; Reserved configuration field 0
60100938hRESERVED_REG_0Reserved configuration field 0; Reserved configuration field 1
6010093ChRESERVED_REG_1Reserved configuration field 2; Reserved configuration field 3
60100940hRESERVED_REG_2Reserved configuration field 4; Reserved configuration field 5
60100944hRESERVED_REG_3Reserved configuration field 6; Reserved configuration field 7
60100948hRESERVED_REG_4Reserved configuration field 8; Reserved configuration field 9
6010094ChCRCJAMCRC of BCR config structureSection 1.4.2.58
60100C00hBSL_CONFIG_IDPredetermined Bootloader config signature IDSection 1.4.2.59
60100C04hBSLPINCFG0UART receive pin number configuration; UART receive pin multiplexer selection; UART transmit pin number configuration; UART transmit pin multiplexer selectionSection 1.4.2.60
60100C08hBSLPINCFG1I2C data pin number configuration; I2C data pin multiplexer selection; I2C clock pin number configuration; I2C clock pin multiplexer selectionSection 1.4.2.61
60100C0ChBSLPINCFG2MCAN receive pin number configuration; MCAN receive pin multiplexer selection; MCAN transmit pin number configuration; MCAN transmit pin multiplexer selectionSection 1.4.2.62
60100C10hBSLCONFIG0BSL invoke pin configuration data 0; BSL invoke pin configuration data 1; Memory readout control.
ENABLE allows memory read operations		Section 1.4.2.63
60100C14hPASSWORD_0BSL access password - Word 0Section 1.4.2.64
60100C18hPASSWORD_1BSL access password - Word 1Section 1.4.2.65
60100C1ChPASSWORD_2BSL access password - Word 2Section 1.4.2.66
60100C20hPASSWORD_3BSL access password - Word 3Section 1.4.2.67
60100C24hPASSWORD_4BSL access password - Word 4Section 1.4.2.68
60100C28hPASSWORD_5BSL access password - Word 5Section 1.4.2.69
60100C2ChPASSWORD_6BSL access password - Word 6Section 1.4.2.70
60100C30hPASSWORD_7BSL access password - Word 7Section 1.4.2.71
60100C34hAPP_REV_POINTERPointer to application version information in MAIN flashSection 1.4.2.72
60100C38hBSLCONFIG1Security alert response: Factory Reset/Disable BSL/Ignore; UART communication speed selection for ROM BSLSection 1.4.2.73
60100C3ChI2C_SLAVE_ADDRI2C slave address for ROM BSL I2C interface; Reserved field; Reserved field
60100C40hRESERVED_REG_0Reserved field; Reserved field; Reserved field; Reserved field
60100C44hRESERVED_REG_1Reserved field; Reserved field; Reserved field; Reserved field
60100C48hRESERVED_REG_2Reserved field; Reserved field; Reserved field; Reserved field
60100C4ChCRCJAMCRC of BSL configuration structure

Complex bit access types are encoded to fit into small table cells. Table 1-6 shows the codes that are used for access types in this section.

Table 1-6 FLNONMAINECC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

1.4.2.1 BCR_CONFIG_ID Register (Offset = 60100800h) [Reset = 00000000h]

BCR_CONFIG_ID is shown in Table 1-7.

Return to the Summary Table.

Predetermined Bootcode config signature ID

Table 1-7 BCR_CONFIG_ID Register Field Descriptions
BitFieldTypeResetDescription
31-0BCR_CONFIG_IDR/W0hPredetermined Bootcode config signature ID

1.4.2.2 BOOTCFG0 Register (Offset = 60100804h) [Reset = 00000000h]

BOOTCFG0 is shown in Table 1-8.

Return to the Summary Table.

Controls enable/disable of AHB-AP, ET-AP, PWR-AP. Values: DEBUG_EN, DEBUG_EN_PW, DEBUG_NS_EN, DEBUG_NS_EN_PW, DEBUG_DIS; Serial Wire Debug Port mode. Disabling this will disable all Debug ports including CFG_AP, SEC_AP. When disabled no DSSM commands are serviced

Table 1-8 BOOTCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-16SWDP_MODER/W0hSerial Wire Debug Port mode. Disabling this will disable all Debug ports including CFG_AP, SEC_AP. When disabled no DSSM commands are serviced
  • 5522h = DISABLED configuration
  • AABBh = ENABLED configuration
15-0DEBUG_ACCESSR/W0hControls enable/disable of AHB-AP, ET-AP, PWR-AP. Values: DEBUG_EN, DEBUG_EN_PW, DEBUG_NS_EN, DEBUG_NS_EN_PW, DEBUG_DIS
  • 5522h = DISABLED configuration
  • AABBh = ENABLED configuration

1.4.2.3 BOOTCFG1 Register (Offset = 60100808h) [Reset = 00000000h]

BOOTCFG1 is shown in Table 1-9.

Return to the Summary Table.

Controls BSL pin invocation capability. Values: BSL_PIN_INVOKE_EN, BSL_PIN_INVOKE_DIS; Controls debug access release until INITDONE is issued

Table 1-9 BOOTCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-16DEBUG_HOLDR/W0hControls debug access release until INITDONE is issued
15-0BSL_PIN_INVOKER/W0hControls BSL pin invocation capability. Values: BSL_PIN_INVOKE_EN, BSL_PIN_INVOKE_DIS
  • 5522h = DISABLED configuration
  • AABBh = ENABLED configuration

1.4.2.4 BOOTCFG2 Register (Offset = 6010080Ch) [Reset = 00000000h]

BOOTCFG2 is shown in Table 1-10.

Return to the Summary Table.

Controls CSC policy in SYSCTL. YES enables CSC policy checking; Controls flash bank swap policy in SYSCTL

Table 1-10 BOOTCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-16FLASH_BANK_SWAP_POLICYR/W0hControls flash bank swap policy in SYSCTL
15-0CSC_EXISTSR/W0hControls CSC policy in SYSCTL. YES enables CSC policy checking
  • 5522h = DISABLED configuration
  • AABBh = ENABLED configuration

1.4.2.5 BOOTCFG3 Register (Offset = 60100810h) [Reset = 00000000h]

BOOTCFG3 is shown in Table 1-11.

Return to the Summary Table.

Fast boot mode configuration - Skips certain boot time checks when enabled; Bootloader mode enable/disable control. Must be enabled for BSL functionality

Table 1-11 BOOTCFG3 Register Field Descriptions
BitFieldTypeResetDescription
31-16BOOTLOADER_MODER/W0hBootloader mode enable/disable control. Must be enabled for BSL functionality
15-0FAST_BOOT_MODER/W0hFast boot mode configuration - Skips certain boot time checks when enabled

1.4.2.6 BOOTCFG4 Register (Offset = 60100814h) [Reset = 00000000h]

BOOTCFG4 is shown in Table 1-12.

Return to the Summary Table.

Mass erase mode configuration. Values: BC_CFG_MASS_ERASE_EN(0xAABB), BC_CFG_MASS_ERASE_EN_PW(0xCCDD), BC_CFG_MASS_ERASE_DIS(0x5522); Factory reset mode configuration. Values: BC_CFG_FACTORY_RESET_EN(0xAABB), BC_CFG_FACTORY_RESET_EN_PW(0xCCDD), BC_CFG_FACTORY_RESET_DIS(0x5522)

Table 1-12 BOOTCFG4 Register Field Descriptions
BitFieldTypeResetDescription
31-16FACTORY_RESET_MODER/W0hFactory reset mode configuration. Values: BC_CFG_FACTORY_RESET_EN(0xAABB), BC_CFG_FACTORY_RESET_EN_PW(0xCCDD), BC_CFG_FACTORY_RESET_DIS(0x5522)
  • 5522h = DISABLE configuration
  • AABBh = ENABLE configuration
  • CCDDh = ENABLE_WITH_PASSWORD configuration
15-0MASS_ERASE_MODER/W0hMass erase mode configuration. Values: BC_CFG_MASS_ERASE_EN(0xAABB), BC_CFG_MASS_ERASE_EN_PW(0xCCDD), BC_CFG_MASS_ERASE_DIS(0x5522)
  • 5522h = DISABLE configuration
  • AABBh = ENABLE configuration
  • CCDDh = ENABLE_WITH_PASSWORD configuration

1.4.2.7 MASS_ERASE_0 Register (Offset = 60100818h) [Reset = 00000000h]

MASS_ERASE_0 is shown in Table 1-13.

Return to the Summary Table.

Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 0

Table 1-13 MASS_ERASE_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0MASS_ERASE_0R/W0hPassword for DSSM_BC_MASS_ERASE_REQUEST command - Word 0

1.4.2.8 MASS_ERASE_1 Register (Offset = 6010081Ch) [Reset = 00000000h]

MASS_ERASE_1 is shown in Table 1-14.

Return to the Summary Table.

Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 1

Table 1-14 MASS_ERASE_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0MASS_ERASE_1R/W0hPassword for DSSM_BC_MASS_ERASE_REQUEST command - Word 1

1.4.2.9 MASS_ERASE_2 Register (Offset = 60100820h) [Reset = 00000000h]

MASS_ERASE_2 is shown in Table 1-15.

Return to the Summary Table.

Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 2

Table 1-15 MASS_ERASE_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0MASS_ERASE_2R/W0hPassword for DSSM_BC_MASS_ERASE_REQUEST command - Word 2

1.4.2.10 MASS_ERASE_3 Register (Offset = 60100824h) [Reset = 00000000h]

MASS_ERASE_3 is shown in Table 1-16.

Return to the Summary Table.

Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 3

Table 1-16 MASS_ERASE_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0MASS_ERASE_3R/W0hPassword for DSSM_BC_MASS_ERASE_REQUEST command - Word 3

1.4.2.11 MASS_ERASE_4 Register (Offset = 60100828h) [Reset = 00000000h]

MASS_ERASE_4 is shown in Table 1-17.

Return to the Summary Table.

Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 4

Table 1-17 MASS_ERASE_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0MASS_ERASE_4R/W0hPassword for DSSM_BC_MASS_ERASE_REQUEST command - Word 4

1.4.2.12 MASS_ERASE_5 Register (Offset = 6010082Ch) [Reset = 00000000h]

MASS_ERASE_5 is shown in Table 1-18.

Return to the Summary Table.

Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 5

Table 1-18 MASS_ERASE_5 Register Field Descriptions
BitFieldTypeResetDescription
31-0MASS_ERASE_5R/W0hPassword for DSSM_BC_MASS_ERASE_REQUEST command - Word 5

1.4.2.13 MASS_ERASE_6 Register (Offset = 60100830h) [Reset = 00000000h]

MASS_ERASE_6 is shown in Table 1-19.

Return to the Summary Table.

Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 6

Table 1-19 MASS_ERASE_6 Register Field Descriptions
BitFieldTypeResetDescription
31-0MASS_ERASE_6R/W0hPassword for DSSM_BC_MASS_ERASE_REQUEST command - Word 6

1.4.2.14 MASS_ERASE_7 Register (Offset = 60100834h) [Reset = 00000000h]

MASS_ERASE_7 is shown in Table 1-20.

Return to the Summary Table.

Password for DSSM_BC_MASS_ERASE_REQUEST command - Word 7

Table 1-20 MASS_ERASE_7 Register Field Descriptions
BitFieldTypeResetDescription
31-0MASS_ERASE_7R/W0hPassword for DSSM_BC_MASS_ERASE_REQUEST command - Word 7

1.4.2.15 FACTORY_RESET_0 Register (Offset = 60100838h) [Reset = 00000000h]

FACTORY_RESET_0 is shown in Table 1-21.

Return to the Summary Table.

Password for factory reset command - Word 0

Table 1-21 FACTORY_RESET_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0FACTORY_RESET_0R/W0hPassword for factory reset command - Word 0

1.4.2.16 FACTORY_RESET_1 Register (Offset = 6010083Ch) [Reset = 00000000h]

FACTORY_RESET_1 is shown in Table 1-22.

Return to the Summary Table.

Password for factory reset command - Word 1

Table 1-22 FACTORY_RESET_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0FACTORY_RESET_1R/W0hPassword for factory reset command - Word 1

1.4.2.17 FACTORY_RESET_2 Register (Offset = 60100840h) [Reset = 00000000h]

FACTORY_RESET_2 is shown in Table 1-23.

Return to the Summary Table.

Password for factory reset command - Word 2

Table 1-23 FACTORY_RESET_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0FACTORY_RESET_2R/W0hPassword for factory reset command - Word 2

1.4.2.18 FACTORY_RESET_3 Register (Offset = 60100844h) [Reset = 00000000h]

FACTORY_RESET_3 is shown in Table 1-24.

Return to the Summary Table.

Password for factory reset command - Word 3

Table 1-24 FACTORY_RESET_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0FACTORY_RESET_3R/W0hPassword for factory reset command - Word 3

1.4.2.19 FACTORY_RESET_4 Register (Offset = 60100848h) [Reset = 00000000h]

FACTORY_RESET_4 is shown in Table 1-25.

Return to the Summary Table.

Password for factory reset command - Word 4

Table 1-25 FACTORY_RESET_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0FACTORY_RESET_4R/W0hPassword for factory reset command - Word 4

1.4.2.20 FACTORY_RESET_5 Register (Offset = 6010084Ch) [Reset = 00000000h]

FACTORY_RESET_5 is shown in Table 1-26.

Return to the Summary Table.

Password for factory reset command - Word 5

Table 1-26 FACTORY_RESET_5 Register Field Descriptions
BitFieldTypeResetDescription
31-0FACTORY_RESET_5R/W0hPassword for factory reset command - Word 5

1.4.2.21 FACTORY_RESET_6 Register (Offset = 60100850h) [Reset = 00000000h]

FACTORY_RESET_6 is shown in Table 1-27.

Return to the Summary Table.

Password for factory reset command - Word 6

Table 1-27 FACTORY_RESET_6 Register Field Descriptions
BitFieldTypeResetDescription
31-0FACTORY_RESET_6R/W0hPassword for factory reset command - Word 6

1.4.2.22 FACTORY_RESET_7 Register (Offset = 60100854h) [Reset = 00000000h]

FACTORY_RESET_7 is shown in Table 1-28.

Return to the Summary Table.

Password for factory reset command - Word 7

Table 1-28 FACTORY_RESET_7 Register Field Descriptions
BitFieldTypeResetDescription
31-0FACTORY_RESET_7R/W0hPassword for factory reset command - Word 7

1.4.2.23 DEBUG_LOCK_0 Register (Offset = 60100858h) [Reset = 00000000h]

DEBUG_LOCK_0 is shown in Table 1-29.

Return to the Summary Table.

Password for debug access authentication - Word 0

Table 1-29 DEBUG_LOCK_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_LOCK_0R/W0hPassword for debug access authentication - Word 0

1.4.2.24 DEBUG_LOCK_1 Register (Offset = 6010085Ch) [Reset = 00000000h]

DEBUG_LOCK_1 is shown in Table 1-30.

Return to the Summary Table.

Password for debug access authentication - Word 1

Table 1-30 DEBUG_LOCK_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_LOCK_1R/W0hPassword for debug access authentication - Word 1

1.4.2.25 DEBUG_LOCK_2 Register (Offset = 60100860h) [Reset = 00000000h]

DEBUG_LOCK_2 is shown in Table 1-31.

Return to the Summary Table.

Password for debug access authentication - Word 2

Table 1-31 DEBUG_LOCK_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_LOCK_2R/W0hPassword for debug access authentication - Word 2

1.4.2.26 DEBUG_LOCK_3 Register (Offset = 60100864h) [Reset = 00000000h]

DEBUG_LOCK_3 is shown in Table 1-32.

Return to the Summary Table.

Password for debug access authentication - Word 3

Table 1-32 DEBUG_LOCK_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_LOCK_3R/W0hPassword for debug access authentication - Word 3

1.4.2.27 DEBUG_LOCK_4 Register (Offset = 60100868h) [Reset = 00000000h]

DEBUG_LOCK_4 is shown in Table 1-33.

Return to the Summary Table.

Password for debug access authentication - Word 4

Table 1-33 DEBUG_LOCK_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_LOCK_4R/W0hPassword for debug access authentication - Word 4

1.4.2.28 DEBUG_LOCK_5 Register (Offset = 6010086Ch) [Reset = 00000000h]

DEBUG_LOCK_5 is shown in Table 1-34.

Return to the Summary Table.

Password for debug access authentication - Word 5

Table 1-34 DEBUG_LOCK_5 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_LOCK_5R/W0hPassword for debug access authentication - Word 5

1.4.2.29 DEBUG_LOCK_6 Register (Offset = 60100870h) [Reset = 00000000h]

DEBUG_LOCK_6 is shown in Table 1-35.

Return to the Summary Table.

Password for debug access authentication - Word 6

Table 1-35 DEBUG_LOCK_6 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_LOCK_6R/W0hPassword for debug access authentication - Word 6

1.4.2.30 DEBUG_LOCK_7 Register (Offset = 60100874h) [Reset = 00000000h]

DEBUG_LOCK_7 is shown in Table 1-36.

Return to the Summary Table.

Password for debug access authentication - Word 7

Table 1-36 DEBUG_LOCK_7 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_LOCK_7R/W0hPassword for debug access authentication - Word 7

1.4.2.31 DEBUG_NS_LOCK_0 Register (Offset = 60100878h) [Reset = 00000000h]

DEBUG_NS_LOCK_0 is shown in Table 1-37.

Return to the Summary Table.

Password for non-secure debug access - Word 0

Table 1-37 DEBUG_NS_LOCK_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_NS_LOCK_0R/W0hPassword for non-secure debug access - Word 0

1.4.2.32 DEBUG_NS_LOCK_1 Register (Offset = 6010087Ch) [Reset = 00000000h]

DEBUG_NS_LOCK_1 is shown in Table 1-38.

Return to the Summary Table.

Password for non-secure debug access - Word 1

Table 1-38 DEBUG_NS_LOCK_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_NS_LOCK_1R/W0hPassword for non-secure debug access - Word 1

1.4.2.33 DEBUG_NS_LOCK_2 Register (Offset = 60100880h) [Reset = 00000000h]

DEBUG_NS_LOCK_2 is shown in Table 1-39.

Return to the Summary Table.

Password for non-secure debug access - Word 2

Table 1-39 DEBUG_NS_LOCK_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_NS_LOCK_2R/W0hPassword for non-secure debug access - Word 2

1.4.2.34 DEBUG_NS_LOCK_3 Register (Offset = 60100884h) [Reset = 00000000h]

DEBUG_NS_LOCK_3 is shown in Table 1-40.

Return to the Summary Table.

Password for non-secure debug access - Word 3

Table 1-40 DEBUG_NS_LOCK_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_NS_LOCK_3R/W0hPassword for non-secure debug access - Word 3

1.4.2.35 DEBUG_NS_LOCK_4 Register (Offset = 60100888h) [Reset = 00000000h]

DEBUG_NS_LOCK_4 is shown in Table 1-41.

Return to the Summary Table.

Password for non-secure debug access - Word 4

Table 1-41 DEBUG_NS_LOCK_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_NS_LOCK_4R/W0hPassword for non-secure debug access - Word 4

1.4.2.36 DEBUG_NS_LOCK_5 Register (Offset = 6010088Ch) [Reset = 00000000h]

DEBUG_NS_LOCK_5 is shown in Table 1-42.

Return to the Summary Table.

Password for non-secure debug access - Word 5

Table 1-42 DEBUG_NS_LOCK_5 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_NS_LOCK_5R/W0hPassword for non-secure debug access - Word 5

1.4.2.37 DEBUG_NS_LOCK_6 Register (Offset = 60100890h) [Reset = 00000000h]

DEBUG_NS_LOCK_6 is shown in Table 1-43.

Return to the Summary Table.

Password for non-secure debug access - Word 6

Table 1-43 DEBUG_NS_LOCK_6 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_NS_LOCK_6R/W0hPassword for non-secure debug access - Word 6

1.4.2.38 DEBUG_NS_LOCK_7 Register (Offset = 60100894h) [Reset = 00000000h]

DEBUG_NS_LOCK_7 is shown in Table 1-44.

Return to the Summary Table.

Password for non-secure debug access - Word 7

Table 1-44 DEBUG_NS_LOCK_7 Register Field Descriptions
BitFieldTypeResetDescription
31-0DEBUG_NS_LOCK_7R/W0hPassword for non-secure debug access - Word 7

1.4.2.39 SECURE_BOOT_MODE Register (Offset = 601008B8h) [Reset = 00000000h]

SECURE_BOOT_MODE is shown in Table 1-45.

Return to the Summary Table.

Controls application authentication; Reserved field

Table 1-45 SECURE_BOOT_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved field
15-0SECURE_BOOT_MODER/W0hControls application authentication
  • AABBh = BC_CFG_SECURE_BOOT_CRC_EN configuration
  • FFFFh = DISABLED configuration

1.4.2.40 USER_SECURE_APP_START_ADDR Register (Offset = 601008BCh) [Reset = 00000000h]

USER_SECURE_APP_START_ADDR is shown in Table 1-46.

Return to the Summary Table.

Starting address for secure application

Table 1-46 USER_SECURE_APP_START_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0USER_SECURE_APP_START_ADDRR/W0hStarting address for secure application

1.4.2.41 USER_SECURE_APP_LENGTH Register (Offset = 601008C0h) [Reset = 00000000h]

USER_SECURE_APP_LENGTH is shown in Table 1-47.

Return to the Summary Table.

Length of secure application

Table 1-47 USER_SECURE_APP_LENGTH Register Field Descriptions
BitFieldTypeResetDescription
31-0USER_SECURE_APP_LENGTHR/W0hLength of secure application

1.4.2.42 USER_SECURE_APP_CRC_0 Register (Offset = 601008C4h) [Reset = 00000000h]

USER_SECURE_APP_CRC_0 is shown in Table 1-48.

Return to the Summary Table.

Secure application CRC - Word 0

Table 1-48 USER_SECURE_APP_CRC_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0USER_SECURE_APP_CRC_0R/W0hSecure application CRC - Word 0

1.4.2.43 BANK0_NM_USER_CONFIG Register (Offset = 601008E4h) [Reset = 00000000h]

BANK0_NM_USER_CONFIG is shown in Table 1-49.

Return to the Summary Table.

User Config Non Main Flash Static Write Protection. WEP_DISABLE=0xAABB; Reserved field

Table 1-49 BANK0_NM_USER_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved field
15-0BANK0_NM_USER_CONFIGR/W0hUser Config Non Main Flash Static Write Protection. WEP_DISABLE=0xAABB

1.4.2.44 BANK0_WRITE_ERASE_PROTECTION_A Register (Offset = 601008E8h) [Reset = 00000000h]

BANK0_WRITE_ERASE_PROTECTION_A is shown in Table 1-50.

Return to the Summary Table.

Write protection for first 32 sectors

Table 1-50 BANK0_WRITE_ERASE_PROTECTION_A Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK0_WRITE_ERASE_PROTECTION_AR/W0hWrite protection for first 32 sectors

1.4.2.45 BANK0_WRITE_ERASE_PROTECTION_B Register (Offset = 601008ECh) [Reset = 00000000h]

BANK0_WRITE_ERASE_PROTECTION_B is shown in Table 1-51.

Return to the Summary Table.

Write Protection for 512KB-64KB

Table 1-51 BANK0_WRITE_ERASE_PROTECTION_B Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK0_WRITE_ERASE_PROTECTION_BR/W0hWrite Protection for 512KB-64KB

1.4.2.46 BANK0_SECURITY_PROTECTION_A Register (Offset = 601008F0h) [Reset = 00000000h]

BANK0_SECURITY_PROTECTION_A is shown in Table 1-52.

Return to the Summary Table.

Security protection for first 32 sectors

Table 1-52 BANK0_SECURITY_PROTECTION_A Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK0_SECURITY_PROTECTION_AR/W0hSecurity protection for first 32 sectors

1.4.2.47 BANK0_SECURITY_PROTECTION_B Register (Offset = 601008F4h) [Reset = 00000000h]

BANK0_SECURITY_PROTECTION_B is shown in Table 1-53.

Return to the Summary Table.

Security protection for 512KB-64KB

Table 1-53 BANK0_SECURITY_PROTECTION_B Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK0_SECURITY_PROTECTION_BR/W0hSecurity protection for 512KB-64KB

1.4.2.48 BANK0_PRIVILEGE_PROTECTION_A Register (Offset = 601008F8h) [Reset = 00000000h]

BANK0_PRIVILEGE_PROTECTION_A is shown in Table 1-54.

Return to the Summary Table.

Privilege protection for first 32 sectors

Table 1-54 BANK0_PRIVILEGE_PROTECTION_A Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK0_PRIVILEGE_PROTECTION_AR/W0hPrivilege protection for first 32 sectors

1.4.2.49 BANK0_PRIVILEGE_PROTECTION_B Register (Offset = 601008FCh) [Reset = 00000000h]

BANK0_PRIVILEGE_PROTECTION_B is shown in Table 1-55.

Return to the Summary Table.

Privilege protection for 512KB-64KB

Table 1-55 BANK0_PRIVILEGE_PROTECTION_B Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK0_PRIVILEGE_PROTECTION_BR/W0hPrivilege protection for 512KB-64KB

1.4.2.50 BANK1_WRITE_ERASE_PROTECTION_A Register (Offset = 60100904h) [Reset = 00000000h]

BANK1_WRITE_ERASE_PROTECTION_A is shown in Table 1-56.

Return to the Summary Table.

Write protection for first 32 sectors

Table 1-56 BANK1_WRITE_ERASE_PROTECTION_A Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK1_WRITE_ERASE_PROTECTION_AR/W0hWrite protection for first 32 sectors

1.4.2.51 BANK1_WRITE_ERASE_PROTECTION_B Register (Offset = 60100908h) [Reset = 00000000h]

BANK1_WRITE_ERASE_PROTECTION_B is shown in Table 1-57.

Return to the Summary Table.

Write Protection for 512KB-64KB

Table 1-57 BANK1_WRITE_ERASE_PROTECTION_B Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK1_WRITE_ERASE_PROTECTION_BR/W0hWrite Protection for 512KB-64KB

1.4.2.52 BANK1_SECURITY_PROTECTION_A Register (Offset = 6010090Ch) [Reset = 00000000h]

BANK1_SECURITY_PROTECTION_A is shown in Table 1-58.

Return to the Summary Table.

Security protection for first 32 sectors

Table 1-58 BANK1_SECURITY_PROTECTION_A Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK1_SECURITY_PROTECTION_AR/W0hSecurity protection for first 32 sectors

1.4.2.53 BANK1_SECURITY_PROTECTION_B Register (Offset = 60100910h) [Reset = 00000000h]

BANK1_SECURITY_PROTECTION_B is shown in Table 1-59.

Return to the Summary Table.

Security protection for 512KB-64KB

Table 1-59 BANK1_SECURITY_PROTECTION_B Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK1_SECURITY_PROTECTION_BR/W0hSecurity protection for 512KB-64KB

1.4.2.54 BANK1_PRIVILEGE_PROTECTION_A Register (Offset = 60100914h) [Reset = 00000000h]

BANK1_PRIVILEGE_PROTECTION_A is shown in Table 1-60.

Return to the Summary Table.

Privilege protection for first 32 sectors

Table 1-60 BANK1_PRIVILEGE_PROTECTION_A Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK1_PRIVILEGE_PROTECTION_AR/W0hPrivilege protection for first 32 sectors

1.4.2.55 BANK1_PRIVILEGE_PROTECTION_B Register (Offset = 60100918h) [Reset = 00000000h]

BANK1_PRIVILEGE_PROTECTION_B is shown in Table 1-61.

Return to the Summary Table.

Privilege protection for 512KB-64KB

Table 1-61 BANK1_PRIVILEGE_PROTECTION_B Register Field Descriptions
BitFieldTypeResetDescription
31-0BANK1_PRIVILEGE_PROTECTION_BR/W0hPrivilege protection for 512KB-64KB

1.4.2.56 BOOTCLK0 Register (Offset = 60100930h) [Reset = 00000000h]

BOOTCLK0 is shown in Table 1-62.

Return to the Summary Table.

Clock configuration; PLL multiplier value; PLL divider value; PLL clock source configuration

Table 1-62 BOOTCLK0 Register Field Descriptions
BitFieldTypeResetDescription
31-24SYSPLL_SOURCER/W0hPLL clock source configuration
  • AAh = BC_CFG_PLL_SOURCE_XTAL_20MHZ configuration
  • FFh = DEFAULT configuration
23-16SYSPLL_CONFIG_RDIVR/W0hPLL divider value
15-8SYSPLL_CONFIG_QDIVR/W0hPLL multiplier value
7-0SYSPLL_CONFIGR/W0hClock configuration
  • AAh = PLL_80 configuration
  • BBh = PLL_CUSTOM configuration
  • FFh = NOPLL configuration

1.4.2.57 BOOTCLK1 Register (Offset = 60100934h) [Reset = 00000000h]

BOOTCLK1 is shown in Table 1-63.

Return to the Summary Table.

CPU delay cycles for PLL settling time; CPU delay cycles for XTAL monitoring; Reserved configuration field 0

Table 1-63 BOOTCLK1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESVD_0R/W0hReserved configuration field 0
15-8XTAL_STARTUP_MONITOR_TIMER/W0hCPU delay cycles for XTAL monitoring
7-0SYSPLL_SETTLING_TIMER/W0hCPU delay cycles for PLL settling time

1.4.2.58 CRC Register (Offset = 6010094Ch) [Reset = 00000000h]

CRC is shown in Table 1-64.

Return to the Summary Table.

JAMCRC of BCR config structure

Table 1-64 CRC Register Field Descriptions
BitFieldTypeResetDescription
31-0CRCR/W0hCRC-32 of BCR config structure

1.4.2.59 BSL_CONFIG_ID Register (Offset = 60100C00h) [Reset = 00000000h]

BSL_CONFIG_ID is shown in Table 1-65.

Return to the Summary Table.

Predetermined Bootloader config signature ID

Table 1-65 BSL_CONFIG_ID Register Field Descriptions
BitFieldTypeResetDescription
31-0BSL_CONFIG_IDR/W0hPredetermined Bootloader config signature ID

1.4.2.60 BSLPINCFG0 Register (Offset = 60100C04h) [Reset = 00000000h]

BSLPINCFG0 is shown in Table 1-66.

Return to the Summary Table.

UART receive pin number configuration; UART receive pin multiplexer selection; UART transmit pin number configuration; UART transmit pin multiplexer selection

Table 1-66 BSLPINCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-24UART_TXD_PF_MUX_SELR/W0hUART transmit pin multiplexer selection
23-16UART_TXD_PAD_NUMR/W0hUART transmit pin number configuration
15-8UART_RXD_PF_MUX_SELR/W0hUART receive pin multiplexer selection
7-0UART_RXD_PAD_NUMR/W0hUART receive pin number configuration

1.4.2.61 BSLPINCFG1 Register (Offset = 60100C08h) [Reset = 00000000h]

BSLPINCFG1 is shown in Table 1-67.

Return to the Summary Table.

I2C data pin number configuration; I2C data pin multiplexer selection; I2C clock pin number configuration; I2C clock pin multiplexer selection

Table 1-67 BSLPINCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-24I2C_SCL_PF_MUX_SELR/W0hI2C clock pin multiplexer selection
23-16I2C_SCL_PAD_NUMR/W0hI2C clock pin number configuration
15-8I2C_SDA_PF_MUX_SELR/W0hI2C data pin multiplexer selection
7-0I2C_SDA_PAD_NUMR/W0hI2C data pin number configuration

1.4.2.62 BSLPINCFG2 Register (Offset = 60100C0Ch) [Reset = 00000000h]

BSLPINCFG2 is shown in Table 1-68.

Return to the Summary Table.

MCAN receive pin number configuration; MCAN receive pin multiplexer selection; MCAN transmit pin number configuration; MCAN transmit pin multiplexer selection

Table 1-68 BSLPINCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-24MCAN_TX_PF_MUX_SELR/W0hMCAN transmit pin multiplexer selection
23-16MCAN_TX_PAD_NUMR/W0hMCAN transmit pin number configuration
15-8MCAN_RX_PF_MUX_SELR/W0hMCAN receive pin multiplexer selection
7-0MCAN_RX_PAD_NUMR/W0hMCAN receive pin number configuration

1.4.2.63 BSLCONFIG0 Register (Offset = 60100C10h) [Reset = 00000000h]

BSLCONFIG0 is shown in Table 1-69.

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BSL invoke pin configuration data 0; BSL invoke pin configuration data 1; Memory readout control. ENABLE allows memory read operations

Table 1-69 BSLCONFIG0 Register Field Descriptions
BitFieldTypeResetDescription
31-16READOUTR/W0hMemory readout control. ENABLE allows memory read operations
15-8PIN_DATA_1R/W0hBSL invoke pin configuration data 1
7-0PIN_DATA_0R/W0hBSL invoke pin configuration data 0

1.4.2.64 PASSWORD_0 Register (Offset = 60100C14h) [Reset = 00000000h]

PASSWORD_0 is shown in Table 1-70.

Return to the Summary Table.

BSL access password - Word 0

Table 1-70 PASSWORD_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORD_0R/W0hBSL access password - Word 0

1.4.2.65 PASSWORD_1 Register (Offset = 60100C18h) [Reset = 00000000h]

PASSWORD_1 is shown in Table 1-71.

Return to the Summary Table.

BSL access password - Word 1

Table 1-71 PASSWORD_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORD_1R/W0hBSL access password - Word 1

1.4.2.66 PASSWORD_2 Register (Offset = 60100C1Ch) [Reset = 00000000h]

PASSWORD_2 is shown in Table 1-72.

Return to the Summary Table.

BSL access password - Word 2

Table 1-72 PASSWORD_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORD_2R/W0hBSL access password - Word 2

1.4.2.67 PASSWORD_3 Register (Offset = 60100C20h) [Reset = 00000000h]

PASSWORD_3 is shown in Table 1-73.

Return to the Summary Table.

BSL access password - Word 3

Table 1-73 PASSWORD_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORD_3R/W0hBSL access password - Word 3

1.4.2.68 PASSWORD_4 Register (Offset = 60100C24h) [Reset = 00000000h]

PASSWORD_4 is shown in Table 1-74.

Return to the Summary Table.

BSL access password - Word 4

Table 1-74 PASSWORD_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORD_4R/W0hBSL access password - Word 4

1.4.2.69 PASSWORD_5 Register (Offset = 60100C28h) [Reset = 00000000h]

PASSWORD_5 is shown in Table 1-75.

Return to the Summary Table.

BSL access password - Word 5

Table 1-75 PASSWORD_5 Register Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORD_5R/W0hBSL access password - Word 5

1.4.2.70 PASSWORD_6 Register (Offset = 60100C2Ch) [Reset = 00000000h]

PASSWORD_6 is shown in Table 1-76.

Return to the Summary Table.

BSL access password - Word 6

Table 1-76 PASSWORD_6 Register Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORD_6R/W0hBSL access password - Word 6

1.4.2.71 PASSWORD_7 Register (Offset = 60100C30h) [Reset = 00000000h]

PASSWORD_7 is shown in Table 1-77.

Return to the Summary Table.

BSL access password - Word 7

Table 1-77 PASSWORD_7 Register Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORD_7R/W0hBSL access password - Word 7

1.4.2.72 APP_REV_POINTER Register (Offset = 60100C34h) [Reset = 00000000h]

APP_REV_POINTER is shown in Table 1-78.

Return to the Summary Table.

Pointer to application version information in MAIN flash

Table 1-78 APP_REV_POINTER Register Field Descriptions
BitFieldTypeResetDescription
31-0APP_REV_POINTERR/W0hPointer to application version information in MAIN flash

1.4.2.73 BSLCONFIG1 Register (Offset = 60100C38h) [Reset = 00000000h]

BSLCONFIG1 is shown in Table 1-79.

Return to the Summary Table.

Security alert response: Factory Reset/Disable BSL/Ignore; UART communication speed selection for ROM BSL

Table 1-79 BSLCONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31-16UART_BAUD_RATER/W0hUART communication speed selection for ROM BSL
  • 1h = BAUDRATE_4800 configuration
  • 2h = BAUDRATE_9600 configuration
  • 3h = BAUDRATE_19200 configuration
  • 4h = BAUDRATE_38400 configuration
  • 5h = BAUDRATE_57600 configuration
  • 6h = BAUDRATE_115200 configuration
  • 7h = BAUDRATE_1000000 configuration
  • 8h = BAUDRATE_2000000 configuration
  • 9h = BAUDRATE_3000000 configuration
15-0SECURITY_ALERT_LEVELR/W0hSecurity alert response: Factory Reset/Disable BSL/Ignore
  • AABBh = FACTORY_RESET configuration
  • CCDDh = DISABLE_BSL configuration
  • FFFFh = DO_NOTHING configuration

1.4.2.74 I2C_SLAVE_ADDR Register (Offset = 60100C3Ch) [Reset = 00000000h]

I2C_SLAVE_ADDR is shown in Table 1-80.

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I2C slave address for ROM BSL I2C interface; Reserved field; Reserved field

Table 1-80 I2C_SLAVE_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved field
23-16RESERVEDR0hReserved field
15-0I2C_SLAVE_ADDRR/W0hI2C slave address for ROM BSL I2C interface