SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

9.3.2 DMA_REGS Registers

Table 9-10 lists the memory-mapped registers for the DMA_REGS registers. All register offset addresses not listed in Table 9-10 should be considered as reserved locations and the register contents should not be modified.

Table 9-10 DMA_REGS Registers
OffsetAcronymRegister NameSection
1018hPDBGCTLPeripheral Debug ControlGo
1020hIIDXInterrupt indexGo
1028hIMASKInterrupt maskGo
1030hRISRaw interrupt statusGo
1038hMISMasked interrupt statusGo
1040hISETInterrupt setGo
1048hICLRInterrupt clearGo
10E0hEVT_MODEEvent ModeGo
10FChDESCModule DescriptionGo
1100hDMAPRIODMA Channel Priority Control
Go
1110h + formulaDMATCTL_jDMA Trigger SelectGo
1200h + formulaDMACTL_jDMA Channel ControlGo
1204h + formulaDMASA_jDMA Channel Source AddressGo
1208h + formulaDMADA_jDMA Channel Destination AddressGo
120Ch + formulaDMASZ_jDMA Channel SizeGo

Complex bit access types are encoded to fit into small table cells. Table 9-11 shows the codes that are used for access types in this section.

Table 9-11 DMA_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

9.3.2.1 PDBGCTL Register (Offset = 1018h) [Reset = 00000000h]

PDBGCTL is shown in Figure 9-5 and described in Table 9-12.

Return to the Summary Table.

This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 9-5 PDBGCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSOFTFREE
R/W-0hR/W-0hR/W-0h
Table 9-12 PDBGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1SOFTR/W1hSoft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0FREER/W1hFree run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

9.3.2.2 IIDX Register (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 9-6 and described in Table 9-13.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, . . . IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS [RIS] and MIS [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Note: The number of DMACH is device dependent. Please consult the datasheet of the specific device to map which channel number is implemented.

Figure 9-6 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 9-13 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No bit is set means there is no pending interrupt request
01h = DMA Channel 0 size counter reached zero (DMASZ=0).
02h = DMA Channel 1 size counter reached zero (DMASZ=0).
03h = DMA Channel 2 size counter reached zero (DMASZ=0).
04h = DMA Channel 3 size counter reached zero (DMASZ=0).
05h = DMA Channel 4 size counter reached zero (DMASZ=0).
06h = DMA Channel 5 size counter reached zero (DMASZ=0).
07h = DMA Channel 6 size counter reached zero (DMASZ=0).
08h = DMA Channel 7 size counter reached zero (DMASZ=0).
09h = DMA Channel 8 size counter reached zero (DMASZ=0).
0Ah = DMA Channel 9 size counter reached zero (DMASZ=0).
0Bh = DMA Channel 10 size counter reached zero (DMASZ=0).
0Ch = DMA Channel 11 size counter reached zero (DMASZ=0).
0Dh = DMA Channel 12 size counter reached zero (DMASZ=0).
0Eh = DMA Channel 13 size counter reached zero (DMASZ=0).
0Fh = DMA Channel 14 size counter reached zero (DMASZ=0).
10h = DMA Channel 15 size counter reached zero (DMASZ=0).
11h = PRE-IRQ event for DMA Channel 0.
12h = PRE-IRQ event for DMA Channel 1.
13h = PRE-IRQ event for DMA Channel 2.
14h = PRE-IRQ event for DMA Channel 3.
15h = PRE-IRQ event for DMA Channel 4.
16h = PRE-IRQ event for DMA Channel 5.
17h = PRE-IRQ event for DMA Channel 6.
18h = PRE-IRQ event for DMA Channel 7.
19h = DMA address error, SRC address not reachable.

9.3.2.3 IMASK Register (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 9-7 and described in Table 9-14.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then the corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX [IIDX], as well as MIS [MIS].

Note: The number of DMACH is device dependent. Please consult the datasheet of the specific device to map which channel number is implemented.

Figure 9-7 IMASK Register
3130292827262524
RESERVEDRESERVEDADDRERR
R/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDPREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-14 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/W0h
25RESERVEDR/W0hReserved
24ADDRERRR/W0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21PREIRQCH5R/W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R/W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R/W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R/W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R/W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R/W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R/W0hDMA Channel 15 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
14DMACH14R/W0hDMA Channel 14 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
13DMACH13R/W0hDMA Channel 13 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
12DMACH12R/W0hDMA Channel 12 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
11DMACH11R/W0hDMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
10DMACH10R/W0hDMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
9DMACH9R/W0hDMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
8DMACH8R/W0hDMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
7DMACH7R/W0hDMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
6DMACH6R/W0hDMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
5DMACH5R/W0hDMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
4DMACH4R/W0hDMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
3DMACH3R/W0hDMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
2DMACH2R/W0hDMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
1DMACH1R/W0hDMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
0DMACH0R/W0hDMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit

9.3.2.4 RIS Register (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 9-8 and described in Table 9-15.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR [ICLR] register bit even if the corresponding IMASK [IMASK] bit is not enabled.

Note: The number of DMACH is device dependent. Please consult the datasheet of the specific device to map which channel number is implemented.

Figure 9-8 RIS Register
3130292827262524
RESERVEDRESERVEDADDRERR
R-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDPREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-15 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25RESERVEDR0hReserved
24ADDRERRR0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23RESERVEDR0hReserved
22RESERVEDR0hReserved
21PREIRQCH5R0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
14DMACH14R0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
13DMACH13R0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
12DMACH12R0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
11DMACH11R0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
10DMACH10R0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
9DMACH9R0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
8DMACH8R0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
7DMACH7R0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
6DMACH6R0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
5DMACH5R0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
4DMACH4R0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
3DMACH3R0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
2DMACH2R0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
1DMACH1R0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
0DMACH0R0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred

9.3.2.5 MIS Register (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 9-9 and described in Table 9-16.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK [IMASK] and RIS [RIS] registers.

Note: The number of DMACH is device dependent. Please consult the datasheet of the specific device to map which channel number is implemented.

Figure 9-9 MIS Register
3130292827262524
RESERVEDRESERVEDADDRERR
R-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDPREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-16 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25RESERVEDR0hReserved
24ADDRERRR0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23RESERVEDR0hReserved
22RESERVEDR0hReserved
21PREIRQCH5R0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
14DMACH14R0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
13DMACH13R0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
12DMACH12R0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
11DMACH11R0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
10DMACH10R0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
9DMACH9R0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
8DMACH8R0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
7DMACH7R0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
6DMACH6R0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
5DMACH5R0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
4DMACH4R0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
3DMACH3R0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
2DMACH2R0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
1DMACH1R0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
0DMACH0R0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred

9.3.2.6 ISET Register (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 9-10 and described in Table 9-17.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS [RIS] bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS [MIS] bit is also set.

Note: The number of DMACH is device dependent. Please consult the datasheet of the specific device to map which channel number is implemented.

Figure 9-10 ISET Register
3130292827262524
RESERVEDRESERVEDADDRERR
W-0hW-0hW-0h
2322212019181716
RESERVEDRESERVEDPREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-17 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDW0h
25RESERVEDW0hReserved
24ADDRERRW0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23RESERVEDW0hReserved
22RESERVEDW0hReserved
21PREIRQCH5W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
14DMACH14W0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
13DMACH13W0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
12DMACH12W0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
11DMACH11W0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
10DMACH10W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
9DMACH9W0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
8DMACH8W0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
7DMACH7W0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
6DMACH6W0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
5DMACH5W0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
4DMACH4W0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
3DMACH3W0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
2DMACH2W0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
1DMACH1W0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
0DMACH0W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt

9.3.2.7 ICLR Register (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 9-11 and described in Table 9-18.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Note: The number of DMACH is device dependent. Please consult the datasheet of the specific device to map which channel number is implemented.

Figure 9-11 ICLR Register
3130292827262524
RESERVEDRESERVEDADDRERR
W-0hW-0hW-0h
2322212019181716
RESERVEDRESERVEDPREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-18 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDW0h
25RESERVEDW0hReserved
24ADDRERRW0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23RESERVEDW0hReserved
22RESERVEDW0hReserved
21PREIRQCH5W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15W0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
14DMACH14W0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
13DMACH13W0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
12DMACH12W0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
11DMACH11W0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
10DMACH10W0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
9DMACH9W0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
8DMACH8W0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
7DMACH7W0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
6DMACH6W0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
5DMACH5W0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
4DMACH4W0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
3DMACH3W0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
2DMACH2W0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
1DMACH1W0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
0DMACH0W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt

9.3.2.8 EVT_MODE Register (Offset = 10E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 9-12 and described in Table 9-19.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 9-12 EVT_MODE Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEVT1_CFGINT0_CFG
R/W-0hR-0hR-0h
Table 9-19 EVT_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-2EVT1_CFGR2hEvent line mode select for event corresponding to generic event GEN_EVENT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0INT0_CFGR1hEvent line mode select for event corresponding to interrupt event CPU_INT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

9.3.2.9 DESC Register (Offset = 10FCh) [Reset = 00000000h]

DESC is shown in Figure 9-13 and described in Table 9-20.

Return to the Summary Table.

This register identifies the peripheral and its exact version.

Figure 9-13 DESC Register
31302928272625242322212019181716
MODULEID
R-0h
1514131211109876543210
FEATUREVERRESERVEDMAJREVMINREV
R-0hR-0hR-0hR-0h
Table 9-20 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR2511hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERRFhFeature Set for the DMA: number of DMA channel minus one (e.g. 0->1ch, 2->3ch, 15->16ch).
0h = Smallest value (1 channel)
Fh = Highest value (16 channel)
11-8RESERVEDR0h
7-4MAJREVR0hMajor rev of the IP
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
0h = Smallest value
Fh = Highest possible value

9.3.2.10 DMAPRIO Register (Offset = 1100h) [Reset = 00000000h]

DMAPRIO is shown in Figure 9-14 and described in Table 9-21.

Return to the Summary Table.

DMA Channel Priority Control

Figure 9-14 DMAPRIO Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDBURSTSZ
R/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDROUNDROBIN
R/W-0hR/W-0h
Table 9-21 DMAPRIO Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0h
17-16BURSTSZR/W0hDefine the burst size of a block transfer, before the priority is re-evaluated
0h = There is no burst size, the whole block transfer is completed on one transfer without interruption
1h = The burst size is 8, after 9 transfers the block transfer is interrupted and the priority is reevaluated
2h = The burst size is 16, after 17 transfers the block transfer is interrupted and the priority is reevaluated
3h = The burst size is 32, after 33 transfers the block transfer is interrupted and the priority is reevaluated
15-1RESERVEDR/W0h
0ROUNDROBINR/W0hRound robin. This bit enables the round-robin DMA channel priorities.
0h = Roundrobin priority disabled, DMA channel priority is fixed: DMA0-DMA1-DMA2-...-DMA16
1h = Roundrobin priority enabled, DMA channel priority changes with each transfer

9.3.2.11 DMATCTL_j Register (Offset = 1110h + formula) [Reset = 00000000h]

DMATCTL_j is shown in Figure 9-15 and described in Table 9-22.

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DMA Trigger Control

Offset = 1110h + (j * 4h); where j = 0h to Fh

Figure 9-15 DMATCTL_j Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
DMATINTDMATSEL
R/W-0hR/W-0h
Table 9-22 DMATCTL_j Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7DMATINTR/W0hDMA Trigger by Internal Channel
0h = DMATSEL will define external trigger select as transfer trigger.
1h = DMATSEL will define internal channel as transfer trigger select. 0-> Channel0-done, 1-> Channel1-done, ...
6-0DMATSELR/W0hDMA Trigger Select

Note: Reference the datasheet of the device to see the specific trigger mapping.
00h = Software trigger request
7Fh = Highest possible value

9.3.2.12 DMACTL_j Register (Offset = 1200h + formula) [Reset = 00000000h]

DMACTL_j is shown in Figure 9-16 and described in Table 9-23.

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DMA Channel Control

Offset = 1200h + (j * 10h); where j = 0h to Fh

Figure 9-16 DMACTL_j Register
3130292827262524
RESERVEDDMATMRESERVEDDMAEM
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
DMADSTINCRDMASRCINCR
R/W-0hR/W-0h
15141312111098
RESERVEDDMADSTWDTHRESERVEDDMASRCWDTH
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDDMAPREIRQDMAAUTOENDMAENDMAREQ
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-23 DMACTL_j Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29-28DMATMR/W0hDMA transfer mode register

Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set.
0h = Single transfer. Each transfers requires a new trigger. When the DMASZ counts down to zero an event can be generated and the DMAEN is cleared.
1h = Block transfer. Each trigger transfers the complete block defined in DMASZ. After the transfer is complete an event can be generated and the DMAEN is cleared.
2h = Repeated single transfer. Each transfers requires a new trigger. When the DMASZ counts down to zero an event can be generated. After the last transfer the DMASA, DMADA, DAMSZ registers are restored to its initial value and the DMAEN stays enabled.
3h = Repeated block transfer. Each trigger transfers the complete block defined in DMASZ. After the last transfer the DMASA, DMADA, DAMSZ registers are restored to its initial value and the DMAEN stays enabled.
27-26RESERVEDR/W0h
25-24DMAEMR/W0hDMA extended mode

Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0.
0h = Normal mode is related to transfers from SRC to DST
1h = Gather mode will read a data from an address table located at SA, and the data is transfered to the DA
2h = Fill mode will copy the SA register content as data to DA
3h = Table mode will read an address and data value from SA and write the data to address
23-20DMADSTINCRR/W0hDMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4.
0h = Address is unchanged (+0)
2h = Decremented by 1 (-1 * DMADSTWDTH)
3h = Incremented by 1 (+1 * DMADSTWDTH)
8h = Stride size 2 (+2 * DMADSTWDTH)
9h = Stride size 3 (+3 * DMADSTWDTH)
Ah = Stride size 4 (+4 * DMADSTWDTH)
Bh = Stride size 5 (+5 * DMADSTWDTH)
Ch = Stride size 6 (+6 * DMADSTWDTH)
Dh = Stride size 7 (+7 * DMADSTWDTH)
Eh = Stride size 8 (+8 * DMADSTWDTH)
Fh = Stride size 9 (+9 * DMADSTWDTH)
19-16DMASRCINCRR/W0hDMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4.
0h = Address is unchanged (+0)
2h = Decremented by 1 (-1 * DMASRCWDTH)
3h = Incremented by 1 (+1 * DMASRCWDTH)
8h = Stride size 2 (+2 * DMASRCWDTH)
9h = Stride size 3 (+3 * DMASRCWDTH)
Ah = Stride size 4 (+4 * DMASRCWDTH)
Bh = Stride size 5 (+5 * DMASRCWDTH)
Ch = Stride size 6 (+6 * DMASRCWDTH)
Dh = Stride size 7 (+7 * DMASRCWDTH)
Eh = Stride size 8 (+8 * DMASRCWDTH)
Fh = Stride size 9 (+9 * DMASRCWDTH)
15RESERVEDR/W0h
14-12DMADSTWDTHR/W0hDMA destination width. This bit selects the destination as a byte, half word, word, long word or long-long word.
0h = Destination data width is BYTE (8-bit)
1h = Destination data width is HALF-WORD (16-bit)
2h = Destination data width is WORD (32-bit)
3h = Destination data width is LONG-WORD (64-bit)
4h = Source data width is LONG-LONG-WORD (128-bit)
11RESERVEDR/W0h
10-8DMASRCWDTHR/W0hDMA source width. This bit selects the source data width as a byte, half word, word, long word or long-long word.
0h = Source data width is BYTE (8-bit)
1h = Source data width is HALF-WORD (16-bit)
2h = Source data width is WORD (32-bit)
3h = Source data width is LONG-WORD (64-bit)
4h = Source data width is LONG-LONG-WORD (128-bit)
7RESERVEDR/W0h
6-4DMAPREIRQR/W0hEnable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete.

Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0.
0h = Pre-IRQ event disabled.
1h = Issure Pre-IRQ event when DMASZ=1
2h = Issure Pre-IRQ event when DMASZ=2
3h = Issure Pre-IRQ event when DMASZ=4
4h = Issure Pre-IRQ event when DMASZ=8
5h = Issure Pre-IRQ event when DMASZ=32
6h = Issure Pre-IRQ event when DMASZ=64
7h = Issure Pre-IRQ event when DMASZ reached the half size point of the original transfer size
3-2DMAAUTOENR/W0hAutomatic DMA channel enable on DMASA, DMADA, DMASZ register write.
If channel is configured as SW trigger (DMATCTL=0), the AUTOEN will set the DMAEN and DMAREQ.
If channel is configured as HW trigger (DMACTL!=0), the AUTOEN will only set the DMAEN.
0h = No automatic DMA enable
1h = Automatic DMA enable on DMASA register write.
2h = Automatic DMA enable on DMADA register write.
3h = Automatic DMA enable on DMASZ register write.
1DMAENR/W0hDMA enable
0h = DMA channel disabled
1h = DMA channel enabled
0DMAREQR/W0hDMA request. Software-controlled DMA start. DMAREQ is reset automatically.

0h = Default read value
1h = DMA transfer request (start DMA)

9.3.2.13 DMASA_j Register (Offset = 1204h + formula) [Reset = 00000000h]

DMASA_j is shown in Figure 9-17 and described in Table 9-24.

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DMA Channel Source Address

Offset = 1204h + (j * 10h); where j = 0h to Fh

Figure 9-17 DMASA_j Register
313029282726252423222120191817161514131211109876543210
ADDR
R/W-0h
Table 9-24 DMASA_j Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hDMA Channel Source Address
0h = Smallest value
FFFFFFFFh = Highest possible value

9.3.2.14 DMADA_j Register (Offset = 1208h + formula) [Reset = 00000000h]

DMADA_j is shown in Figure 9-18 and described in Table 9-25.

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DMA Channel Destination Address

Offset = 1208h + (j * 10h); where j = 0h to Fh

Figure 9-18 DMADA_j Register
313029282726252423222120191817161514131211109876543210
ADDR
R/W-0h
Table 9-25 DMADA_j Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hDMA Channel Destination Address
0h = Smallest value
FFFFFFFFh = Highest possible value

9.3.2.15 DMASZ_j Register (Offset = 120Ch + formula) [Reset = 00000000h]

DMASZ_j is shown in Figure 9-19 and described in Table 9-26.

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DMA Channel Size

Offset = 120Ch + (j * 10h); where j = 0h to Fh

Figure 9-19 DMASZ_j Register
313029282726252423222120191817161514131211109876543210
RESERVEDSIZE
R/W-0hR/W-0h
Table 9-26 DMASZ_j Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0SIZER/W0hDMA Channel Size in number of transfers
0h = Smallest value
FFFFh = Highest possible value