SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

29.2.2 AES_REGS Registers

Table 29-7 lists the memory-mapped registers for the AES_REGS registers. All register offset addresses not listed in Table 29-7 should be considered as reserved locations and the register contents should not be modified.

Table 29-7 AES_REGS Registers
OffsetAcronymRegister NameSection
480hCPU_CONNECT_0CPU ConnectGo
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
814hSTATStatus RegisterGo
1018hPDBGCTLPeripheral Debug ControlGo
1020hIIDXInterrupt Index RegisterGo
1028hIMASKInterrupt maskGo
1030hRISRaw interrupt statusGo
1038hMISMasked interrupt statusGo
1040hISETInterrupt setGo
1048hICLRInterrupt clearGo
1050hIIDXInterrupt Index RegisterGo
1058hIMASKInterrupt maskGo
1060hRISRaw interrupt statusGo
1068hMISMasked interrupt statusGo
1070hISETInterrupt setGo
1078hICLRInterrupt clearGo
1080hIIDXInterrupt Index RegisterGo
1088hIMASKInterrupt maskGo
1090hRISRaw interrupt statusGo
1098hMISMasked interrupt statusGo
10A0hISETInterrupt setGo
10A8hICLRInterrupt clearGo
10E0hEVT_MODEEvent ModeGo
1100hGCMCCM_TAG0CBC-MAC third key (LSW) / GCM & CCM Intermediate TAG (LSW)Go
1104hGCMCCM_TAG1CBC-MAC third key / GCM & CCM Intermediate TAGGo
1108hGCMCCM_TAG2CBC-MAC third key / GCM & CCM Intermediate TAGGo
110ChGCMCCM_TAG3CBC-MAC third key (MSW) / GCM & CCM Intermediate TAG (MSW)Go
1110hGHASH_H0CCM & CBC-MAC second key (LSW) / GCM Hash Key input (LSW)Go
1114hGHASH_H1CCM & CBC-MAC second key / GCM Hash Key inputGo
1118hGHASH_H2CCM & CBC-MAC second key / GCM Hash Key inputGo
111ChGHASH_H3CCM & CBC-MAC second key (MSW) / GCM Hash Key input (MSW)Go
1120hKEY0KEY (LSW)Go
1124hKEY1KEYGo
1128hKEY2KEYGo
112ChKEY3KEYGo
1130hKEY4KEYGo
1134hKEY5KEYGo
1138hKEY6KEYGo
113ChKEY7KEY (MSW)Go
1140hIV0IV (LSW)Go
1144hIV1IVGo
1148hIV2IVGo
114ChIV3IVGo
1150hCTRLInput/Output Buffer Control and Mode selectionGo
1154hC_LENGTH_0Crypto data length (LSW)Go
1158hC_LENGTH_1Crypto data length (MSW)Go
115ChAAD_LENGTHAAD Data LengthGo
1160hDATA0Data input (LSW) / Data output (LSW)Go
1164hDATA1Data input / Data outputGo
1168hDATA2Data input / Data outputGo
116ChDATA3Data input (LSW) / Data output (MSW)Go
1170hTAG0Hash result (LSW)Go
1174hTAG1Hash resultGo
1178hTAG2Hash resultGo
117ChTAG3Hash result (MSW)Go
1180hSTATUSStatusGo
1184hDATA_INData in alias registerGo
1188hDATA_OUTData out alias registerGo
11D0hFORCE_IN_AVData control register for input dataGo
11D4hCCM_ALN_WRDAES-CCM AAD alignment data wordGo
11D8hBLK_CNT0Internal block counter (LSW)Go
11DChBLK_CNT1Internal block counter (MSW)Go
11F4hDMA_HSControl register for DMA handshakingGo

Complex bit access types are encoded to fit into small table cells. Table 29-8 shows the codes that are used for access types in this section.

Table 29-8 AES_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value

29.2.2.1 CPU_CONNECT_0 Register (Offset = 480h) [Reset = 00000000h]

CPU_CONNECT_0 is shown in Figure 29-11 and described in Table 29-9.

Return to the Summary Table.

Directly connect peripheral publisher port to application processor

Figure 29-11 CPU_CONNECT_0 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
Table 29-9 CPU_CONNECT_0 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1RESERVEDR/W0hReserved
0RESERVEDR/W0h

29.2.2.2 PWREN Register (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 29-12 and described in Table 29-10.

Return to the Summary Table.

Register to control the power state

Figure 29-12 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE
R/W-0hR/WK-0h
Table 29-10 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR/W0h
0ENABLER/WK0hEnable the power

[EXT_GPRCM.GPRCM.PWREN.KEY] must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

29.2.2.3 RSTCTL Register (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 29-13 and described in Table 29-11.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 29-13 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-0hWK-0hWK-0h
Table 29-11 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDW0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

[EXT_GPRCM.GPRCM.RSTCTL.KEY] must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

[EXT_GPRCM.GPRCM.RSTCTL.KEY] must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

29.2.2.4 STAT Register (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 29-14 and described in Table 29-12.

Return to the Summary Table.

peripheral enable and reset status

Figure 29-14 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 29-12 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

29.2.2.5 PDBGCTL Register (Offset = 1018h) [Reset = 00000000h]

PDBGCTL is shown in Figure 29-15 and described in Table 29-13.

Return to the Summary Table.

AES can not be halted when the core is halted. In order to halt the AES, the DMA shall be halted.
This achieves the same effect as a halt feature in the AES: when the AES submits the next DMA trigger, if the DMA is halted, then the AES will automatically halt.

Figure 29-15 PDBGCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDFREE
R-0hR-0h
Table 29-13 PDBGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0FREER1hFree run control
1h = The peripheral ignores the state of the Core Halted input

29.2.2.6 IIDX Register (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 29-16 and described in Table 29-14.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, ... IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 29-16 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 29-14 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
1h = This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
2h = This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
3h = This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the 'save_context' bit is set to '1b'. The bit is mutually exclusive with the 'context_ready' bit.
4h = This bit indicates that the context data registers can be overwritten, and the CPU is permitted to write new context.

29.2.2.7 IMASK Register (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 29-17 and described in Table 29-15.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 29-17 IMASK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 29-15 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3CNTXTRDYR/W0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2SAVEDCNTXTRDYR/W0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the 'save_context' bit is set to '1b'. The bit is mutually exclusive with the 'context_ready' bit.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1INPUTRDYR/W0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0OUTPUTRDYR/W0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask

29.2.2.8 RIS Register (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 29-18 and described in Table 29-16.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 29-18 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
R-0hR-0hR-0hR-0hR-0h
Table 29-16 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3CNTXTRDYR0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2SAVEDCNTXTRDYR0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the 'save_context' bit is set to '1b'. The bit is mutually exclusive with the 'context_ready' bit.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1INPUTRDYR0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0OUTPUTRDYR0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Interrupt did not occur
1h = Interrupt occured

29.2.2.9 MIS Register (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 29-19 and described in Table 29-17.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 29-19 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
R-0hR-0hR-0hR-0hR-0h
Table 29-17 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3CNTXTRDYR0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2SAVEDCNTXTRDYR0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the 'save_context' bit is set to '1b'. The bit is mutually exclusive with the 'context_ready' bit.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1INPUTRDYR0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0OUTPUTRDYR0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Interrupt did not occur
1h = Interrupt occured

29.2.2.10 ISET Register (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 29-20 and described in Table 29-18.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 29-20 ISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
W-0hW-0hW-0hW-0hW-0h
Table 29-18 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3CNTXTRDYW0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2SAVEDCNTXTRDYW0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the 'save_context' bit is set to '1b'. The bit is mutually exclusive with the 'context_ready' bit.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1INPUTRDYW0hThis indicates that the engine can take new input.This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0OUTPUTRDYW0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Writing 0 has no effect
1h = Set Interrupt

29.2.2.11 ICLR Register (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 29-21 and described in Table 29-19.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 29-21 ICLR Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
W-0hW-0hW-0hW-0hW-0h
Table 29-19 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3CNTXTRDYW0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2SAVEDCNTXTRDYW0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the 'save_context' bit is set to '1b'. The bit is mutually exclusive with the 'context_ready' bit.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1INPUTRDYW0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0OUTPUTRDYW0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Writing 0 has no effect
1h = Clear Interrupt

29.2.2.12 IIDX Register (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 29-22 and described in Table 29-20.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, ... IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 29-22 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 29-20 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
1h = AES trigger 0 DMA (Data Input trigger)

29.2.2.13 IMASK Register (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 29-23 and described in Table 29-21.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 29-23 IMASK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDTRIG0
R/W-0hR/W-0h
Table 29-21 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0TRIG0R/W0hTRIG0 event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask

29.2.2.14 RIS Register (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 29-24 and described in Table 29-22.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 29-24 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG0
R-0hR-0h
Table 29-22 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG0R0hTRIG0 event
0h = Interrupt did not occur
1h = Interrupt occured

29.2.2.15 MIS Register (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 29-25 and described in Table 29-23.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 29-25 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG0
R-0hR-0h
Table 29-23 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG0R0hTRIG0 event
0h = Interrupt did not occur
1h = Interrupt occured

29.2.2.16 ISET Register (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 29-26 and described in Table 29-24.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 29-26 ISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDTRIG0
W-0hW-0h
Table 29-24 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0TRIG0W0hTRIG0
0h = Writing 0 has no effect
1h = Set Interrupt

29.2.2.17 ICLR Register (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 29-27 and described in Table 29-25.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 29-27 ICLR Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDTRIG0
W-0hW-0h
Table 29-25 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0TRIG0W0hTRIG0 event
0h = Writing 0 has no effect
1h = Clear Interrupt

29.2.2.18 IIDX Register (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 29-28 and described in Table 29-26.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, ... IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 29-28 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 29-26 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
1h = AES DMA Trigger 1 (Data Output trigger)

29.2.2.19 IMASK Register (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 29-29 and described in Table 29-27.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 29-29 IMASK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDTRIG1
R/W-0hR/W-0h
Table 29-27 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0TRIG1R/W0hTRIG1 event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask

29.2.2.20 RIS Register (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 29-30 and described in Table 29-28.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 29-30 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG1
R-0hR-0h
Table 29-28 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG1R0hTRIG1 event
0h = Interrupt did not occur
1h = Interrupt occured

29.2.2.21 MIS Register (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 29-31 and described in Table 29-29.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 29-31 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG1
R-0hR-0h
Table 29-29 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG1R0hTRIG1 event
0h = Interrupt did not occur
1h = Interrupt occured

29.2.2.22 ISET Register (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 29-32 and described in Table 29-30.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 29-32 ISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDTRIG1
W-0hW-0h
Table 29-30 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0TRIG1W0hTRIG1 event
0h = Writing 0 has no effect
1h = Set Interrupt

29.2.2.23 ICLR Register (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 29-33 and described in Table 29-31.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 29-33 ICLR Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDTRIG1
W-0hW-0h
Table 29-31 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0TRIG1W0hTRIG1 event
0h = Writing 0 has no effect
1h = Clear Interrupt

29.2.2.24 EVT_MODE Register (Offset = 10E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 29-34 and described in Table 29-32.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 29-34 EVT_MODE Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEVT2_CFGEVT1_CFGINT0_CFG
R/W-0hR-0hR-0hR-0h
Table 29-32 EVT_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-4EVT2_CFGR2hEvent line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2EVT1_CFGR2hEvent line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0INT0_CFGR1hEvent line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

29.2.2.25 GCMCCM_TAG0 Register (Offset = 1100h) [Reset = 00000000h]

GCMCCM_TAG0 is shown in Figure 29-35 and described in Table 29-33.

Return to the Summary Table.

CBC-MAC third key (LSW) / GCM & CCM Intermediate TAG (LSW)
For CBC-MAC: Pre-calculated CBC-MAC third key used to perform a final XOR operation on the last input data block.
For CCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new CCM context. To restore an interrupted CCM operation, this register needs to be loaded with the intermediate TAG.
For GCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new GCM context. To restore an interrupted GCM operation, this register needs to be loaded with the intermediate TAG.

Figure 29-35 GCMCCM_TAG0 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-33 GCMCCM_TAG0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.26 GCMCCM_TAG1 Register (Offset = 1104h) [Reset = 00000000h]

GCMCCM_TAG1 is shown in Figure 29-36 and described in Table 29-34.

Return to the Summary Table.

CBC-MAC third key / GCM & CCM Intermediate TAG
For CBC-MAC: Pre-calculated CBC-MAC third key used to perform a final XOR operation on the last input data block.
For CCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new CCM context. To restore an interrupted CCM operation, this register needs to be loaded with the intermediate TAG.
For GCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new GCM context. To restore an interrupted GCM operation, this register needs to be loaded with the intermediate TAG.

Figure 29-36 GCMCCM_TAG1 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-34 GCMCCM_TAG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.27 GCMCCM_TAG2 Register (Offset = 1108h) [Reset = 00000000h]

GCMCCM_TAG2 is shown in Figure 29-37 and described in Table 29-35.

Return to the Summary Table.

CBC-MAC third key / GCM & CCM Intermediate TAG
For CBC-MAC: Pre-calculated CBC-MAC third key used to perform a final XOR operation on the last input data block.
For CCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new CCM context. To restore an interrupted CCM operation, this register needs to be loaded with the intermediate TAG.
For GCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new GCM context. To restore an interrupted GCM operation, this register needs to be loaded with the intermediate TAG.

Figure 29-37 GCMCCM_TAG2 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-35 GCMCCM_TAG2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.28 GCMCCM_TAG3 Register (Offset = 110Ch) [Reset = 00000000h]

GCMCCM_TAG3 is shown in Figure 29-38 and described in Table 29-36.

Return to the Summary Table.

CBC-MAC third key (MSW) / GCM & CCM Intermediate TAG (MSW)
For CBC-MAC: Pre-calculated CBC-MAC third key used to perform a final XOR operation on the last input data block.
For CCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new CCM context. To restore an interrupted CCM operation, this register needs to be loaded with the intermediate TAG.
For GCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new GCM context. To restore an interrupted GCM operation, this register needs to be loaded with the intermediate TAG.

Figure 29-38 GCMCCM_TAG3 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-36 GCMCCM_TAG3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.29 GHASH_H0 Register (Offset = 1110h) [Reset = 00000000h]

GHASH_H0 is shown in Figure 29-39 and described in Table 29-37.

Return to the Summary Table.

CCM & CBC-MAC second key (LSW) / GCM Hash Key input (LSW)
For CBC-MAC: Pre-calculated CBC-MAC second key used to perform a final XOR operation on the last input data block.
For GCM: Hash key
can be calculated internal or written via these registers. Only used for GHASH (GCM) modes.
For a CPU write operation, these registers must be written with the new values to be subsequently transferred to the engine.

Figure 29-39 GHASH_H0 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-37 GHASH_H0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.30 GHASH_H1 Register (Offset = 1114h) [Reset = 00000000h]

GHASH_H1 is shown in Figure 29-40 and described in Table 29-38.

Return to the Summary Table.

CCM & CBC-MAC second key / GCM Hash Key input
For CBC-MAC: Pre-calculated CBC-MAC second key used to perform a final XOR operation on the last input data block.
For GCM: Hash key
can be calculated internal or written via these registers. Only used for GHASH (GCM) modes.
For a CPU write operation, these registers must be written with the new values to be subsequently transferred to the engine.

Figure 29-40 GHASH_H1 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-38 GHASH_H1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.31 GHASH_H2 Register (Offset = 1118h) [Reset = 00000000h]

GHASH_H2 is shown in Figure 29-41 and described in Table 29-39.

Return to the Summary Table.

CCM & CBC-MAC second key / GCM Hash Key input
For CBC-MAC: Pre-calculated CBC-MAC second key used to perform a final XOR operation on the last input data block.
For GCM: Hash key
can be calculated internal or written via these registers. Only used for GHASH (GCM) modes.
For a CPU write operation, these registers must be written with the new values to be subsequently transferred to the engine.

Figure 29-41 GHASH_H2 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-39 GHASH_H2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.32 GHASH_H3 Register (Offset = 111Ch) [Reset = 00000000h]

GHASH_H3 is shown in Figure 29-42 and described in Table 29-40.

Return to the Summary Table.

CCM & CBC-MAC second key (MSW) / GCM Hash Key input (MSW)
For CBC-MAC: Pre-calculated CBC-MAC second key used to perform a final XOR operation on the last input data block.
For GCM: Hash key
can be calculated internal or written via these registers. Only used for GHASH (GCM) modes.
For a CPU write operation, these registers must be written with the new values to be subsequently transferred to the engine.

Figure 29-42 GHASH_H3 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-40 GHASH_H3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.33 KEY0 Register (Offset = 1120h) [Reset = 00000000h]

KEY0 is shown in Figure 29-43 and described in Table 29-41.

Return to the Summary Table.

KEY (LSW)

Figure 29-43 KEY0 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-41 KEY0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.34 KEY1 Register (Offset = 1124h) [Reset = 00000000h]

KEY1 is shown in Figure 29-44 and described in Table 29-42.

Return to the Summary Table.

KEY

Figure 29-44 KEY1 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-42 KEY1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.35 KEY2 Register (Offset = 1128h) [Reset = 00000000h]

KEY2 is shown in Figure 29-45 and described in Table 29-43.

Return to the Summary Table.

KEY

Figure 29-45 KEY2 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-43 KEY2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.36 KEY3 Register (Offset = 112Ch) [Reset = 00000000h]

KEY3 is shown in Figure 29-46 and described in Table 29-44.

Return to the Summary Table.

KEY

Figure 29-46 KEY3 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-44 KEY3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.37 KEY4 Register (Offset = 1130h) [Reset = 00000000h]

KEY4 is shown in Figure 29-47 and described in Table 29-45.

Return to the Summary Table.

KEY

Figure 29-47 KEY4 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-45 KEY4 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.38 KEY5 Register (Offset = 1134h) [Reset = 00000000h]

KEY5 is shown in Figure 29-48 and described in Table 29-46.

Return to the Summary Table.

KEY

Figure 29-48 KEY5 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-46 KEY5 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.39 KEY6 Register (Offset = 1138h) [Reset = 00000000h]

KEY6 is shown in Figure 29-49 and described in Table 29-47.

Return to the Summary Table.

KEY

Figure 29-49 KEY6 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-47 KEY6 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.40 KEY7 Register (Offset = 113Ch) [Reset = 00000000h]

KEY7 is shown in Figure 29-50 and described in Table 29-48.

Return to the Summary Table.

KEY (MSW)

Figure 29-50 KEY7 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-48 KEY7 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.41 IV0 Register (Offset = 1140h) [Reset = 00000000h]

IV0 is shown in Figure 29-51 and described in Table 29-49.

Return to the Summary Table.

IV (LSW)

Figure 29-51 IV0 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-49 IV0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.42 IV1 Register (Offset = 1144h) [Reset = 00000000h]

IV1 is shown in Figure 29-52 and described in Table 29-50.

Return to the Summary Table.

IV

Figure 29-52 IV1 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-50 IV1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.43 IV2 Register (Offset = 1148h) [Reset = 00000000h]

IV2 is shown in Figure 29-53 and described in Table 29-51.

Return to the Summary Table.

IV

Figure 29-53 IV2 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-51 IV2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.44 IV3 Register (Offset = 114Ch) [Reset = 00000000h]

IV3 is shown in Figure 29-54 and described in Table 29-52.

Return to the Summary Table.

IV

Figure 29-54 IV3 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-52 IV3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

29.2.2.45 CTRL Register (Offset = 1150h) [Reset = 80000000h]

CTRL is shown in Figure 29-55 and described in Table 29-53.

Return to the Summary Table.

Input/Output Buffer Control and Mode selection. The content of this register determines the mode of operation of the EIP-39.

Figure 29-55 CTRL Register
3130292827262524
CNTXT_RDYSAVED_CNTXT_RDYSAVE_CNTXTGCM_CONTGET_DIGESTOFB_GCM_CCM_CONTRESERVEDCCMM
R-1hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CCMMCCMLCCMGCM
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CBCMACRESERVEDCFBICMCTR_WIDTH
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CTR_WIDTHCTRCBCKEYSIZEDIRINPUT_RDYOUTPUT_RDY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR-0h
Table 29-53 CTRL Register Field Descriptions
BitFieldTypeResetDescription
31CNTXT_RDYR1hIf '1b', this read-only status bit indicates that the context data registers can be overwritten, and the CPU is permitted to write the next context.
0h = Not ready
1h = Ready
30SAVED_CNTXT_RDYR0hIf '1b', this read-only status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if the 'save_context' bit is set to '1b'. The bit is mutually exclusive with the 'context_ready' bit.
0h = Not ready
1h = Ready
29SAVE_CNTXTR/W0hThis bit is used to indicate that an authentication TAG or result IV needs to be stored as a result context. If this bit is set, context output DMA and/or interrupt will be asserted if the operation is finished, and related signals are enabled.
Typically, this value must be set for authentication modes returning a TAG (CBC-MAC, GCM and CCM), or for basic encryption modes that require future continuation with the current result IV.
If this bit is set, the engine will hold its full context until the TAG and/or IV registers are read. Only after reading the TAG or IV, a new DMA request for a new (input) context will be asserted.
If this bit is not set, the engine will assert the context input DMA request signal directly after starting to process the last block with the current context.
0h = No effect
1h = Enable
28GCM_CONTR/W0hContinue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase.
Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation, to continue processing from the next full block (128 bits) boundary.
Before setting this bit all applicable context to resume processing must have been loaded into the engine: Keys, IV, intermediate digest/TAG and block counter. The mode can be written together with this bit, as it is part of the same register.
0h = No effect
1h = Enable
27GET_DIGESTR/W0hInterrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation.
Set this write-only signal to '1b' to interrupt GCM or CCM processing at the next full block (128 bits) boundary. An intermediate digest may be requested during the encryption/decryption data phase or in the AAD phase.
Note: Interruption can only be done on full block (128 bits) boundaries. The minimum number of remaining bytes to resume and finalize the operation, must be greater than or equal to 1.
0h = No effect
1h = Enable
26OFB_GCM_CCM_CONTR/W0hThis bit has a dual use, depending on the selection of CCM/GCM, see bits [18:16].
If CCM/GCM is not selected:
If this bit is set to '1b', full block AES output feedback mode (OFB-128) is selected.
If CCM/GCM is selected:
Continue processing of an interrupted AES-GCM or AES-CCM operation in the AAD phase.
Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation, to continue processing from the next full AAD block (128 bits) boundary.
Before setting this bit all applicable context to resume processing must have been loaded into the engine: Keys, IV, intermediate digest/TAG, block counter and the CCM align data word (the latter is for CCM mode only). The mode can be written together with this bit, as it is part of the same register.
1h = Continue GCM/CCM processing in AAD phase
25RESERVEDR/W0h
24-22CCMMR/W0hDefines "M" that indicates the length of the authentication field for CCM operations
the authentication field length equals two times (the value of CCM-M plus one). Note: The EIP-39 always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported.
0h = Length is 1
7h = Length is 8
21-19CCMLR/W0hDefines "L" that indicates the width of the length field for CCM operations
the length field in bytes equals the value of CMM-L plus one. All values are supported.
0h = Length is 1
7h = Length is 8
18CCMR/W0hIf set to '1b', AES-CCM is selected, this is a combined mode, using AES for both authentication and encryption. In addition to the CCM bit, the CTR mode bit must be set such that AES-CTR is enabled. Other combinations with CCM are invalid.
0h = Disable CBC mode
1h = Select CBC mode
17-16GCMR/W0hIf not set to '00b', AES-GCM mode is selected, this is a combined mode, using the Galois field multiplier GF(2128) for authentication and AES-CTR mode for encryption, the bits specify the GCM mode: 01b = GHASH with H loaded and Y0-encrypted forced to zero 10b = GHASH with H loaded and Y0-encrypted calculated internally 11b = Autonomous GHASH (both H and Y0-encrypted calculated internally) Note: Besides GCM, the CTR mode bits must also be set to '1b' to enable GCM with AES-CTR
if the CTR bit is not set a GHASH (authentication) only operation is performed. A GHASH only operation is only allowed if the GCM mode is set to '01b' and the direction bit is set to '0b'. Other modes may not be selected in combination with GCM. Table 14 below shows the valid combinations for the GCM and CTR mode bits, all other options are invalid and must not be selected.
1h = GHASH with H loaded and Y0-encrypted forced to 0.
2h = GHASH with H loaded and Y0-encrypted calculated internally
3h = Autonomous GHASH (both H and Y0-encrypted calculated internally)
15CBCMACR/W0hIf set to '1b', AES-CBC MAC is selected, the Direction bit must be set to '1' for this mode.
0h = Disable CBC mode
1h = Select CBC mode
14-11RESERVEDR/W0h
10CFBR/W0hIf set to '1b', AES cipher feedback mode CFB is selected. Use the ctr_width field to specify the feedback width.
0h = Disable CBC mode
1h = Select CBC mode
9ICMR/W0hWhen the CFB bit is set, specifies the CFB mode feedback width:
0h = Disable CBC mode
1h = Select CBC mode
8-7CTR_WIDTHR/W0hWhen the CTR bit is set, specifies the counter width for AES-CTR mode.
When the CFB bit is set, specifies the CFB mode feedback width:
0h = CFB-128 mode
1h = 64-bit counter
2h = 96-bit counter
3h = 128-bit counter
6CTRR/W0hIf set to '1b', AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM, when encryption/decryption is required.
0h = Disable CBC mode
1h = Select CBC mode
5CBCR/W0hIf set to '1b', cipher-block-chaining (CBC) mode is selected.
0h = Disable CBC mode
1h = Select CBC mode
4-3KEYSIZER/W0hSpecifies the encryption strength / key width
1h = 128-bit key
3h = 256-bit key
2DIRR/W0hDirection. If set to '1b' an encrypt operation is performed. If set to '0b' a decrypt operation is performed. Note: This bit must be written with a '1b' when CBC-MAC is selected.
0h = Decryption
1h = Encryption
1INPUT_RDYR0hReady for input. If '1b', this read-only status bit indicates that the 16-byte input buffer is empty, and the CPU is permitted to write the next block of data. After reset, this bit is '0'. After writing a context, this bit will become '1b'.
0h = Not Ready
1h = Ready
0OUTPUT_RDYR0hOutput Ready. If '1b', this read-only status bit indicates that an AES output block is available for the CPU to retrieve.
0h = Not Ready
1h = Ready

29.2.2.46 C_LENGTH_0 Register (Offset = 1154h) [Reset = 00000000h]

C_LENGTH_0 is shown in Figure 29-56 and described in Table 29-54.

Return to the Summary Table.

Crypto data length (LSW). These registers buffer the Length values to the EIP-39. While processing, the length values decrement to zero. If both lengths are zero, the data stream is finished, and a new context is requested. For basic AES modes (ECB/CBC/CTR/ICM/CFB/OFB), a crypto length of '0' can be written if the context DMA is disabled. Writing a zero length results in continued data requests until a new context is written. For the other modes (GCM and CCM) no (new) data requests are done if the length decrements to or equals zero.
It is advised to write a new length per packet. If the length registers decrement to zero, no new data is processed until a new context or length value is written.
When writing a new context without writing the length registers, the length register values from the previous context are reused.

Figure 29-56 C_LENGTH_0 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-54 C_LENGTH_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hBits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261-1) bytes are allowed.
For GCM, any value up to 236-32 bytes can be used. This is because a 32-bit counter mode is used
the maximum number of 128-bit blocks is 232-2, resulting in a maximum number of bytes of 236-32.
A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM.
Note that for the combined modes, this length does not include the authentication only data
the authentication length is specified in the AES_AAD_LENGTH register below.
All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero.
For the basic encryption modes (ECB/CBC/CTR/ICM/CFB/OFB) it is allowed to program zero to the length field
in that case the length is assumed infinite.
All data must be byte (8-bit) aligned for stream cipher modes
bit aligned data streams are not supported. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes.

29.2.2.47 C_LENGTH_1 Register (Offset = 1158h) [Reset = 00000000h]

C_LENGTH_1 is shown in Figure 29-57 and described in Table 29-55.

Return to the Summary Table.

Crypto data length (MSW). These registers buffer the Length values to the EIP-39. While processing, the length values decrement to zero. If both lengths are zero, the data stream is finished, and a new context is requested. For basic AES modes (ECB/CBC/CTR/ICM/CFB/OFB), a crypto length of '0' can be written if the context DMA is disabled. Writing a zero length results in continued data requests until a new context is written. For the other modes (GCM and CCM) no (new) data requests are done if the length decrements to or equals zero.
It is advised to write a new length per packet. If the length registers decrement to zero, no new data is processed until a new context or length value is written.
When writing a new context without writing the length registers, the length register values from the previous context are reused.

Figure 29-57 C_LENGTH_1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
W-0hW-0h
Table 29-55 C_LENGTH_1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28-0DATAW0hBits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261-1) bytes are allowed.
For GCM, any value up to 236-32 bytes can be used. This is because a 32-bit counter mode is used
the maximum number of 128-bit blocks is 232-2, resulting in a maximum number of bytes of 236-32.
A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM.
Note that for the combined modes, this length does not include the authentication only data
the authentication length is specified in the AES_AAD_LENGTH register below.
All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero.
For the basic encryption modes (ECB/CBC/CTR/ICM/CFB/OFB) it is allowed to program zero to the length field
in that case the length is assumed infinite.
All data must be byte (8-bit) aligned for stream cipher modes
bit aligned data streams are not supported. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes.

29.2.2.48 AAD_LENGTH Register (Offset = 115Ch) [Reset = 00000000h]

AAD_LENGTH is shown in Figure 29-58 and described in Table 29-56.

Return to the Summary Table.

AAD Data Length

Figure 29-58 AAD_LENGTH Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-56 AAD_LENGTH Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hBits [31:0] of the authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM)
Supported AAD-lengths for CCM are from 0 to (216-28) bytes. For GCM any value up to (232-1) bytes can be used. Once processing with this context is started, this length decrements to zero.
A write to this register triggers the engine to start using this context for GCM and CCM.

29.2.2.49 DATA0 Register (Offset = 1160h) [Reset = 00000000h]

DATA0 is shown in Figure 29-59 and described in Table 29-57.

Return to the Summary Table.

Data input (LSW) / Data output (LSW)\. The Data Input/Output Registers buffer the input/output data blocks to/from the EIP-39. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written
for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface.

Figure 29-59 DATA0 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 29-57 DATA0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hData

29.2.2.50 DATA1 Register (Offset = 1164h) [Reset = 00000000h]

DATA1 is shown in Figure 29-60 and described in Table 29-58.

Return to the Summary Table.

Data input / Data output. The Data Input/Output Registers buffer the input/output data blocks to/from the EIP-39. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written
for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface.

Figure 29-60 DATA1 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 29-58 DATA1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hData

29.2.2.51 DATA2 Register (Offset = 1168h) [Reset = 00000000h]

DATA2 is shown in Figure 29-61 and described in Table 29-59.

Return to the Summary Table.

Data input / Data output. The Data Input/Output Registers buffer the input/output data blocks to/from the EIP-39. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written
for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface.

Figure 29-61 DATA2 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 29-59 DATA2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hData

29.2.2.52 DATA3 Register (Offset = 116Ch) [Reset = 00000000h]

DATA3 is shown in Figure 29-62 and described in Table 29-60.

Return to the Summary Table.

Data input (MSW) / Data output (MSW). The Data Input/Output Registers buffer the input/output data blocks to/from the EIP-39. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written
for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface.

Figure 29-62 DATA3 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 29-60 DATA3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hData

29.2.2.53 TAG0 Register (Offset = 1170h) [Reset = 00000000h]

TAG0 is shown in Figure 29-63 and described in Table 29-61.

Return to the Summary Table.

Hash result (LSW). These registers buffer the TAG from the EIP-39. The registers are shared with the intermediate authentication result registers but cannot be read until the processing is finished.

Figure 29-63 TAG0 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 29-61 TAG0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hFor a CPU read operation, these registers contain the last 128-bit TAG output of the EIP-39
the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available, when the 'saved_context_ready' or 'get_digest' bit from AES_CTRL register is set. In case of get_digest, the output will be an intermediate TAG for CCM or GCM operation continuation. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register, the IV register must be accessed directly.

29.2.2.54 TAG1 Register (Offset = 1174h) [Reset = 00000000h]

TAG1 is shown in Figure 29-64 and described in Table 29-62.

Return to the Summary Table.

Hash result. These registers buffer the TAG from the EIP-39. The registers are shared with the intermediate authentication result registers but cannot be read until the processing is finished.

Figure 29-64 TAG1 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 29-62 TAG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hFor a CPU read operation, these registers contain the last 128-bit TAG output of the EIP-39
the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available, when the 'saved_context_ready' or 'get_digest' bit from AES_CTRL register is set. In case of get_digest, the output will be an intermediate TAG for CCM or GCM operation continuation. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register, the IV register must be accessed directly.

29.2.2.55 TAG2 Register (Offset = 1178h) [Reset = 00000000h]

TAG2 is shown in Figure 29-65 and described in Table 29-63.

Return to the Summary Table.

Hash result. These registers buffer the TAG from the EIP-39. The registers are shared with the intermediate authentication result registers but cannot be read until the processing is finished.

Figure 29-65 TAG2 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 29-63 TAG2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hFor a CPU read operation, these registers contain the last 128-bit TAG output of the EIP-39
the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available, when the 'saved_context_ready' or 'get_digest' bit from AES_CTRL register is set. In case of get_digest, the output will be an intermediate TAG for CCM or GCM operation continuation. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register, the IV register must be accessed directly.

29.2.2.56 TAG3 Register (Offset = 117Ch) [Reset = 00000000h]

TAG3 is shown in Figure 29-66 and described in Table 29-64.

Return to the Summary Table.

Hash result (MSW). These registers buffer the TAG from the EIP-39. The registers are shared with the intermediate authentication result registers but cannot be read until the processing is finished.

Figure 29-66 TAG3 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 29-64 TAG3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hFor a CPU read operation, these registers contain the last 128-bit TAG output of the EIP-39
the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available, when the 'saved_context_ready' or 'get_digest' bit from AES_CTRL register is set. In case of get_digest, the output will be an intermediate TAG for CCM or GCM operation continuation. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register, the IV register must be accessed directly.

29.2.2.57 STATUS Register (Offset = 1180h) [Reset = 00000000h]

STATUS is shown in Figure 29-67 and described in Table 29-65.

Return to the Summary Table.

Status register

Figure 29-67 STATUS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDKEYWR
R-0hR-0h
Table 29-65 STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0KEYWRR0hKey write status. 0 - user write to KEY register is allowed. 1 - user write to KEY register is ignored.
In order to allow user write, perform a module reset.
0h = User write to KEY MMR is allowed
1h = User write to KEY MMR is disabled. Writing has no effect.

29.2.2.58 DATA_IN Register (Offset = 1184h) [Reset = 00000000h]

DATA_IN is shown in Figure 29-68 and described in Table 29-66.

Return to the Summary Table.

Data-in register: alias for DATA0/1/2/3 at a single address for DMA addressing

Figure 29-68 DATA_IN Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-66 DATA_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hData input word

29.2.2.59 DATA_OUT Register (Offset = 1188h) [Reset = 00000000h]

DATA_OUT is shown in Figure 29-69 and described in Table 29-67.

Return to the Summary Table.

Data-out register: alias for DATA0/1/2/3 at a single address for DMA addressing

Figure 29-69 DATA_OUT Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 29-67 DATA_OUT Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData output word

29.2.2.60 FORCE_IN_AV Register (Offset = 11D0h) [Reset = 00000000h]

FORCE_IN_AV is shown in Figure 29-70 and described in Table 29-68.

Return to the Summary Table.

Data control register for input data. This write-only register provides a means to force the availability of the input data buffer of the EIP-39.

Figure 29-70 FORCE_IN_AV Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-68 FORCE_IN_AV Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hAny write to this register forces the input data buffer to valid and will force the engine to start processing this data. The data written here is not used. The core must be configured to have input and output data acknowledge be I/O register based

29.2.2.61 CCM_ALN_WRD Register (Offset = 11D4h) [Reset = 00000000h]

CCM_ALN_WRD is shown in Figure 29-71 and described in Table 29-69.

Return to the Summary Table.

AES-CCM AAD alignment data word. This register provides a means to access an internal EIP-39 register that stores alignment data bytes during the AAD phase of AES-CCM processing. This register needs to be read and stored when an AES-CCM operation is interrupted during the AAD phase. This value needs to be restored by writing this register, when resuming that AES-CCM operation in a later session.

Figure 29-71 CCM_ALN_WRD Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 29-69 CCM_ALN_WRD Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis register provides a means to access an internal EIP-39 register that stores alignment data bytes during the AAD phase of AES-CCM processing. This register needs to be read and stored when an AES-CCM operation is interrupted during the AAD phase. This value needs to be restored by writing this register, when resuming that AES-CCM operation in a later session.

29.2.2.62 BLK_CNT0 Register (Offset = 11D8h) [Reset = 00000000h]

BLK_CNT0 is shown in Figure 29-72 and described in Table 29-70.

Return to the Summary Table.

Internal block counter (LSW). This register along with BLK_CNT1 register provides access to the internal data block counter of the EIP-39. This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations. Reading and writing this counter allows interruption and resuming of long CCM or GCM operations. Note that internally, the block counter is used for AAD data as well as encryption/decryption data. Interruption and resuming is only supported in the encryption/decryption data phase and not during AAD.

Figure 29-72 BLK_CNT0 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 29-70 BLK_CNT0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hInternal block counter for AES GCM and CCM operations.
These bits read the block count value that represents the number of blocks to go. This value is valid with saved_context_ready after a request for an intermediate GCM/CCM digest.
Writing these registers will restore the internal block counter to the programmed value. This only needs to be done to prepare the engine to continue processing of an interrupted GCM or CCM operation.
Also refer to the get_digest and gcm_ccm_continue bits in AES_CTRL register.

29.2.2.63 BLK_CNT1 Register (Offset = 11DCh) [Reset = 00000000h]

BLK_CNT1 is shown in Figure 29-73 and described in Table 29-71.

Return to the Summary Table.

Internal block counter (MSW). This register along with BLK_CNT0 register provides access to the internal data block counter of the EIP-39. This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations. Reading and writing this counter allows interruption and resuming of long CCM or GCM operations. Note that internally, the block counter is used for AAD data as well as encryption/decryption data. Interruption and resuming is only supported in the encryption/decryption data phase and not during AAD.

Figure 29-73 BLK_CNT1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R/W-0hR/W-0h
Table 29-71 BLK_CNT1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0h
23-0DATAR/W0hInternal block counter for AES GCM and CCM operations.
These bits read the block count value that represents the number of blocks to go. This value is valid with saved_context_ready after a request for an intermediate GCM/CCM digest.
Writing these registers will restore the internal block counter to the programmed value. This only needs to be done to prepare the engine to continue processing of an interrupted GCM or CCM operation.
Also refer to the get_digest and gcm_ccm_continue bits in AES_CTRL register.

29.2.2.64 DMA_HS Register (Offset = 11F4h) [Reset = 00000000h]

DMA_HS is shown in Figure 29-74 and described in Table 29-72.

Return to the Summary Table.

Control register for DMA handshaking

Figure 29-74 DMA_HS Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDDMA_DATA_ACK
R/W-0hR/W-0h
Table 29-72 DMA_HS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0DMA_DATA_ACKR/W0hWhen this bit is 0b, input and output data acknowledge is I/O register based, as specified in the description of the AES_DATA_IN_n / AES_DATA_OUT_n registers.
When this bit is 1b, input and ouput data acknowledge is based on DMA handshake signals.
0h = Disable DMA based data handshake
1h = Enables DMA based handshake