SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

31.2.2 TIMG4_REGS Registers

Table 31-19 lists the memory-mapped registers for the TIMG4_REGS registers. All register offset addresses not listed in Table 31-19 should be considered as reserved locations and the register contents should not be modified.

Table 31-19 TIMG4_REGS Registers
OffsetAcronymRegister NameSection
4hCCP0CCP0 PinCMGo
8hCCP1CCP0 PinCMGo
24hCCP2_CMPLCCP2_CMPL PinCMGo
28hCCP3_CMPLCCP3_CMPL PinCMGo
204hCCP0CCP0 FUPDATEGo
208hCCP1CCP1 FUPDATEGo
224hCCP2_CMPLCCP2_CMPL FUPDATEGo
228hCCP3_CMPLCCP3_CMPL FUPDATEGo
400hFSUB_0Subsciber Port 0Go
404hFSUB_1Subscriber Port 1Go
444hFPUB_0Publisher Port 0Go
448hFPUB_1Publisher Port 1Go
480hCPU_CONNECT_0CPU connect 0 configuration byteGo
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
814hSTATStatus RegisterGo
1000hCLKDIVClock DividerGo
1008hCLKSELClock Select for Ultra Low Power peripheralsGo
1018hPDBGCTLPeripheral Debug ControlGo
1020hIIDXInterrupt indexGo
1028hIMASKInterrupt maskGo
1030hRISRaw interrupt statusGo
1038hMISMasked interrupt statusGo
1040hISETInterrupt setGo
1048hICLRInterrupt clearGo
1050hIIDXInterrupt indexGo
1058hIMASKInterrupt maskGo
1060hRISRaw interrupt statusGo
1068hMISMasked interrupt statusGo
1070hISETInterrupt setGo
1078hICLRInterrupt clearGo
1080hIIDXInterrupt indexGo
1088hIMASKInterrupt maskGo
1090hRISRaw interrupt statusGo
1098hMISMasked interrupt statusGo
10A0hISETInterrupt setGo
10A8hICLRInterrupt clearGo
10E0hEVT_MODEEvent ModeGo
10FChDESCModule DescriptionGo
1100hCCPDCCP DirectionGo
1104hODISOutput DisableGo
1108hCCLKCTLCounter Clock Control RegisterGo
110ChCPSClock Prescale RegisterGo
1110hCPSVClock prescale count status registerGo
1114hCTTRIGCTLTimer Cross Trigger Control RegisterGo
111ChCTTRIGTimer Cross Trigger RegisterGo
1800hCTRCounter RegisterGo
1804hCTRCTLCounter Control RegisterGo
1808hLOADLoad RegisterGo
1810h + formulaCC_01_yCapture or Compare Register 0/1Go
1830h + formulaCCCTL_01_yCapture or Compare Control Registers 0/1Go
1850h + formulaOCTL_01_yCCP Output Control Registers 0/1Go
1870h + formulaCCACT_01_yCapture or Compare Action Registers 0/1Go
1880h + formulaIFCTL_01_yInput Filter Control Register 0/1Go
18B0hTSELTrigger Select RegisterGo

Complex bit access types are encoded to fit into small table cells. Table 31-20 shows the codes that are used for access types in this section.

Table 31-20 TIMG4_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

31.2.2.1 CCP0 Register (Offset = 4h) [Reset = 00000000h]

CCP0 is shown in Figure 31-25 and described in Table 31-21.

Return to the Summary Table.

CCP0 PinCM register in full write region

Figure 31-25 CCP0 Register
3130292827262524
RESERVEDGFLTSLEWWCOMPWUENINVHIGHZ1HIGHZ0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDDRVHYSTENINENAPIPUPIPD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GSTATERESERVED
R/W-0hR/W-0h
76543210
PSTATERESERVED
R/W-0hR/W-0h
Table 31-21 CCP0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h
30GFLTR/W0hGlitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29SLEWR/W0hReserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28WCOMPR/W0hWake up compare value
0h = Match '0' will wake
1h = Match '1' will wake
27WUENR/W0hWake up enable
0h = Wake up not enabled
1h = Wake up enabled
26INVR/W0hInvert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25HIGHZ1R/W0hHigh-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24HIGHZ0R/W0hHigh-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23RESERVEDR/W0h
22-20DRVR/W0hDrive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19HYSTENR/W0hHysteresis enable
0h = No hysteresis
1h = Hysteresis on
18INENAR/W0hInput enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17PIPUR/W0hPull up enable
0h = No pull up
1h = Pull up
16PIPDR/W0hPull down enable
0h = No pull down
1h = Pull down
15-14GSTATER/W0hGPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channle is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8RESERVEDR/W0h
7-6PSTATER/W0hPeripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channle is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0RESERVEDR/W0h

31.2.2.2 CCP1 Register (Offset = 8h) [Reset = 00000000h]

CCP1 is shown in Figure 31-26 and described in Table 31-22.

Return to the Summary Table.

CCP0 PinCM register in full write region

Figure 31-26 CCP1 Register
3130292827262524
RESERVEDGFLTSLEWWCOMPWUENINVHIGHZ1HIGHZ0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDDRVHYSTENINENAPIPUPIPD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GSTATERESERVED
R/W-0hR/W-0h
76543210
PSTATERESERVED
R/W-0hR/W-0h
Table 31-22 CCP1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h
30GFLTR/W0hGlitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29SLEWR/W0hReserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28WCOMPR/W0hWake up compare value
0h = Match '0' will wake
1h = Match '1' will wake
27WUENR/W0hWake up enable
0h = Wake up not enabled
1h = Wake up enabled
26INVR/W0hInvert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25HIGHZ1R/W0hHigh-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24HIGHZ0R/W0hHigh-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23RESERVEDR/W0h
22-20DRVR/W0hDrive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19HYSTENR/W0hHysteresis enable
0h = No hysteresis
1h = Hysteresis on
18INENAR/W0hInput enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17PIPUR/W0hPull up enable
0h = No pull up
1h = Pull up
16PIPDR/W0hPull down enable
0h = No pull down
1h = Pull down
15-14GSTATER/W0hGPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channle is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8RESERVEDR/W0h
7-6PSTATER/W0hPeripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channle is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0RESERVEDR/W0h

31.2.2.3 CCP2_CMPL Register (Offset = 24h) [Reset = 00000000h]

CCP2_CMPL is shown in Figure 31-27 and described in Table 31-23.

Return to the Summary Table.

CCP2_CMPL PinCM register in full write region

Figure 31-27 CCP2_CMPL Register
3130292827262524
RESERVEDGFLTSLEWWCOMPWUENINVHIGHZ1HIGHZ0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDDRVHYSTENINENAPIPUPIPD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GSTATERESERVED
R/W-0hR/W-0h
76543210
PSTATERESERVED
R/W-0hR/W-0h
Table 31-23 CCP2_CMPL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h
30GFLTR/W0hGlitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29SLEWR/W0hReserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28WCOMPR/W0hWake up compare value
0h = Match '0' will wake
1h = Match '1' will wake
27WUENR/W0hWake up enable
0h = Wake up not enabled
1h = Wake up enabled
26INVR/W0hInvert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25HIGHZ1R/W0hHigh-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24HIGHZ0R/W0hHigh-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23RESERVEDR/W0h
22-20DRVR/W0hDrive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19HYSTENR/W0hHysteresis enable
0h = No hysteresis
1h = Hysteresis on
18INENAR/W0hInput enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17PIPUR/W0hPull up enable
0h = No pull up
1h = Pull up
16PIPDR/W0hPull down enable
0h = No pull down
1h = Pull down
15-14GSTATER/W0hGPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channle is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8RESERVEDR/W0h
7-6PSTATER/W0hPeripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channle is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0RESERVEDR/W0h

31.2.2.4 CCP3_CMPL Register (Offset = 28h) [Reset = 00000000h]

CCP3_CMPL is shown in Figure 31-28 and described in Table 31-24.

Return to the Summary Table.

CCP3_CMPL PinCM register in full write region

Figure 31-28 CCP3_CMPL Register
3130292827262524
RESERVEDGFLTSLEWWCOMPWUENINVHIGHZ1HIGHZ0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDDRVHYSTENINENAPIPUPIPD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GSTATERESERVED
R/W-0hR/W-0h
76543210
PSTATERESERVED
R/W-0hR/W-0h
Table 31-24 CCP3_CMPL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h
30GFLTR/W0hGlitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29SLEWR/W0hReserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28WCOMPR/W0hWake up compare value
0h = Match '0' will wake
1h = Match '1' will wake
27WUENR/W0hWake up enable
0h = Wake up not enabled
1h = Wake up enabled
26INVR/W0hInvert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25HIGHZ1R/W0hHigh-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24HIGHZ0R/W0hHigh-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23RESERVEDR/W0h
22-20DRVR/W0hDrive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19HYSTENR/W0hHysteresis enable
0h = No hysteresis
1h = Hysteresis on
18INENAR/W0hInput enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17PIPUR/W0hPull up enable
0h = No pull up
1h = Pull up
16PIPDR/W0hPull down enable
0h = No pull down
1h = Pull down
15-14GSTATER/W0hGPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channle is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8RESERVEDR/W0h
7-6PSTATER/W0hPeripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channle is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0RESERVEDR/W0h

31.2.2.5 CCP0 Register (Offset = 204h) [Reset = 00000000h]

CCP0 is shown in Figure 31-29 and described in Table 31-25.

Return to the Summary Table.

FUPDATE version of CCP0

Figure 31-29 CCP0 Register
3130292827262524
RESERVEDIOADDR
W-0hW-0h
2322212019181716
IOADDR
W-0h
15141312111098
IOADDR
W-0h
76543210
IOADDRLOCKGSEL
W-0hW-0hW-0h
Table 31-25 CCP0 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDW0h
27-2IOADDRW0hIO Address This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the "Full Write" subregion of the pinmux subregion.
1LOCKW0hSets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0GSELW0hGPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update

0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

31.2.2.6 CCP1 Register (Offset = 208h) [Reset = 00000000h]

CCP1 is shown in Figure 31-30 and described in Table 31-26.

Return to the Summary Table.

FUPDATE version of CCP1

Figure 31-30 CCP1 Register
3130292827262524
RESERVEDIOADDR
W-0hW-0h
2322212019181716
IOADDR
W-0h
15141312111098
IOADDR
W-0h
76543210
IOADDRLOCKGSEL
W-0hW-0hW-0h
Table 31-26 CCP1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDW0h
27-2IOADDRW0hIO Address This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the "Full Write" subregion of the pinmux subregion.
1LOCKW0hSets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0GSELW0hGPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update

0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

31.2.2.7 CCP2_CMPL Register (Offset = 224h) [Reset = 00000000h]

CCP2_CMPL is shown in Figure 31-31 and described in Table 31-27.

Return to the Summary Table.

FUPDATE version of CCP2_CMPL

Figure 31-31 CCP2_CMPL Register
3130292827262524
RESERVEDIOADDR
W-0hW-0h
2322212019181716
IOADDR
W-0h
15141312111098
IOADDR
W-0h
76543210
IOADDRLOCKGSEL
W-0hW-0hW-0h
Table 31-27 CCP2_CMPL Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDW0h
27-2IOADDRW0hIO Address This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the "Full Write" subregion of the pinmux subregion.
1LOCKW0hSets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0GSELW0hGPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update

0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

31.2.2.8 CCP3_CMPL Register (Offset = 228h) [Reset = 00000000h]

CCP3_CMPL is shown in Figure 31-32 and described in Table 31-28.

Return to the Summary Table.

FUPDATE version of CCP3_CMPL

Figure 31-32 CCP3_CMPL Register
3130292827262524
RESERVEDIOADDR
W-0hW-0h
2322212019181716
IOADDR
W-0h
15141312111098
IOADDR
W-0h
76543210
IOADDRLOCKGSEL
W-0hW-0hW-0h
Table 31-28 CCP3_CMPL Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDW0h
27-2IOADDRW0hIO Address This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the "Full Write" subregion of the pinmux subregion.
1LOCKW0hSets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0GSELW0hGPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update

0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

31.2.2.9 FSUB_0 Register (Offset = 400h) [Reset = 00000000h]

FSUB_0 is shown in Figure 31-33 and described in Table 31-29.

Return to the Summary Table.

Subscriber port

Figure 31-33 FSUB_0 Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 31-29 FSUB_0 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device datasheet as the actual allowed maximum may be less than 15.

31.2.2.10 FSUB_1 Register (Offset = 404h) [Reset = 00000000h]

FSUB_1 is shown in Figure 31-34 and described in Table 31-30.

Return to the Summary Table.

Subscriber port

Figure 31-34 FSUB_1 Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 31-30 FSUB_1 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device datasheet as the actual allowed maximum may be less than 15.

31.2.2.11 FPUB_0 Register (Offset = 444h) [Reset = 00000000h]

FPUB_0 is shown in Figure 31-35 and described in Table 31-31.

Return to the Summary Table.

Publisher port

Figure 31-35 FPUB_0 Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 31-31 FPUB_0 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device datasheet as the actual allowed maximum may be less than 15.

31.2.2.12 FPUB_1 Register (Offset = 448h) [Reset = 00000000h]

FPUB_1 is shown in Figure 31-36 and described in Table 31-32.

Return to the Summary Table.

Publisher port

Figure 31-36 FPUB_1 Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 31-32 FPUB_1 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device datasheet as the actual allowed maximum may be less than 15.

31.2.2.13 CPU_CONNECT_0 Register (Offset = 480h) [Reset = 00000000h]

CPU_CONNECT_0 is shown in Figure 31-37 and described in Table 31-33.

Return to the Summary Table.

Connect peripheral interrupts / publisher port (FPUB_1) to application processor

Figure 31-37 CPU_CONNECT_0 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCPUSS0_CONNRESERVED
R/W-0hR/W-0hR/W-0h
Table 31-33 CPU_CONNECT_0 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1CPUSS0_CONNR/W0hCPUSS0 connect bit.
0h = The CPU is not connected.
1h = The CPU is connected.
0RESERVEDR/W0h

31.2.2.14 PWREN Register (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 31-38 and described in Table 31-34.

Return to the Summary Table.

Register to control the power state

Figure 31-38 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE
R/W-0hR/WK-0h
Table 31-34 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR/W0h
0ENABLER/WK0hEnable the power

[EXT_GPRCM.GPRCM.PWREN.KEY] must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

31.2.2.15 RSTCTL Register (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 31-39 and described in Table 31-35.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 31-39 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-0hWK-0hWK-0h
Table 31-35 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDW0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

[EXT_GPRCM.GPRCM.RSTCTL.KEY] must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

[EXT_GPRCM.GPRCM.RSTCTL.KEY] must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

31.2.2.16 STAT Register (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 31-40 and described in Table 31-36.

Return to the Summary Table.

peripheral enable and reset status

Figure 31-40 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 31-36 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

31.2.2.17 CLKDIV Register (Offset = 1000h) [Reset = 00000000h]

CLKDIV is shown in Figure 31-41 and described in Table 31-37.

Return to the Summary Table.

This register is used to specify module-specific divide ratio of the functional clock

Figure 31-41 CLKDIV Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDRATIO
R/W-0hR/W-0h
Table 31-37 CLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0RATIOR/W0hSelects divide ratio of module clock
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 3
3h = Divide clock source by 4
4h = Divide clock source by 5
5h = Divide clock source by 6
6h = Divide clock source by 7
7h = Divide clock source by 8

31.2.2.18 CLKSEL Register (Offset = 1008h) [Reset = 00000000h]

CLKSEL is shown in Figure 31-42 and described in Table 31-38.

Return to the Summary Table.

Clock Source Select Register

Figure 31-42 CLKSEL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDBUSCLK_SELMFCLK_SELLFCLK_SELRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-38 CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0h
4RESERVEDR/W0hReserved
3BUSCLK_SELR/W0hSelects BUSCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
2MFCLK_SELR/W0hSelects MFCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
1LFCLK_SELR/W0hSelects LFCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
0RESERVEDR/W0h

31.2.2.19 PDBGCTL Register (Offset = 1018h) [Reset = 00000000h]

PDBGCTL is shown in Figure 31-43 and described in Table 31-39.

Return to the Summary Table.

This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 31-43 PDBGCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSOFTFREE
R/W-0hR/W-0hR/W-0h
Table 31-39 PDBGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1SOFTR/W1hSoft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0FREER/W1hFree run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

31.2.2.20 IIDX Register (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 31-44 and described in Table 31-40.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, ... IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 31-44 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 31-40 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = Interrupt Source: Zero event (Z)
02h = nterrupt Source: Load event (L)
05h = Interrupt Source: Capture or compare down event (CCD0)
06h = Interrupt Source: Capture or compare down event (CCD1)
07h = Interrupt Source: Capture or compare down event (CCD2)
08h = Interrupt Source: Capture or compare down event (CCD3)
09h = Interrupt Source: Capture or compare up event (CCU0)
0Ah = Interrupt Source: Capture or compare up event (CCU1)
0Bh = Interrupt Source: Capture or compare up event (CCU2)
0Ch = Interrupt Source: Capture or compare up event (CCU3)
0Dh = Interrupt Source: Compare down event (CCD4)
0Eh = Interrupt Source: Compare down event (CCD5)
0Fh = Interrupt Source: Compare down event (CCU4)
10h = Interrupt Source: Compare down event (CCU5)
19h = Interrupt Source: Fault Event generated an interrupt. (F)
1Ah = Interrupt Source: Trigger overflow (TOV)
1Bh = Interrupt Source: Repeat Counter Zero (REPC)
1Ch = Interrupt Source: Direction Change (DC)
1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR)

31.2.2.21 IMASK Register (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 31-45 and described in Table 31-41.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS."

Figure 31-45 IMASK Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-41 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25TOVR/W0hTrigger Overflow Event mask
0h = Disable Event
1h = Enable Event
24RESERVEDR/W0hReserved
23-16RESERVEDR/W0h
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9CCU1R/W0hCapture or Compare UP event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8CCU0R/W0hCapture or Compare UP event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5CCD1R/W0hCapture or Compare DN event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4CCD0R/W0hCapture or Compare DN event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3-2RESERVEDR/W0h
1LR/W0hLoad Event mask
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0ZR/W0hZero Event mask
0h = Disable Event
1h = Enable Event

31.2.2.22 RIS Register (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 31-46 and described in Table 31-42.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 31-46 RIS Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-42 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24RESERVEDR0hReserved
23-16RESERVEDR0h
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

31.2.2.23 MIS Register (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 31-47 and described in Table 31-43.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 31-47 MIS Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-43 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24RESERVEDR0hReserved
23-16RESERVEDR0h
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

31.2.2.24 ISET Register (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 31-48 and described in Table 31-44.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 31-48 ISET Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-44 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28RESERVEDW0hReserved
27RESERVEDW0hReserved
26RESERVEDW0hReserved
25TOVW0hTrigger Overflow event SET
0h = Writing 0 has no effect.
1h = Event Set
24RESERVEDW0hReserved
23-16RESERVEDW0h
15RESERVEDW0hReserved
14RESERVEDW0hReserved
13RESERVEDW0hReserved
12RESERVEDW0hReserved
11RESERVEDW0hReserved
10RESERVEDW0hReserved
9CCU1W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
8CCU0W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
7RESERVEDW0hReserved
6RESERVEDW0hReserved
5CCD1W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
4CCD0W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
3-2RESERVEDW0h
1LW0h Load event SET
0h = Writing 0 has no effect.
1h = Event Set
0ZW0h Zero event SET
0h = Writing 0 has no effect.
1h = Event Set

31.2.2.25 ICLR Register (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 31-49 and described in Table 31-45.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 31-49 ICLR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-45 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28RESERVEDW0hReserved
27RESERVEDW0hReserved
26RESERVEDW0hReserved
25TOVW0hTrigger Overflow event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
24RESERVEDW0hReserved
23-16RESERVEDW0h
15RESERVEDW0hReserved
14RESERVEDW0hReserved
13RESERVEDW0hReserved
12RESERVEDW0hReserved
11RESERVEDW0hReserved
10RESERVEDW0hReserved
9CCU1W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
8CCU0W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
7RESERVEDW0hReserved
6RESERVEDW0hReserved
5CCD1W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
4CCD0W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
3-2RESERVEDW0h
1LW0h Load event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
0ZW0h Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear

31.2.2.26 IIDX Register (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 31-50 and described in Table 31-46.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, ... IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 31-50 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 31-46 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = Interrupt Source: Zero event (Z)
02h = nterrupt Source: Load event (L)
05h = Interrupt Source: Capture or compare down event (CCD0)
06h = Interrupt Source: Capture or compare down event (CCD1)
07h = Interrupt Source: Capture or compare down event (CCD2)
08h = Interrupt Source: Capture or compare down event (CCD3)
09h = Interrupt Source: Capture or compare up event (CCU0)
0Ah = Interrupt Source: Capture or compare up event (CCU1)
0Bh = Interrupt Source: Capture or compare up event (CCU2)
0Ch = Interrupt Source: Capture or compare up event (CCU3)
0Dh = Interrupt Source: Compare down event (CCD4)
0Eh = Interrupt Source: Compare down event (CCD5)
0Fh = Interrupt Source: Compare down event (CCU4)
10h = Interrupt Source: Compare down event (CCU5)
19h = Interrupt Source: Fault Event generated an interrupt. (F)
1Ah = Interrupt Source: Trigger overflow (TOV)
1Bh = Interrupt Source: Repeat Counter Zero (REPC)
1Ch = Interrupt Source: Direction Change (DC)
1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR)

31.2.2.27 IMASK Register (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 31-51 and described in Table 31-47.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS."

Figure 31-51 IMASK Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-47 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25TOVR/W0hTrigger Overflow Event mask
0h = Disable Event
1h = Enable Event
24RESERVEDR/W0hReserved
23-16RESERVEDR/W0h
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9CCU1R/W0hCapture or Compare UP event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8CCU0R/W0hCapture or Compare UP event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5CCD1R/W0hCapture or Compare DN event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4CCD0R/W0hCapture or Compare DN event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3-2RESERVEDR/W0h
1LR/W0hLoad Event mask
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0ZR/W0hZero Event mask
0h = Disable Event
1h = Enable Event

31.2.2.28 RIS Register (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 31-52 and described in Table 31-48.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 31-52 RIS Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-48 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24RESERVEDR0hReserved
23-16RESERVEDR0h
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

31.2.2.29 MIS Register (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 31-53 and described in Table 31-49.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 31-53 MIS Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-49 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24RESERVEDR0hReserved
23-16RESERVEDR0h
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

31.2.2.30 ISET Register (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 31-54 and described in Table 31-50.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 31-54 ISET Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-50 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28RESERVEDW0hReserved
27RESERVEDW0hReserved
26RESERVEDW0hReserved
25TOVW0hTrigger Overflow event SET
0h = Writing 0 has no effect.
1h = Event Set
24RESERVEDW0hReserved
23-16RESERVEDW0h
15RESERVEDW0hReserved
14RESERVEDW0hReserved
13RESERVEDW0hReserved
12RESERVEDW0hReserved
11RESERVEDW0hReserved
10RESERVEDW0hReserved
9CCU1W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
8CCU0W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
7RESERVEDW0hReserved
6RESERVEDW0hReserved
5CCD1W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
4CCD0W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
3-2RESERVEDW0h
1LW0h Load event SET
0h = Writing 0 has no effect.
1h = Event Set
0ZW0h Zero event SET
0h = Writing 0 has no effect.
1h = Event Set

31.2.2.31 ICLR Register (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 31-55 and described in Table 31-51.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 31-55 ICLR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-51 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28RESERVEDW0hReserved
27RESERVEDW0hReserved
26RESERVEDW0hReserved
25TOVW0hTrigger Overflow event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
24RESERVEDW0hReserved
23-16RESERVEDW0h
15RESERVEDW0hReserved
14RESERVEDW0hReserved
13RESERVEDW0hReserved
12RESERVEDW0hReserved
11RESERVEDW0hReserved
10RESERVEDW0hReserved
9CCU1W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
8CCU0W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
7RESERVEDW0hReserved
6RESERVEDW0hReserved
5CCD1W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
4CCD0W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
3-2RESERVEDW0h
1LW0h Load event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
0ZW0h Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear

31.2.2.32 IIDX Register (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 31-56 and described in Table 31-52.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, ... IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 31-56 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 31-52 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = Interrupt Source: Zero event (Z)
02h = nterrupt Source: Load event (L)
05h = Interrupt Source: Capture or compare down event (CCD0)
06h = Interrupt Source: Capture or compare down event (CCD1)
07h = Interrupt Source: Capture or compare down event (CCD2)
08h = Interrupt Source: Capture or compare down event (CCD3)
09h = Interrupt Source: Capture or compare up event (CCU0)
0Ah = Interrupt Source: Capture or compare up event (CCU1)
0Bh = Interrupt Source: Capture or compare up event (CCU2)
0Ch = Interrupt Source: Capture or compare up event (CCU3)
0Dh = Interrupt Source: Compare down event (CCD4)
0Eh = Interrupt Source: Compare down event (CCD5)
0Fh = Interrupt Source: Compare down event (CCU4)
10h = Interrupt Source: Compare down event (CCU5)
19h = Interrupt Source: Fault Event generated an interrupt. (F)
1Ah = Interrupt Source: Trigger overflow (TOV)
1Bh = Interrupt Source: Repeat Counter Zero (REPC)
1Ch = Interrupt Source: Direction Change (DC)
1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR)

31.2.2.33 IMASK Register (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 31-57 and described in Table 31-53.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS."

Figure 31-57 IMASK Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-53 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25TOVR/W0hTrigger Overflow Event mask
0h = Disable Event
1h = Enable Event
24RESERVEDR/W0hReserved
23-16RESERVEDR/W0h
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9CCU1R/W0hCapture or Compare UP event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8CCU0R/W0hCapture or Compare UP event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5CCD1R/W0hCapture or Compare DN event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4CCD0R/W0hCapture or Compare DN event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3-2RESERVEDR/W0h
1LR/W0hLoad Event mask
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0ZR/W0hZero Event mask
0h = Disable Event
1h = Enable Event

31.2.2.34 RIS Register (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 31-58 and described in Table 31-54.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 31-58 RIS Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-54 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24RESERVEDR0hReserved
23-16RESERVEDR0h
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

31.2.2.35 MIS Register (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 31-59 and described in Table 31-55.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 31-59 MIS Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-55 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24RESERVEDR0hReserved
23-16RESERVEDR0h
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

31.2.2.36 ISET Register (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 31-60 and described in Table 31-56.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 31-60 ISET Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-56 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28RESERVEDW0hReserved
27RESERVEDW0hReserved
26RESERVEDW0hReserved
25TOVW0hTrigger Overflow event SET
0h = Writing 0 has no effect.
1h = Event Set
24RESERVEDW0hReserved
23-16RESERVEDW0h
15RESERVEDW0hReserved
14RESERVEDW0hReserved
13RESERVEDW0hReserved
12RESERVEDW0hReserved
11RESERVEDW0hReserved
10RESERVEDW0hReserved
9CCU1W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
8CCU0W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
7RESERVEDW0hReserved
6RESERVEDW0hReserved
5CCD1W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
4CCD0W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
3-2RESERVEDW0h
1LW0h Load event SET
0h = Writing 0 has no effect.
1h = Event Set
0ZW0h Zero event SET
0h = Writing 0 has no effect.
1h = Event Set

31.2.2.37 ICLR Register (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 31-61 and described in Table 31-57.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 31-61 ICLR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDTOVRESERVED
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESERVEDRESERVEDCCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-57 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28RESERVEDW0hReserved
27RESERVEDW0hReserved
26RESERVEDW0hReserved
25TOVW0hTrigger Overflow event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
24RESERVEDW0hReserved
23-16RESERVEDW0h
15RESERVEDW0hReserved
14RESERVEDW0hReserved
13RESERVEDW0hReserved
12RESERVEDW0hReserved
11RESERVEDW0hReserved
10RESERVEDW0hReserved
9CCU1W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
8CCU0W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
7RESERVEDW0hReserved
6RESERVEDW0hReserved
5CCD1W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
4CCD0W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
3-2RESERVEDW0h
1LW0h Load event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
0ZW0h Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear

31.2.2.38 EVT_MODE Register (Offset = 10E0h) [Reset = 00000029h]

EVT_MODE is shown in Figure 31-62 and described in Table 31-58.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 31-62 EVT_MODE Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEVT2_CFGEVT1_CFGEVT0_CFG
R/W-0hR-2hR-2hR-1h
Table 31-58 EVT_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-4EVT2_CFGR2hEvent line mode select for event corresponding to GEN_EVENT1
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2EVT1_CFGR2hEvent line mode select for event corresponding to GEN_EVENT0
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0EVT0_CFGR1hEvent line mode select for event corresponding to CPU_INT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

31.2.2.39 DESC Register (Offset = 10FCh) [Reset = 00000000h]

DESC is shown in Figure 31-63 and described in Table 31-59.

Return to the Summary Table.

This register identifies the peripheral and its exact version.

Figure 31-63 DESC Register
31302928272625242322212019181716
MODULEID
R-0h
1514131211109876543210
FEATUREVERINSTNUMMAJREVMINREV
R-0hR-0hR-0hR-0h
Table 31-59 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR1111hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERR0hFeature Set for the module *instance*
0h = Smallest value
Fh = Highest possible value
11-8INSTNUMR0hInstance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0h = Smallest value
Fh = Highest possible value
7-4MAJREVR0hMajor rev of the IP
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
0h = Smallest value
Fh = Highest possible value

31.2.2.40 CCPD Register (Offset = 1100h) [Reset = 00000000h]

CCPD is shown in Figure 31-64 and described in Table 31-60.

Return to the Summary Table.

CCP Direction. Controls whether CCP is used as an input or an output.

Figure 31-64 CCPD Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVEDC0CCP1C0CCP0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-60 CCPD Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1C0CCP1R/W0hCCP1 direction
0h = Input
1h = Output
0C0CCP0R/W0hCCP0 direction
0h = Input
1h = Output

31.2.2.41 ODIS Register (Offset = 1104h) [Reset = 00000000h]

ODIS is shown in Figure 31-65 and described in Table 31-61.

Return to the Summary Table.

The ODIS register output is inverted and then ANDed with the output signal selected by the OCTL register CCPO field (before conditional inversion) to allow software the ability to hold the CCP output low during configuration or shutdown.

Figure 31-65 ODIS Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVEDC0CCP1C0CCP0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-61 ODIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1C0CCP1R/W0hCounter CCP1 Disable Mask
Defines whether CCP0 of Counter n is forced low or not

0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block.
1h = CCP output occpout[1] is forced low.
0C0CCP0R/W0hCounter CCP0 Disable Mask
Defines whether CCP0 of Counter n is forced low or not

0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block.
1h = CCP output occpout[0] is forced low.

31.2.2.42 CCLKCTL Register (Offset = 1108h) [Reset = 00000000h]

CCLKCTL is shown in Figure 31-66 and described in Table 31-62.

Return to the Summary Table.

The CCLKCTL register provides a SW mechanism for gating the TIMER clock
if the module is expected not to be used but the power domain is alive.
This effectively puts the IP in an IDLE state

Figure 31-66 CCLKCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCLKEN
R/W-0hR/W-0h
Table 31-62 CCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0CLKENR/W0hClock Enable
Disables the clock gating to the module. SW has to explicitly program the value
to 0 to gate the clock.

0h = Clock is disabled.
1h = Clock is enabled

31.2.2.43 CPS Register (Offset = 110Ch) [Reset = 00000000h]

CPS is shown in Figure 31-67 and described in Table 31-63.

Return to the Summary Table.

The CPS register provides the value for the clock pre-scaler.

Figure 31-67 CPS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPCNT
R/W-0hR/W-0h
Table 31-63 CPS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0PCNTR/W0hPre-Scale Count
This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1).
A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider.
A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock

0h = Minimum value

FFh = Maximum Value

31.2.2.44 CPSV Register (Offset = 1110h) [Reset = 00000000h]

CPSV is shown in Figure 31-68 and described in Table 31-64.

Return to the Summary Table.

The CPSV register provides the ability to read the current clock prescale count value.

Figure 31-68 CPSV Register
313029282726252423222120191817161514131211109876543210
RESERVEDCPSVAL
R-0hR-0h
Table 31-64 CPSV Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0CPSVALR0hCurrent Prescale Count Value
0h = Minimum value

FFh = Maximum Value

31.2.2.45 CTTRIGCTL Register (Offset = 1114h) [Reset = 00000000h]

CTTRIGCTL is shown in Figure 31-69 and described in Table 31-65.

Return to the Summary Table.

Cross Timer Trigger Control Register
This register is used to control the cross trigger connections for enables and faults of different timer instances in the same power domain. Please refer to sections Timer Module Cross Trigger (In/Out) and Fault Cross Triggering for details.

Figure 31-69 CTTRIGCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDEVTCTTRIGSEL
R/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEVTCTENCTEN
R/W-0hR/W-0hR/W-0h
Table 31-65 CTTRIGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
19-16EVTCTTRIGSELR/W0hUsed to Select the subscriber port that should be used for input cross trigger.
0h = Use FSUB0 as cross trigger source.
1h = Use FSUB1 as cross trigger source.
2h = Use Zero event as cross trigger source.
3h = Use Load event as cross trigger source.
4h = Use CCD0 event as cross trigger source.
5h = Use CCD1 event as cross trigger source.
6h = Use CCD2 event as cross trigger source.
7h = Use CCD3 event as cross trigger source.
8h = Use CCU0 event as cross trigger source.
9h = Use CCU1 event as cross trigger source.
Ah = Use CCU2 event as cross trigger source.
Bh = Use CCU3 event as cross trigger source.
15-2RESERVEDR/W0h
1EVTCTENR/W0hEnable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers.
0h = Cross trigger generation disabled.
1h = Cross trigger generation enabled
0CTENR/W0hTimer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system.
These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain.

The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0h = Cross trigger generation disabled.
1h = Cross trigger generation enabled

31.2.2.46 CTTRIG Register (Offset = 111Ch) [Reset = 00000000h]

CTTRIG is shown in Figure 31-70 and described in Table 31-66.

Return to the Summary Table.

Cross Timer Trigger Register
This register is used to trigger the timer instances connected and enabled using CTTRIGCTL and CTTRIGMSK registers.

Figure 31-70 CTTRIG Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDTRIG
W-0hW-0h
Table 31-66 CTTRIG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0TRIGW0hGenerate Cross Trigger
This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.

0h = Cross trigger generation disabled
1h = Generate Cross trigger pulse

31.2.2.47 CTR Register (Offset = 1800h) [Reset = 00000000h]

CTR is shown in Figure 31-71 and described in Table 31-67.

Return to the Summary Table.

This is the TIMER counter register.
This can be set by SW. However, the writes will be unpredictable if the software
tries to set a value while the counter is running.

Figure 31-71 CTR Register
313029282726252423222120191817161514131211109876543210
RESERVEDCCTR
R/W-0hR/W-0h
Table 31-67 CTR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0CCTRR/W0h Current Counter value
0h = Minimum value

FFFFFFFFh = Maximum Value

31.2.2.48 CTRCTL Register (Offset = 1804h) [Reset = 0000FF80h]

CTRCTL is shown in Figure 31-72 and described in Table 31-68.

Return to the Summary Table.

This register provides control over the counter operation.
The configuration can change as well as setting the EN bit in a single write.
There is no requirement to change the configuration first and then do an
additional write to set the EN bit.

Figure 31-72 CTRCTL Register
3130292827262524
RESERVEDCVAERESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDDRBRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CZCCACCLC
R/W-7hR/W-7hR/W-7h
76543210
CLCRESERVEDCMREPEATEN
R/W-7hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-68 CTRCTL Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29-28CVAER/W0h Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0h = The counter is set to the LOAD register value
1h = The counter value is unchanged from its current value which could have been initialized by software
2h = The counter is set to zero
27-25RESERVEDR/W0h
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22-20RESERVEDR/W0h
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17DRBR/W0h Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0h = Resume counting
1h = Perform the action as specified by the CVAE field.
16RESERVEDR/W0h
15-13CZCR/W7h Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value.

Encodings 1-3 are present based on the CCPC
parameter value. Bits 4-5 are present based on
the HQEI parameter value. Any encodings not
provided are documented as reserved.
0h = CCCTL_0 ZCOND
1h = CCCTL_1 ZCOND
2h = CCCTL_2 ZCOND
This value exists when there are 4 channels.
3h = CCCTL_3 ZCOND
This value exists when there are 4 channels.
4h = Controlled by 2-input QEI mode

This value exists when TIMER support QEI feature.
5h = Controlled by 3-input QEI mode

This value exists when TIMER support QEI feature.
12-10CACR/W7h Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value.
Encodings 1-3 are present based on the CCPC
parameter value. Bits 4-5 are present based on
the HQEI parameter value. Any encodings not
provided are documented as reserved.
0h = CCCTL_0 ACOND
1h = CCCTL_1 ACOND
2h = CCCTL_2 ACOND
This value exists when there are 4 channels.
3h = CCCTL_3 ACOND
This value exists when there are 4 channels.
4h = Controlled by 2-input QEI mode

This value exists when TIMER support QEI feature.
5h = Controlled by 3-input QEI mode

This value exists when TIMER support QEI feature.
9-7CLCR/W7h Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value.

Encodings 1-3 are present based on the CCPC
parameter value. Bits 4-5 are present based on
the HQEI parameter value. Any encodings not
provided are documented as reserved.
0h = CCCTL_0 LCOND
1h = CCCTL_1 LCOND
2h = CCCTL_2 LCOND
This value exists when there are 4 channels.
3h = CCCTL_3 LCOND
This value exists when there are 4 channels.
4h = Controlled by 2 input QEI mode.
This value exists when TIMER support QEI feature.
5h = Controlled by 3 input QEI mode.

This value exists when TIMER support QEI feature.
6RESERVEDR/W0h
5-4CMR/W0h Count Mode
0h = Down
1h = Up/Down
2h = Counter counts up.
3-1REPEATR/W0h Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0h = Does not automatically advance following a zero event.
1h = Continues to advance following a zero event.
2h = Reserved
3h = Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode.
4h = Reserved
0ENR/W0h Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0h = Disabled
1h = Enabled

31.2.2.49 LOAD Register (Offset = 1808h) [Reset = 00000000h]

LOAD is shown in Figure 31-73 and described in Table 31-69.

Return to the Summary Table.

The contents of LOAD register are copied to CTR on any operation designated to do a "LOAD". The LOAD is used to compare with the CTR for generating a "Load Event" that can be used for interrupt, trigger, or signal generator actions.

Figure 31-73 LOAD Register
313029282726252423222120191817161514131211109876543210
RESERVEDLD
R/W-0hR/W-0h
Table 31-69 LOAD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0LDR/W0h Load Value
0h = Minimum value

FFFFFFFFh = Maximum Value

31.2.2.50 CC_01_y Register (Offset = 1810h + formula) [Reset = 00000000h]

CC_01_y is shown in Figure 31-74 and described in Table 31-70.

Return to the Summary Table.

The CC_01 register is a register that can be used as either a capture register, to capture the next CTR value on an event, or a compare to the current CTR to create an event. It cannot operate concurrently as both. There are two Capture-Compare slices of hardware for each counter, hence there are two CC_01 registers per timer. On a capture event, the next value of the CTR is loaded so that CTR and CC_01 (which captured) will be equal on the cycle that an interrupt or trigger is created from the capture action.

Offset = 1810h + (y * 4h); where y = 0h to 1h

Figure 31-74 CC_01_y Register
313029282726252423222120191817161514131211109876543210
RESERVEDCCVAL
R/W-0hR/W-0h
Table 31-70 CC_01_y Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0CCVALR/W0h Capture or compare value
0h = Minimum value

FFFFFFFFh = Maximum Value

31.2.2.51 CCCTL_01_y Register (Offset = 1830h + formula) [Reset = 00000000h]

CCCTL_01_y is shown in Figure 31-75 and described in Table 31-71.

Return to the Summary Table.

The CCCTL_01 registers control the operations of the respective CC registers and the counter.

Offset = 1830h + (y * 4h); where y = 0h to 1h

Figure 31-75 CCCTL_01_y Register
3130292827262524
CC2SELDCCACTUPDRESERVEDCC2SELU
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CC2SELURESERVEDRESERVEDCOCRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDZCONDRESERVEDLCOND
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDACONDRESERVEDCCOND
R/W-0hR/W-0hR/W-0hR/W-0h
Table 31-71 CCCTL_01_y Register Field Descriptions
BitFieldTypeResetDescription
31-29CC2SELDR/W0hSelects the source second CCD event.
0h = Selects CCD from CC0.
1h = Selects CCD from CC1.
2h = Selects CCD from CC2.
3h = Selects CCD from CC3.
4h = Selects CCD from CC4.
5h = Selects CCD from CC5.
28-26CCACTUPDR/W0hCCACT shadow register Update Method
This field controls how updates to the CCACT shadow register are performed

0h = Value written to the CCACT register has immediate effect.
1h = Following a zero event (CTR=0)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0.
2h = Following a CCD event (CTR=CC_xy)
Writes to the CCACTx_y register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals the CCx_y register value.
3h = Following a CCU event (CTR=CC_xy)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals the CCx_y register
value.
4h = Following a zero event (CTR=0) or load event (CTR = LOAD)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0 or CTR. Equals
LDn.

Note this update mechanism is
defined for use only in
configurations using up/down
counting. This mode is not intended for use in down count
configurations.
5h = Following a zero event (CTR=0) with repeat count also zero (RC=0).

Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0 and if RC equal
0.
6h = On a TRIG pulse, the value stored in CCACT_xy shadow register is loaded into CCACT_xy register.
25RESERVEDR/W0hReserved
24-22CC2SELUR/W0hSelects the source second CCU event.
0h = Selects CCU from CC0.
1h = Selects CCU from CC1.
2h = Selects CCU from CC2.
3h = Selects CCU from CC3.
4h = Selects CCU from CC4.
5h = Selects CCU from CC5.
21RESERVEDR/W0h
20-18RESERVEDR/W0hReserved
17COCR/W0h Capture or Compare.
Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0h = Compare
1h = Capture
16-15RESERVEDR/W0h
14-12ZCONDR/W0h Zero Condition.
This field specifies the condition that generates a zero pulse.
0h = CCP edges have no effect
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
11RESERVEDR/W0h
10-8LCONDR/W0h Load Condition.
Specifies the condition that generates a load pulse.
0h = CCP edges have no effect
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
7RESERVEDR/W0h
6-4ACONDR/W0h Advance Condition.
Specifies the condition that generates an advance pulse.
0h = Each TIMCLK
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
5h = CCP High or Trigger assertion (level)
3RESERVEDR/W0h
2-0CCONDR/W0h Capture Condition.
Specifies the condition that generates a capture pulse.
0h = None (never captures)
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)

31.2.2.52 OCTL_01_y Register (Offset = 1850h + formula) [Reset = 00000000h]

OCTL_01_y is shown in Figure 31-76 and described in Table 31-72.

Return to the Summary Table.

The OCTL_01 register controls the CCP output of the Capture-Compare slice of the counter. This includes the ability to select the source of what is driven out along with initial condition values and final inversion options.

Offset = 1850h + (y * 4h); where y = 0h to 1h

Figure 31-76 OCTL_01_y Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCCPIVCCPOINVCCPO
R/W-0hR/W-0hR/W-0hR/W-0h
Table 31-72 OCTL_01_y Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5CCPIVR/W0h CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0h = Low
1h = High
4CCPOINVR/W0h CCP Output Invert The output as selected by CCPO is conditionally inverted.
0h = No inversion
1h = Invert
3-0CCPOR/W0h CCP Output Source
0h = Signal generator value (for example, PWM, triggered PWM)
1h = Load event
2h = CCU event or CCD event
4h = Zero event
5h = Capture event
6h = Fault condition
8h = Mirror CCP of first capture and compare register to other capture compare blocks
9h = Mirror CCP of second capture and compare register in other capture compare blocks
Ch = Signal generator output after deadband insertion
Dh = Counter direction

31.2.2.53 CCACT_01_y Register (Offset = 1870h + formula) [Reset = 00000000h]

CCACT_01_y is shown in Figure 31-77 and described in Table 31-73.

Return to the Summary Table.

The CCACT_01 register controls the actions of the signal generator of the capture-compare slice based on the events created in the counter block, the capture and compare block and debug events.

Offset = 1870h + (y * 4h); where y = 0h to 1h

Figure 31-77 CCACT_01_y Register
3130292827262524
RESERVEDSWFRCACTRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDCC2UACT
R/W-0hR/W-0hR/W-0h
15141312111098
CC2UACTRESERVEDCC2DACTRESERVEDCUACTRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CDACTRESERVEDLACTRESERVEDZACT
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-73 CCACT_01_y Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28SWFRCACTR/W0hCCP Output Action on Software Force Output

This field describes the resulting action of software force.

This action has a shadow register, which will be updated under specific condition.
So that this register cannot take into effect immediately.


0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
27-25RESERVEDR/W0hReserved
24-22RESERVEDR/W0hReserved
21-17RESERVEDR/W0h
16-15CC2UACTR/W0h CCP Output Action on CC2U event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
14RESERVEDR/W0h
13-12CC2DACTR/W0h CCP Output Action on CC2D event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
11RESERVEDR/W0h
10-9CUACTR/W0h CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
8RESERVEDR/W0h
7-6CDACTR/W0h CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
5RESERVEDR/W0h
4-3LACTR/W0h CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
2RESERVEDR/W0h
1-0ZACTR/W0h CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled

31.2.2.54 IFCTL_01_y Register (Offset = 1880h + formula) [Reset = 00000000h]

IFCTL_01_y is shown in Figure 31-78 and described in Table 31-74.

Return to the Summary Table.

The IFCTL_01 register controls the input selection and inversion for the associated Capture-Compare slice.

Offset = 1880h + (y * 4h); where y = 0h to 1h

Figure 31-78 IFCTL_01_y Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDFECPVRESERVEDFP
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
INVRESERVEDISEL
R/W-0hR/W-0hR/W-0h
Table 31-74 IFCTL_01_y Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR/W0h
12FER/W0hFilter Enable
This bit controls whether the input is filtered by
the input filter or bypasses to the edge
detect.
0h = Bypass.
1h = Filtered.
11CPVR/W0hConsecutive Period/Voting Select

This bit controls whether the input filter uses a
stricter consecutive period count or majority
voting.
0h = Consecutive Periods
The input must be at a specific logic level for the period defined by FP before it is passed to the filter output.
1h = Voting

The filter ignores one clock of
opposite logic over the filter
period.
I.e. Over FP samples of the
input, up to 1 sample may be of
an opposite logic value (glitch)
without affecting the output.
10RESERVEDR/W0h
9-8FPR/W0hFilter Period. This field specifies the sample period for the
input filter. I.e. The input is sampled for FP
timer clocks during filtering.
0h = The division factor is 3
1h = The division factor is 5
2h = The division factor is 8
7INVR/W0h Input Inversion This bit controls whether the selected input is inverted.
0h = Noninverted
1h = Inverted
6-4RESERVEDR/W0h
3-0ISELR/W0h Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0h = CCP of the corresponding capture compare unit
1h = Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0.
2h = CCP0 of the counter
3h = Trigger
4h = XOR of CCP inputs as input source (Used in Hall input mode).
5h = subscriber 0 event as input source.
6h = subscriber 1 event as input source.
7h = Comparator 0 output.
8h = Comparator 1 output.
9h = Comparator 2 output.

31.2.2.55 TSEL Register (Offset = 18B0h) [Reset = 00000000h]

TSEL is shown in Figure 31-79 and described in Table 31-75.

Return to the Summary Table.

The TSEL register controls the input trigger enable and selection of the trigger source. Trigger sources are generated by other SoC elements through their respective publisher ports (subscribed in by the timer's subscriber port).

Figure 31-79 TSEL Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDTERESERVEDETSEL
R/W-0hR/W-0hR/W-0hR/W-0h
Table 31-75 TSEL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9TER/W0hTrigger Enable.
This selects whether a trigger is enabled or not for this counter
0x0 = Triggers are not used
0x1 = Triggers are used as selected by the ETSEL field
0h = Triggers are not used.
1h = Triggers are used as selected by the IE, ITSEL and ETSEL fields.
8-5RESERVEDR/W0h
4-0ETSELR/W0hExternal Trigger Select.
This selects which System Event is used if the input filter selects trigger.
Triggers 0-15 are used to connect triggers generated by other timer modules. Refer to the SoC datasheet for details related to timer trigger sources.
Triggers 16 and 17 are connected to event manager subscriber ports.
Event lines 18-31 are reserved for future use.
0h = TRIGx = External trigger input from TIM x.
1h = TRIGx = External trigger input from TIM x.
2h = TRIGx = External trigger input from TIM x.
3h = TRIGx = External trigger input from TIM x.
4h = TRIGx = External trigger input from TIM x.
5h = TRIGx = External trigger input from TIM x.
6h = TRIGx = External trigger input from TIM x.
7h = TRIGx = External trigger input from TIM x.
8h = TRIGx = External trigger input from TIM x.
9h = TRIGx = External trigger input from TIM x.
Ah = TRIGx = External trigger input from TIM x.
Bh = TRIGx = External trigger input from TIM x.
Ch = TRIGx = External trigger input from TIM x.
Dh = TRIGx = External trigger input from TIM x.
Eh = TRIGx = External trigger input from TIM x.
Fh = TRIGx = External trigger input from TIM x.
10h = TRIG_SUBx = External trigger input from subscriber port x.
11h = TRIG_SUBx = External trigger input from subscriber port x.