SPRUJF2 User guide | 德州仪器 TI.com.cn

SPRUJF2A March 2026 – March 2026 AM13E23019

1
Read This First
1. About This Manual
2. Notational Conventions
3. Glossary
4. Related Documentation
5. Support Resources
6. Trademarks
1 Introduction
1. 1.1 Overview
2. 1.2 AM13E230x Architecture Overview
3. 1.3 Platform Memory Map
4. 1.4 Boot Configuration
  1. 1.4.1 Configuration Memory
  2. 1.4.2 FLNONMAINECC Registers
5. 1.5 Factory Constants
  1. 1.5.1 FLASH Registers
6. 1.6 Memory Configuration
  1. 1.6.1 MEMCFG Registers
    1. 1.6.1.1 MEMCFG Base Address Table
    2. 1.6.1.2 MEM_CFG_REGS Registers
2 Peripheral Registers Memory Map
3 Power Management and Clock Unit (PMCU)
1. 3.1 PMCU Overview
  1. 3.1.1 Power Domains
  2. 3.1.2 Operating Modes
2. 3.2 Quick Start Reference
3. 3.3 Power Management (PMU)
4. 3.4 Clock Module (CKM)
5. 3.5 System Controller (SYSCTL)
6. 3.6 SYSCTL Registers
  1. 3.6.1 SYSCTL Base Address Table
  2. 3.6.2 SYSCTL_REGS Registers
4 Central Processing Unit (CPU)
1. 4.1 Overview
2. 4.2 CPU
3. 4.3 Interrupts and Exceptions
4. 4.4 CPU Peripherals
5. 4.5 Read-Only Memory (ROM)
5 Trigonometric Math Unit (TMU)
1. 5.1 Introduction
2. 5.2 Features
3. 5.3 Functional Operation
  1. 5.3.1 Supported TMU Instructions
6 TinyEngine™ NPU
1. 6.1 Introduction
  1. 6.1.1 TinyEngine™ NPU Related Collateral
7 Secure ROM
1. 7.1 ROM Overview
2. 7.2 Memory Map
3. 7.3 Boot Configuration Routine (BCR)
  1. 7.3.1 SWD Mass Erase and Factory Reset Commands
  2. 7.3.2 Fast Boot
4. 7.4 Bootstrap Loader (BSL)
5. 7.5 Lifecycle Management
  1. 7.5.1 Device Sub-Type
  2. 7.5.2 Lifecycle Transitions
6. 7.6 Boot and Startup Sequence
  1. 7.6.1 Secure Boot
  2. 7.6.2 Customer Secure Code (CSC)
8 Global Security Controller (GSC)
1. 8.1 GSC Introduction
  1. 8.1.1 GSC Features
2. 8.2 GSC Operation
3. 8.3 GSC Registers
  1. 8.3.1 GSC Base Address Table
  2. 8.3.2 GSC_LITE_REGS Registers
9 Direct Memory Access (DMA)
1. 9.1 DMA Overview
2. 9.2 DMA Operation
3. 9.3 DMA Registers
  1. 9.3.1 DMA Base Address Table
  2. 9.3.2 DMA_REGS Registers
10Flash Module
1. 10.1 Flash (NVM)
2. 10.2 FLASH Registers
11Error Aggregator Module (EAM)
1. 11.1 EAM
  1. 11.1.1 EAM Introduction
  2. 11.1.2 EAM Operation
2. 11.2 EAM Registers
  1. 11.2.1 EAM Base Address Table
  2. 11.2.2 EAM_REGS Registers
12Events
1. 12.1 Events Overview
13IOMUX
1. 13.1 IOMUX
  1. 13.1.1 IOMUX Overview
    1. 13.1.1.1 IO Types and Analog Sharing
  2. 13.1.2 IOMUX Operation
2. 13.2 IOMUX Registers
  1. 13.2.1 IOMUX Base Address Table
  2. 13.2.2 IOMUX_REGS Registers
14General Purpose Input/Output (GPIO)
1. 14.1 General-Purpose Input/Output (GPIO)
  1. 14.1.1 GPIO Overview
  2. 14.1.2 GPIO Operation
2. 14.2 GPIO Registers
  1. 14.2.1 GPIO Base Address Table
  2. 14.2.2 GPIO_REGS Registers
15Analog-to-Digital Converter (ADC)
1. 15.1 Introduction
2. 15.2 ADC Configurability
3. 15.3 SOC Principle of Operation
4. 15.4 SOC Configuration Examples
5. 15.5 EOC and Interrupt Operation
6. 15.6 Post-Processing Blocks
7. 15.7 Opens/Shorts Detection Circuit (OSDETECT)
8. 15.8 Power-Up Sequence
9. 15.9 ADC Calibration
10. 15.10 ADC Timings
  1. 15.10.1 ADC Timing Diagrams
  2. 15.10.2 Post-Processing Block Timings
11. 15.11 Additional Information
12. 15.12 ADC Registers
16Comparator Subsystem (CMPSS)
1. 16.1 Introduction
2. 16.2 Comparator
3. 16.3 Reference DAC
4. 16.4 Digital Filter
  1. 16.4.1 Filter Initialization Sequence
5. 16.5 Using the CMPSS
6. 16.6 CMPSS DAC Output
7. 16.7 CMPSS Registers
  1. 16.7.1 CMPSS Base Address Table
  2. 16.7.2 CMPSS_LITE_REGS Registers
17Programmable Gain Amplifier (PGA)
1. 17.1 Programmable Gain Amplifier (PGA) Overview
  1. 17.1.1 Features
  2. 17.1.2 Block Diagram
    1. 17.1.2.1 PGA Mux Selection Options
2. 17.2 Linear Output Range
3. 17.3 Gain Values
4. 17.4 Modes of Operation
5. 17.5 External Filtering
  1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
  2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
6. 17.6 Error Calibration
  1. 17.6.1 Offset Error
  2. 17.6.2 Gain Error
7. 17.7 Chopping Feature
8. 17.8 Enabling and Disabling the PGA Clock
9. 17.9 Lock Register
10. 17.10 Analog Front-End Integration
11. 17.11 Examples
12. 17.12 PGA Registers
  1. 17.12.1 PGA Base Address Table
  2. 17.12.2 PGA_REGS Registers
18Multi-Channel Pulse Width Modulator (MCPWM)
1. 18.1 Introduction
  1. 18.1.1 PWM Related Collateral
  2. 18.1.2 MCPWM Overview
2. 18.2 Configuring Device Pins
3. 18.3 MCPWM Modules Overview
4. 18.4 Time-Base (TB) Submodule
5. 18.5 Counter-Compare (CC) Submodule
6. 18.6 Action-Qualifier (AQ) Submodule
7. 18.7 Dead-Band Generator (DB) Submodule
8. 18.8 Trip-Zone (TZ) Submodule
9. 18.9 Event-Trigger (ET) Submodule
  1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
10. 18.10 PWM Crossbar (X-BAR)
11. 18.11 MCPWM Registers
  1. 18.11.1 MCPWM Base Address Table
  2. 18.11.2 MCPWM_6CH_REGS Registers
19Enhanced Capture (eCAP)
1. 19.1 Introduction
  1. 19.1.1 Features
  2. 19.1.2 ECAP Related Collateral
2. 19.2 Description
3. 19.3 Configuring Device Pins for the eCAP
4. 19.4 Capture and APWM Operating Mode
5. 19.5 Capture Mode Description
6. 19.6 Application of the eCAP Module
7. 19.7 Application of the APWM Mode
  1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
8. 19.8 ECAP Registers
  1. 19.8.1 ECAP Base Address Table
  2. 19.8.2 ECAP_REGS Registers
20Enhanced Quadrature Encoder Pulse (eQEP)
1. 20.1 Introduction
  1. 20.1.1 EQEP Related Collateral
2. 20.2 Configuring Device Pins
3. 20.3 Description
4. 20.4 Quadrature Decoder Unit (QDU)
5. 20.5 Position Counter and Control Unit (PCCU)
6. 20.6 eQEP Edge Capture Unit
7. 20.7 eQEP Watchdog
8. 20.8 eQEP Unit Timer Base
9. 20.9 QMA Module
  1. 20.9.1 Modes of Operation
    1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
    2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
  2. 20.9.2 Interrupt and Error Generation
10. 20.10 eQEP Interrupt Structure
11. 20.11 Software
  1. 20.11.1 EQEP Examples
12. 20.12 EQEP Registers
  1. 20.12.1 EQEP Base Address Table
  2. 20.12.2 EQEP_REGS Registers
21Crossbar (X-BAR)
1. 21.1 INPUTXBAR
2. 21.2 MCPWM and GPIO Output X-BAR
3. 21.3 XBAR Registers
22Unified Communication Peripheral (UNICOMM)
1. 22.1 Overview
  1. 22.1.1 Block Diagram
2. 22.2 Unicomm Architecture
3. 22.3 High-Level Initialization
4. 22.4 Enables & Resets
5. 22.5 Suspending Communication
6. 22.6 UNICOMM Registers
  1. 22.6.1 UNICOMM Base Address Table
  2. 22.6.2 UNICOMM_REGS Registers
7. 22.7 SPG Registers
  1. 22.7.1 SPG Base Address Table
  2. 22.7.2 SPGSS_REGS Registers
23Universal Asychronous Receiver/Transmitter (UART)
1. 23.1 Overview
2. 23.2 Peripheral Functional Description
3. 23.3 UNICOMM-UART Registers
  1. 23.3.1 UNICOMM-UART Base Address Table
  2. 23.3.2 UNICOMMUART_REGS Registers
24Inter-Integrated Circuit (I2C)
1. 24.1 Overview
2. 24.2 Peripheral Functional Description
3. 24.3 UNICOMM-I2C Registers
25Serial Peripheral Interface (SPI)
1. 25.1 Overview
2. 25.2 Peripheral Functional Description
3. 25.3 UNICOMM-SPI Registers
  1. 25.3.1 UNICOMM-SPI Base Address Table
  2. 25.3.2 UNICOMMSPI_REGS Registers
26Modular Controller Area Network (MCAN)
1. 26.1 CAN-FD
2. 26.2 MCAN Registers
  1. 26.2.1 MCAN Base Address Table
  2. 26.2.2 MCAN_REGS Registers
27External Peripheral Interface (EPI)
1. 27.1 External Peripheral Interface (EPI)
2. 27.2 EPI Registers
28Cyclic Redundancy Check (CRC)
1. 28.1 CRC
  1. 28.1.1 CRC Overview
    1. 28.1.1.1 CRC16-CCITT
    2. 28.1.1.2 CRC32-ISO3309
  2. 28.1.2 CRC Operation
    1. 28.1.2.1 CRC Generator Implementation
    2. 28.1.2.2 Configuration
2. 28.2 CRC Registers
  1. 28.2.1 CRC Base Address Table
  2. 28.2.2 CRCP_REGS Registers
29Advanced Encryption Standard (AES) Accelerator
1. 29.1 AESADV
  1. 29.1.1 AES Overview
    1. 29.1.1.1 AESADV Performance
  2. 29.1.2 AESADV Operation
2. 29.2 AES Registers
  1. 29.2.1 AES Base Address Table
  2. 29.2.2 AES_REGS Registers
30Keystore
1. 30.1 Keystore
  1. 30.1.1 Overview
  2. 30.1.2 Detailed Description
2. 30.2 KEYSTORE Registers
  1. 30.2.1 KEYSTORE Base Address Table
  2. 30.2.2 KEYSTORE_REGS Registers
31Timers
1. 31.1 Timers (TIMx)
  1. 31.1.1 TIMx Overview
  2. 31.1.2 TIMx Operation
2. 31.2 TIMERS Registers
32Windowed Watchdog Timer (WWDT)
1. 32.1 Window Watchdog Timer (WWDT)
  1. 32.1.1 WWDT Overview
    1. 32.1.1.1 Watchdog Mode
    2. 32.1.1.2 Interval Timer Mode
  2. 32.1.2 WWDT Operation
2. 32.2 WWDT Registers
  1. 32.2.1 WWDT Base Address Table
  2. 32.2.2 WWDT_REGS Registers
33Debug Subsystem (DEBUGSS)
1. 33.1 Debug Subsystem
  1. 33.1.1 DEBUGSS Overview
  2. 33.1.2 DEBUGSS Operation
2. 33.2 DEBUGSS Registers
  1. 33.2.1 DEBUGSS Base Address Table
  2. 33.2.2 DEBUGSS_REGS Registers
34Revision History

15.12.2 ADC_LITE_REGS Registers

Table 15-15 lists the memory-mapped registers for the ADC_LITE_REGS registers. All register offset addresses not listed in Table 15-15 should be considered as reserved locations and the register contents should not be modified.

Table 15-15 ADC_LITE_REGS Registers

Offset	Acronym	Register Name	Write Protection	Section
0h	ADCCTL1	ADC Control 1 Register	EALLOW	Go
4h	ADCCTL2	ADC Control 2 Register	EALLOW	Go
10h	ADCINTSEL	ADC Interrupt 1, 2, 3 and 4 Selection Register	EALLOW	Go
14h	ADCDMAINTSEL	ADC DMA Interrupt 1, 2, 3 and 4 Selection Register	EALLOW	Go
18h	ADCRAWINTFLG	ADC Raw Interrupt Flag Register		Go
1Ch	ADCINTFLG	ADC Interrupt Flag Register		Go
20h	ADCINTFLGFRC	ADC Interrupt Flag Force Register		Go
24h	ADCINTFLGCLR	ADC Interrupt Flag Clear Register		Go
28h	ADCINTOVF	ADC Interrupt Overflow Register		Go
2Ch	ADCINTOVFCLR	ADC Interrupt Overflow Clear Register		Go
3Ch	ADCSOCFLG1	ADC SOC Flag 1 Register		Go
44h	ADCSOCOVF1	ADC SOC Overflow 1 Register		Go
48h	ADCSOCOVFCLR1	ADC SOC Overflow Clear 1 Register		Go
4Ch	ADCSOC0CTL	ADC SOC0 Control Register	EALLOW	Go
50h	ADCSOC1CTL	ADC SOC1 Control Register	EALLOW	Go
54h	ADCSOC2CTL	ADC SOC2 Control Register	EALLOW	Go
58h	ADCSOC3CTL	ADC SOC3 Control Register	EALLOW	Go
5Ch	ADCSOC4CTL	ADC SOC4 Control Register	EALLOW	Go
60h	ADCSOC5CTL	ADC SOC5 Control Register	EALLOW	Go
64h	ADCSOC6CTL	ADC SOC6 Control Register	EALLOW	Go
68h	ADCSOC7CTL	ADC SOC7 Control Register	EALLOW	Go
6Ch	ADCSOC8CTL	ADC SOC8 Control Register	EALLOW	Go
70h	ADCSOC9CTL	ADC SOC9 Control Register	EALLOW	Go
74h	ADCSOC10CTL	ADC SOC10 Control Register	EALLOW	Go
78h	ADCSOC11CTL	ADC SOC11 Control Register	EALLOW	Go
7Ch	ADCSOC12CTL	ADC SOC12 Control Register	EALLOW	Go
80h	ADCSOC13CTL	ADC SOC13 Control Register	EALLOW	Go
84h	ADCSOC14CTL	ADC SOC14 Control Register	EALLOW	Go
88h	ADCSOC15CTL	ADC SOC15 Control Register	EALLOW	Go
CCh	ADCEVTSTAT	ADC Event Status Register		Go
D0h	ADCEVTCLR	ADC Event Clear Register		Go
D4h	ADCEVTSEL	ADC Event Selection Register	EALLOW	Go
D8h	ADCEVTINTSEL	ADC Event Interrupt Selection Register	EALLOW	Go
E4h	ADCREV	ADC Revision Register		Go
E8h	ADCOFFTRIM	ADC Offset Trim Register 1	EALLOW	Go
100h	ADCPPB1CONFIG	ADC PPB1 Config Register	EALLOW	Go
110h	ADCPPB1TRIPHI	ADC PPB1 Trip High Register	EALLOW	Go
114h	ADCPPB1TRIPLO	ADC PPB1 Trip Low/Trigger Time Stamp Register	EALLOW	Go
120h	ADCPPB2CONFIG	ADC PPB2 Config Register	EALLOW	Go
130h	ADCPPB2TRIPHI	ADC PPB2 Trip High Register	EALLOW	Go
134h	ADCPPB2TRIPLO	ADC PPB2 Trip Low/Trigger Time Stamp Register	EALLOW	Go
140h	ADCPPB3CONFIG	ADC PPB3 Config Register	EALLOW	Go
150h	ADCPPB3TRIPHI	ADC PPB3 Trip High Register	EALLOW	Go
154h	ADCPPB3TRIPLO	ADC PPB3 Trip Low/Trigger Time Stamp Register	EALLOW	Go
160h	ADCPPB4CONFIG	ADC PPB4 Config Register	EALLOW	Go
170h	ADCPPB4TRIPHI	ADC PPB4 Trip High Register	EALLOW	Go
174h	ADCPPB4TRIPLO	ADC PPB4 Trip Low/Trigger Time Stamp Register	EALLOW	Go
180h	ADCINTCYCLE	ADC Early Interrupt Generation Cycle	EALLOW	Go
19Ch	ADCREV2	ADC Wrapper Revision Register		Go
200h	ADCPPB1LIMIT	ADC PPB1Conversion Count Limit Register	EALLOW	Go
204h	ADCPPB1PCOUNT	ADC PPB1 Partial Conversion Count Register		Go
208h	ADCPPB1CONFIG2	ADC PPB1 Sum Shift Register		Go
20Ch	ADCPPB1PSUM	ADC PPB1 Partial Sum Register		Go
240h	ADCPPB2LIMIT	ADC PPB2Conversion Count Limit Register	EALLOW	Go
244h	ADCPPB2PCOUNT	ADC PPB2 Partial Conversion Count Register		Go
248h	ADCPPB2CONFIG2	ADC PPB2 Sum Shift Register		Go
24Ch	ADCPPB2PSUM	ADC PPB2 Partial Sum Register		Go
280h	ADCPPB3LIMIT	ADC PPB3Conversion Count Limit Register	EALLOW	Go
284h	ADCPPB3PCOUNT	ADC PPB3 Partial Conversion Count Register		Go
288h	ADCPPB3CONFIG2	ADC PPB3 Sum Shift Register		Go
28Ch	ADCPPB3PSUM	ADC PPB3 Partial Sum Register		Go
2C0h	ADCPPB4LIMIT	ADC PPB4Conversion Count Limit Register	EALLOW	Go
2C4h	ADCPPB4PCOUNT	ADC PPB4 Partial Conversion Count Register		Go
2C8h	ADCPPB4CONFIG2	ADC PPB4 Sum Shift Register		Go
2CCh	ADCPPB4PSUM	ADC PPB4 Partial Sum Register		Go
320h	ADCSEQCTL	ADC Sequencer common control Register		Go
324h	ADCSEQ1CONFIG_AM13E2X	ADC Sequencer 1 Config register		Go
328h	ADCSEQ2CONFIG_AM13E2X	ADC Sequencer 2 Config register		Go
32Ch	ADCSEQ3CONFIG_AM13E2X	ADC Sequencer 3 Config register		Go
330h	ADCSEQ4CONFIG_AM13E2X	ADC Sequencer 4 Config register		Go
800h	PWREN	Power enable		Go
804h	RSTCTL	Reset Control		Go
814h	STAT	Status Register		Go

Complex bit access types are encoded to fit into small table cells. Table 15-16 shows the codes that are used for access types in this section.

Table 15-16 ADC_LITE_REGS Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
W1S	W 1S	Write 1 to set
WK	W K	Write Write protected by a key
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When this variable is used in a register name, an offset, or an address it refers to the value of a register array.

15.12.2.1 ADCCTL1 Register (Offset = 0h) [Reset = 00000000h]

ADCCTL1 is shown in Figure 15-21 and described in Table 15-17.

Return to the Summary Table.

ADC Control 1 Register

Figure 15-21 ADCCTL1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED		ADCBSY	RESERVED	ADCBSYCHN
R-0h		R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
ADCPWDNZ	RESERVED				INTPULSEPOS	RESERVED
R/W-0h	R-0h				R/W-0h	R-0h

Table 15-17 ADCCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R	0h	Reserved
13	ADCBSY	R	0h	ADC Busy. Set when ADC SOC is generated, cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy and cannot sample another channel Reset type: SYSRSn
12	RESERVED	R	0h	Reserved
11-8	ADCBSYCHN	R	0h	ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated. When ADCBSY=0: holds the value of the last converted SOC When ADCBSY=1: reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted 1h SOC1 is currently processing or was last SOC converted 2h SOC2 is currently processing or was last SOC converted 3h SOC3 is currently processing or was last SOC converted 4h SOC4 is currently processing or was last SOC converted 5h SOC5 is currently processing or was last SOC converted 6h SOC6 is currently processing or was last SOC converted 7h SOC7 is currently processing or was last SOC converted 8h SOC8 is currently processing or was last SOC converted 9h SOC9 is currently processing or was last SOC converted Ah SOC10 is currently processing or was last SOC converted Bh SOC11 is currently processing or was last SOC converted Ch SOC12 is currently processing or was last SOC converted Dh SOC13 is currently processing or was last SOC converted Eh SOC14 is currently processing or was last SOC converted Fh SOC15 is currently processing or was last SOC converted Reset type: SYSRSn
7	ADCPWDNZ	R/W	0h	ADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up Reset type: SYSRSn
6-3	RESERVED	R	0h	Reserved
2	INTPULSEPOS	R/W	0h	ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of MCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse generation occurs at the end of the conversion, 1 cycle prior to the ADC result latching into its result register Reset type: SYSRSn
1-0	RESERVED	R	0h	Reserved

15.12.2.2 ADCCTL2 Register (Offset = 4h) [Reset = 00000000h]

ADCCTL2 is shown in Figure 15-22 and described in Table 15-18.

Return to the Summary Table.

ADC Control 2 Register

Figure 15-22 ADCCTL2 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED			RESERVED				RESERVED
R-0h			R-0h				R/W-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED		PRESCALE
R/W-0h	R/W-0h	R-0h		R/W-0h

Table 15-18 ADCCTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12-9	RESERVED	R	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5-4	RESERVED	R	0h	Reserved
3-0	PRESCALE	R/W	0h	ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 ADCCLK = Input Clock / 1.5 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK = Input Clock / 4.5 1000 ADCCLK = Input Clock / 5.0 1001 ADCCLK = Input Clock / 5.5 1010 ADCCLK = Input Clock / 6.0 1011 ADCCLK = Input Clock / 6.5 1100 ADCCLK = Input Clock / 7.0 1101 ADCCLK = Input Clock / 7.5 1110 ADCCLK = Input Clock / 8.0 1111 ADCCLK = Input Clock / 8.5 Reset type: SYSRSn

15.12.2.3 ADCINTSEL Register (Offset = 10h) [Reset = 00000000h]

ADCINTSEL is shown in Figure 15-23 and described in Table 15-19.

Return to the Summary Table.

ADC Interrupt 1, 2, 3 and 4 Selection Register

Figure 15-23 ADCINTSEL Register

31	30	29	28	27	26	25	24
INT4E	INT4CONT	RESERVED		INT4SEL
R/W-0h	R/W-0h	R-0h		R/W-0h

23	22	21	20	19	18	17	16
INT3E	INT3CONT	RESERVED		INT3SEL
R/W-0h	R/W-0h	R-0h		R/W-0h

15	14	13	12	11	10	9	8
INT2E	INT2CONT	RESERVED		INT2SEL
R/W-0h	R/W-0h	R-0h		R/W-0h

7	6	5	4	3	2	1	0
INT1E	INT1CONT	RESERVED		INT1SEL
R/W-0h	R/W-0h	R-0h		R/W-0h

Table 15-19 ADCINTSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	INT4E	R/W	0h	ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled Reset type: SYSRSn
30	INT4CONT	R/W	0h	ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
29-28	RESERVED	R	0h	Reserved
27-24	INT4SEL	R/W	0h	ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger for ADCINT4 07h EOC7 is trigger for ADCINT4 08h EOC8 is trigger for ADCINT4 09h EOC9 is trigger for ADCINT4 0Ah EOC10 is trigger for ADCINT4 0Bh EOC11 is trigger for ADCINT4 0Ch EOC12 is trigger for ADCINT4 0Dh EOC13 is trigger for ADCINT4 0Eh EOC14 is trigger for ADCINT4 0Fh EOC15 is trigger for ADCINT4 Note : When oversampling is enabled, the end of the last oversampled coversion will trigger the interrupts Reset type: SYSRSn
23	INT3E	R/W	0h	ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled Reset type: SYSRSn
22	INT3CONT	R/W	0h	ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
21-20	RESERVED	R	0h	Reserved
19-16	INT3SEL	R/W	0h	ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger for ADCINT3 07h EOC7 is trigger for ADCINT3 08h EOC8 is trigger for ADCINT3 09h EOC9 is trigger for ADCINT3 0Ah EOC10 is trigger for ADCINT3 0Bh EOC11 is trigger for ADCINT3 0Ch EOC12 is trigger for ADCINT3 0Dh EOC13 is trigger for ADCINT3 0Eh EOC14 is trigger for ADCINT3 0Fh EOC15 is trigger for ADCINT3 Note : When oversampling is enabled, the end of the last oversampled coversion will trigger the interrupts Reset type: SYSRSn
15	INT2E	R/W	0h	ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled Reset type: SYSRSn
14	INT2CONT	R/W	0h	ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
13-12	RESERVED	R	0h	Reserved
11-8	INT2SEL	R/W	0h	ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger for ADCINT2 07h EOC7 is trigger for ADCINT2 08h EOC8 is trigger for ADCINT2 09h EOC9 is trigger for ADCINT2 0Ah EOC10 is trigger for ADCINT2 0Bh EOC11 is trigger for ADCINT2 0Ch EOC12 is trigger for ADCINT2 0Dh EOC13 is trigger for ADCINT2 0Eh EOC14 is trigger for ADCINT2 0Fh EOC15 is trigger for ADCINT2 Note : When oversampling is enabled, the end of the last oversampled coversion will trigger the interrupts Reset type: SYSRSn
7	INT1E	R/W	0h	ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled Reset type: SYSRSn
6	INT1CONT	R/W	0h	ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
5-4	RESERVED	R	0h	Reserved
3-0	INT1SEL	R/W	0h	ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger for ADCINT1 07h EOC7 is trigger for ADCINT1 08h EOC8 is trigger for ADCINT1 09h EOC9 is trigger for ADCINT1 0Ah EOC10 is trigger for ADCINT1 0Bh EOC11 is trigger for ADCINT1 0Ch EOC12 is trigger for ADCINT1 0Dh EOC13 is trigger for ADCINT1 0Eh EOC14 is trigger for ADCINT1 0Fh EOC15 is trigger for ADCINT1 Note : When oversampling is enabled, the end of the last oversampled coversion will trigger the interrupts Reset type: SYSRSn

15.12.2.4 ADCDMAINTSEL Register (Offset = 14h) [Reset = 00000000h]

ADCDMAINTSEL is shown in Figure 15-24 and described in Table 15-20.

Return to the Summary Table.

ADC DMA Interrupt 1, 2, 3 and 4 Selection Register

Figure 15-24 ADCDMAINTSEL Register

31	30	29	28	27	26	25	24
DMAINT4E	DMAINT4CONT	RESERVED		DMAINT4SEL
R/W-0h	R/W-0h	R-0h		R/W-0h

23	22	21	20	19	18	17	16
DMAINT3E	DMAINT3CONT	RESERVED		DMAINT3SEL
R/W-0h	R/W-0h	R-0h		R/W-0h

15	14	13	12	11	10	9	8
DMAINT2E	DMAINT2CONT	RESERVED		DMAINT2SEL
R/W-0h	R/W-0h	R-0h		R/W-0h

7	6	5	4	3	2	1	0
DMAINT1E	DMAINT1CONT	RESERVED		DMAINT1SEL
R/W-0h	R/W-0h	R-0h		R/W-0h

Table 15-20 ADCDMAINTSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DMAINT4E	R/W	0h	ADCDMAINT4 Interrupt Enable 0 ADCDMAINT4 is disabled 1 ADCDMAINT4 is enabled Reset type: SYSRSn
30	DMAINT4CONT	R/W	0h	ADCDMAINT4 Continue to Interrupt Mode 0 No further ADCDMAINT4 pulses are generated until ADCDMAINT4 flag (in ADCDMAINTFLG register) is cleared by user. 1 ADCDMAINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
29-28	RESERVED	R	0h	Reserved
27-24	DMAINT4SEL	R/W	0h	ADCDMAINT4 EOC Source Select 00h EOC0 is trigger for ADCDMAINT4 01h EOC1 is trigger for ADCDMAINT4 02h EOC2 is trigger for ADCDMAINT4 03h EOC3 is trigger for ADCDMAINT4 04h EOC4 is trigger for ADCDMAINT4 05h EOC5 is trigger for ADCDMAINT4 06h EOC6 is trigger for ADCDMAINT4 07h EOC7 is trigger for ADCDMAINT4 08h EOC8 is trigger for ADCDMAINT4 09h EOC9 is trigger for ADCDMAINT4 0Ah EOC10 is trigger for ADCDMAINT4 0Bh EOC11 is trigger for ADCDMAINT4 0Ch EOC12 is trigger for ADCDMAINT4 0Dh EOC13 is trigger for ADCDMAINT4 0Eh EOC14 is trigger for ADCDMAINT4 0Fh EOC15 is trigger for ADCDMAINT4 Note : When oversampling is enabled, the end of the last oversampled coversion will trigger the DMAINTerrupts Reset type: SYSRSn
23	DMAINT3E	R/W	0h	ADCDMAINT3 Interrupt Enable 0 ADCDMAINT3 is disabled 1 ADCDMAINT3 is enabled Reset type: SYSRSn
22	DMAINT3CONT	R/W	0h	ADCDMAINT3 Continue to Interrupt Mode 0 No further ADCDMAINT3 pulses are generated until ADCDMAINT3 flag (in ADCDMAINTFLG register) is cleared by user. 1 ADCDMAINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
21-20	RESERVED	R	0h	Reserved
19-16	DMAINT3SEL	R/W	0h	ADCDMAINT3 EOC Source Select 00h EOC0 is trigger for ADCDMAINT3 01h EOC1 is trigger for ADCDMAINT3 02h EOC2 is trigger for ADCDMAINT3 03h EOC3 is trigger for ADCDMAINT3 04h EOC4 is trigger for ADCDMAINT3 05h EOC5 is trigger for ADCDMAINT3 06h EOC6 is trigger for ADCDMAINT3 07h EOC7 is trigger for ADCDMAINT3 08h EOC8 is trigger for ADCDMAINT3 09h EOC9 is trigger for ADCDMAINT3 0Ah EOC10 is trigger for ADCDMAINT3 0Bh EOC11 is trigger for ADCDMAINT3 0Ch EOC12 is trigger for ADCDMAINT3 0Dh EOC13 is trigger for ADCDMAINT3 0Eh EOC14 is trigger for ADCDMAINT3 0Fh EOC15 is trigger for ADCDMAINT3 Note : When oversampling is enabled, the end of the last oversampled coversion will trigger the DMAINTerrupts Reset type: SYSRSn
15	DMAINT2E	R/W	0h	ADCDMAINT2 Interrupt Enable 0 ADCDMAINT2 is disabled 1 ADCDMAINT2 is enabled Reset type: SYSRSn
14	DMAINT2CONT	R/W	0h	ADCDMAINT2 Continue to Interrupt Mode 0 No further ADCDMAINT2 pulses are generated until ADCDMAINT2 flag (in ADCDMAINTFLG register) is cleared by user. 1 ADCDMAINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
13-12	RESERVED	R	0h	Reserved
11-8	DMAINT2SEL	R/W	0h	ADCDMAINT2 EOC Source Select 00h EOC0 is trigger for ADCDMAINT2 01h EOC1 is trigger for ADCDMAINT2 02h EOC2 is trigger for ADCDMAINT2 03h EOC3 is trigger for ADCDMAINT2 04h EOC4 is trigger for ADCDMAINT2 05h EOC5 is trigger for ADCDMAINT2 06h EOC6 is trigger for ADCDMAINT2 07h EOC7 is trigger for ADCDMAINT2 08h EOC8 is trigger for ADCDMAINT2 09h EOC9 is trigger for ADCDMAINT2 0Ah EOC10 is trigger for ADCDMAINT2 0Bh EOC11 is trigger for ADCDMAINT2 0Ch EOC12 is trigger for ADCDMAINT2 0Dh EOC13 is trigger for ADCDMAINT2 0Eh EOC14 is trigger for ADCDMAINT2 0Fh EOC15 is trigger for ADCDMAINT2 Note : When oversampling is enabled, the end of the last oversampled coversion will trigger the DMAINTerrupts Reset type: SYSRSn
7	DMAINT1E	R/W	0h	ADCDMAINT1 Interrupt Enable 0 ADCDMAINT1 is disabled 1 ADCDMAINT1 is enabled Reset type: SYSRSn
6	DMAINT1CONT	R/W	0h	ADCDMAINT1 Continue to Interrupt Mode 0 No further ADCDMAINT1 pulses are generated until ADCDMAINT1 flag (in ADCDMAINTFLG register) is cleared by user. 1 ADCDMAINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
5-4	RESERVED	R	0h	Reserved
3-0	DMAINT1SEL	R/W	0h	ADCDMAINT1 EOC Source Select 00h EOC0 is trigger for ADCDMAINT1 01h EOC1 is trigger for ADCDMAINT1 02h EOC2 is trigger for ADCDMAINT1 03h EOC3 is trigger for ADCDMAINT1 04h EOC4 is trigger for ADCDMAINT1 05h EOC5 is trigger for ADCDMAINT1 06h EOC6 is trigger for ADCDMAINT1 07h EOC7 is trigger for ADCDMAINT1 08h EOC8 is trigger for ADCDMAINT1 09h EOC9 is trigger for ADCDMAINT1 0Ah EOC10 is trigger for ADCDMAINT1 0Bh EOC11 is trigger for ADCDMAINT1 0Ch EOC12 is trigger for ADCDMAINT1 0Dh EOC13 is trigger for ADCDMAINT1 0Eh EOC14 is trigger for ADCDMAINT1 0Fh EOC15 is trigger for ADCDMAINT1 Note : When oversampling is enabled, the end of the last oversampled conversion will trigger the DMAINTerrupts Reset type: SYSRSn

15.12.2.5 ADCRAWINTFLG Register (Offset = 18h) [Reset = 00000000h]

ADCRAWINTFLG is shown in Figure 15-25 and described in Table 15-21.

Return to the Summary Table.

ADC Raw Interrupt Flag Register

Figure 15-25 ADCRAWINTFLG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				ADCDMARAWINT4	ADCDMARAWINT3	ADCDMARAWINT2	ADCDMARAWINT1
R-0h				R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCRAWINT4	ADCRAWINT3	ADCRAWINT2	ADCRAWINT1
R-0h				R-0h	R-0h	R-0h	R-0h

Table 15-21 ADCRAWINTFLG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19	ADCDMARAWINT4	R	0h	ADC DMA Raw Interrupt 4 Flag. Reading these flags indicates if the associated ADCDMAINT condition occurred. This flag will be set irrespective of corresponding DMAINTE setting 0 Selected EOC/OSINT event did not occur 1 Selected EOC/OSINT event occurred Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit. Reset type: SYSRSn
18	ADCDMARAWINT3	R	0h	ADC DMA Raw Interrupt 3 Flag. Reading these flags indicates if the associated ADCDMAINT condition occurred. This flag will be set irrespective of corresponding DMAINTE setting 0 Selected EOC/OSINT event did not occur 1 Selected EOC/OSINT event occurred Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit. Reset type: SYSRSn
17	ADCDMARAWINT2	R	0h	ADC DMA Raw Interrupt 2 Flag. Reading these flags indicates if the associated ADCDMAINT condition occurred. This flag will be set irrespective of corresponding DMAINTE setting 0 Selected EOC/OSINT event did not occur 1 Selected EOC/OSINT event occurred Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit. Reset type: SYSRSn
16	ADCDMARAWINT1	R	0h	ADC DMA Raw Interrupt 1 Flag. Reading these flags indicates if the associated ADCDMAINT condition occurred. This flag will be set irrespective of corresponding DMAINTE setting 0 Selected EOC/OSINT event did not occur 1 Selected EOC/OSINT event occurred Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit. Reset type: SYSRSn
15-4	RESERVED	R	0h	Reserved
3	ADCRAWINT4	R	0h	ADC RAW Interrupt 4 Flag. Reading these flags indicates if the associated INT condition occurred. This flag will be set irrespective of corresponding INTE setting 0 Selected EOC/OSINT event did not occur 1 Selected EOC/OSINT event occured Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit. Reset type: SYSRSn
2	ADCRAWINT3	R	0h	ADC RAW Interrupt 3 Flag. Reading these flags indicates if the associated INT condition occurred. This flag will be set irrespective of corresponding INTE setting 0 Selected EOC/OSINT event did not occur 1 Selected EOC/OSINT event occured Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit. Reset type: SYSRSn
1	ADCRAWINT2	R	0h	ADC RAW Interrupt 2 Flag. Reading these flags indicates if the associated INT condition occurred. This flag will be set irrespective of corresponding INTE setting 0 Selected EOC/OSINT event did not occur 1 Selected EOC/OSINT event occured Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit. Reset type: SYSRSn
0	ADCRAWINT1	R	0h	ADC RAW Interrupt 1 Flag. Reading these flags indicates if the associated INT condition occurred. This flag will be set irrespective of corresponding INTE setting 0 Selected EOC/OSINT event did not occur 1 Selected EOC/OSINT event occurred Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit. Reset type: SYSRSn

15.12.2.6 ADCINTFLG Register (Offset = 1Ch) [Reset = 00000000h]

ADCINTFLG is shown in Figure 15-26 and described in Table 15-22.

Return to the Summary Table.

ADC Interrupt Flag Register

Figure 15-26 ADCINTFLG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				ADCDMAINT4	ADCDMAINT3	ADCDMAINT2	ADCDMAINT1
R-0h				R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED				ADCINT4RESULT	ADCINT3RESULT	ADCINT2RESULT	ADCINT1RESULT
R-0h				R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCINT4	ADCINT3	ADCINT2	ADCINT1
R-0h				R-0h	R-0h	R-0h	R-0h

Table 15-22 ADCINTFLG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19	ADCDMAINT4	R	0h	ADC DMA Interrupt 4 Flag. Reading these flags indicates if the associated ADCDMAINT pulse was generated since the last clear. 0 No ADC DMA interru4pt pulse generated 1 ADC DMA interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (DMAINTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
18	ADCDMAINT3	R	0h	ADC DMA Interrupt 3 Flag. Reading these flags indicates if the associated ADCDMAINT pulse was generated since the last clear. 0 No ADC DMA interrupt pulse generated 1 ADC DMA interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (DMAINTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
17	ADCDMAINT2	R	0h	ADC DMA Interrupt 2 Flag. Reading these flags indicates if the associated ADCDMAINT pulse was generated since the last clear. 0 No ADC DMA interrupt pulse generated 1 ADC DMA interrupt pulse generated If the ADC DMA interrupt is placed in continue to interrupt mode (DMAINTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
16	ADCDMAINT1	R	0h	ADC DMA Interrupt 1 Flag. Reading these flags indicates if the associated ADCDMAINT pulse was generated since the last clear. 0 No ADC DMA interrupt pulse generated 1 ADC DMA interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (DMAINTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
15-12	RESERVED	R	0h	Reserved
11	ADCINT4RESULT	R	0h	ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT4 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the NVIC . In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn
10	ADCINT3RESULT	R	0h	ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT3 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the NVIC . In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn
9	ADCINT2RESULT	R	0h	ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT2 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the NVIC . In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn
8	ADCINT1RESULT	R	0h	ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT1 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the NVIC . In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn
7-4	RESERVED	R	0h	Reserved
3	ADCINT4	R	0h	ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
2	ADCINT3	R	0h	ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
1	ADCINT2	R	0h	ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
0	ADCINT1	R	0h	ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn

15.12.2.7 ADCINTFLGFRC Register (Offset = 20h) [Reset = 00000000h]

ADCINTFLGFRC is shown in Figure 15-27 and described in Table 15-23.

Return to the Summary Table.

ADC Interrupt Flag Force Register

Figure 15-27 ADCINTFLGFRC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				ADCDMAINT4	ADCDMAINT3	ADCDMAINT2	ADCDMAINT1
R-0h				R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCINT4	ADCINT3	ADCINT2	ADCINT1
R-0h				R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

Table 15-23 ADCINTFLGFRC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19	ADCDMAINT4	R-0/W1S	0h	ADC DMA interrupt 4 Flag Force. Reads return 0. 0 No action 1 Forces ADCDMAINT4 flags in the ADCINTFLG and ADCRAWINTFLG registers. Reset type: SYSRSn
18	ADCDMAINT3	R-0/W1S	0h	ADC DMA interrupt 3 Flag Force. Reads return 0. 0 No action 1 Forces ADCDMAINT3 flags in the ADCINTFLG and ADCRAWINTFLG registers. Reset type: SYSRSn
17	ADCDMAINT2	R-0/W1S	0h	ADC DMA interrupt 2 Flag Force. Reads return 0. 0 No action 1 Forces ADCDMAINT2 flags in the ADCINTFLG and ADCRAWINTFLG registers. Reset type: SYSRSn
16	ADCDMAINT1	R-0/W1S	0h	ADC DMA interrupt 1 Flag Force. Reads return 0. 0 No action 1 Forces ADCDMAINT1 flags in the ADCINTFLG and ADCRAWINTFLG registers. Reset type: SYSRSn
15-4	RESERVED	R	0h	Reserved
3	ADCINT4	R-0/W1S	0h	ADC Interrupt 4 Flag Force. Reads return 0. 0 No action 1 Forces ADCINT4 flags in the ADCINTFLG and ADCRAWINTFLG registers. Reset type: SYSRSn
2	ADCINT3	R-0/W1S	0h	ADC Interrupt 3 Flag Force. Reads return 0. 0 No action 1 Forces ADCINT3 flags in the ADCINTFLG and ADCRAWINTFLG registers. Reset type: SYSRSn
1	ADCINT2	R-0/W1S	0h	ADC Interrupt 2 Flag Force. Reads return 0. 0 No action 1 Forces ADCINT2 flags in the ADCINTFLG and ADCRAWINTFLG registers. Reset type: SYSRSn
0	ADCINT1	R-0/W1S	0h	ADC Interrupt 1 Flag Force. Reads return 0. 0 No action 1 Forces ADCINT1 flags in the ADCINTFLG and ADCRAWINTFLG registers. Reset type: SYSRSn

15.12.2.8 ADCINTFLGCLR Register (Offset = 24h) [Reset = 00000000h]

ADCINTFLGCLR is shown in Figure 15-28 and described in Table 15-24.

Return to the Summary Table.

ADC Interrupt Flag Clear Register

Figure 15-28 ADCINTFLGCLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				ADCDMAINT4	ADCDMAINT3	ADCDMAINT2	ADCDMAINT1
R-0h				R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCINT4	ADCINT3	ADCINT2	ADCINT1
R-0h				R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

Table 15-24 ADCINTFLGCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19	ADCDMAINT4	R-0/W1C	0h	ADC DMA Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADDMACINT4 flags in the ADCINTFLG ,ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
18	ADCDMAINT3	R-0/W1C	0h	ADC DMA Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADDMACINT3 flags in the ADCINTFLG ,ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
17	ADCDMAINT2	R-0/W1C	0h	ADC DMA Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADDMACINT2 flags in the ADCINTFLG ,ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
16	ADCDMAINT1	R-0/W1C	0h	ADC DMA Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADDMACINT1 flags in the ADCINTFLG ,ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
15-4	RESERVED	R	0h	Reserved
3	ADCINT4	R-0/W1C	0h	ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG,, ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
2	ADCINT3	R-0/W1C	0h	ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG, ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
1	ADCINT2	R-0/W1C	0h	ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG, ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
0	ADCINT1	R-0/W1C	0h	ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG, ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn

15.12.2.9 ADCINTOVF Register (Offset = 28h) [Reset = 00000000h]

ADCINTOVF is shown in Figure 15-29 and described in Table 15-25.

Return to the Summary Table.

ADC Interrupt Overflow Register

Figure 15-29 ADCINTOVF Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				ADCDMAINT4OVF	ADCDMAINT3OVF	ADCDMAINT2OVF	ADCDMAINT1OVF
R-0h				R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCINT4OVF	ADCINT3OVF	ADCINT2OVF	ADCINT1OVF
R-0h				R-0h	R-0h	R-0h	R-0h

Table 15-25 ADCINTOVF Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19	ADCDMAINT4OVF	R	0h	ADC DMA Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC DMA Interrupt overflow event detected. 1 ADC DMA Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
18	ADCDMAINT3OVF	R	0h	ADC DMA Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC DMA Interrupt overflow event detected. 1 ADC DMA Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
17	ADCDMAINT2OVF	R	0h	ADC DMA Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC DMA Interrupt overflow event detected. 1 ADC DMA Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
16	ADCDMAINT1OVF	R	0h	ADC DMA Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC DMA Interrupt overflow event detected. 1 ADC DMA Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
15-4	RESERVED	R	0h	Reserved
3	ADCINT4OVF	R	0h	ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
2	ADCINT3OVF	R	0h	ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
1	ADCINT2OVF	R	0h	ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
0	ADCINT1OVF	R	0h	ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn

15.12.2.10 ADCINTOVFCLR Register (Offset = 2Ch) [Reset = 00000000h]

ADCINTOVFCLR is shown in Figure 15-30 and described in Table 15-26.

Return to the Summary Table.

ADC Interrupt Overflow Clear Register

Figure 15-30 ADCINTOVFCLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				ADCDMAINT4OVF	ADCDMAINT3OVF	ADCDMAINT2OVF	ADCDMAINT1OVF
R-0h				R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCINT4OVF	ADCINT3OVF	ADCINT2OVF	ADCINT1OVF
R-0h				R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

Table 15-26 ADCINTOVFCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19	ADCDMAINT4OVF	R-0/W1C	0h	ADC DMA Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
18	ADCDMAINT3OVF	R-0/W1C	0h	ADC DMA Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
17	ADCDMAINT2OVF	R-0/W1C	0h	ADC DMA Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
16	ADCDMAINT1OVF	R-0/W1C	0h	ADC DMA Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
15-4	RESERVED	R	0h	Reserved
3	ADCINT4OVF	R-0/W1C	0h	ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
2	ADCINT3OVF	R-0/W1C	0h	ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
1	ADCINT2OVF	R-0/W1C	0h	ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
0	ADCINT1OVF	R-0/W1C	0h	ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn

15.12.2.11 ADCSOCFLG1 Register (Offset = 3Ch) [Reset = 00000000h]

ADCSOCFLG1 is shown in Figure 15-31 and described in Table 15-27.

Return to the Summary Table.

ADC SOC Flag 1 Register

Figure 15-31 ADCSOCFLG1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
SOC15	SOC14	SOC13	SOC12	SOC11	SOC10	SOC9	SOC8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
SOC7	SOC6	SOC5	SOC4	SOC3	SOC2	SOC1	SOC0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 15-27 ADCSOCFLG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	SOC15	R	0h	SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
14	SOC14	R	0h	SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
13	SOC13	R	0h	SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
12	SOC12	R	0h	SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
11	SOC11	R	0h	SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
10	SOC10	R	0h	SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
9	SOC9	R	0h	SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
8	SOC8	R	0h	SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
7	SOC7	R	0h	SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
6	SOC6	R	0h	SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
5	SOC5	R	0h	SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
4	SOC4	R	0h	SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
3	SOC3	R	0h	SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
2	SOC2	R	0h	SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
1	SOC1	R	0h	SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
0	SOC0	R	0h	SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn

15.12.2.12 ADCSOCOVF1 Register (Offset = 44h) [Reset = 00000000h]

ADCSOCOVF1 is shown in Figure 15-32 and described in Table 15-28.

Return to the Summary Table.

ADC SOC Overflow 1 Register

Figure 15-32 ADCSOCOVF1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
SOC15OVF	SOC14OVF	SOC13OVF	SOC12OVF	SOC11OVF	SOC10OVF	SOC9OVF	SOC8OVF
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
SOC7OVF	SOC6OVF	SOC5OVF	SOC4OVF	SOC3OVF	SOC2OVF	SOC1OVF	SOC0OVF
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 15-28 ADCSOCOVF1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	SOC15OVF	R	0h	SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
14	SOC14OVF	R	0h	SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
13	SOC13OVF	R	0h	SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
12	SOC12OVF	R	0h	SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
11	SOC11OVF	R	0h	SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
10	SOC10OVF	R	0h	SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
9	SOC9OVF	R	0h	SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
8	SOC8OVF	R	0h	SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
7	SOC7OVF	R	0h	SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
6	SOC6OVF	R	0h	SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
5	SOC5OVF	R	0h	SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
4	SOC4OVF	R	0h	SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
3	SOC3OVF	R	0h	SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
2	SOC2OVF	R	0h	SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
1	SOC1OVF	R	0h	SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn
0	SOC0OVF	R	0h	SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from being processed. It simply is an indication that a hardware trigger was missed. Reset type: SYSRSn

15.12.2.13 ADCSOCOVFCLR1 Register (Offset = 48h) [Reset = 00000000h]

ADCSOCOVFCLR1 is shown in Figure 15-33 and described in Table 15-29.

Return to the Summary Table.

ADC SOC Overflow Clear 1 Register

Figure 15-33 ADCSOCOVFCLR1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
SOC15OVF	SOC14OVF	SOC13OVF	SOC12OVF	SOC11OVF	SOC10OVF	SOC9OVF	SOC8OVF
R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

7	6	5	4	3	2	1	0
SOC7OVF	SOC6OVF	SOC5OVF	SOC4OVF	SOC3OVF	SOC2OVF	SOC1OVF	SOC0OVF
R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

Table 15-29 ADCSOCOVFCLR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	SOC15OVF	R-0/W1C	0h	SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
14	SOC14OVF	R-0/W1C	0h	SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
13	SOC13OVF	R-0/W1C	0h	SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
12	SOC12OVF	R-0/W1C	0h	SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
11	SOC11OVF	R-0/W1C	0h	SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
10	SOC10OVF	R-0/W1C	0h	SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
9	SOC9OVF	R-0/W1C	0h	SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
8	SOC8OVF	R-0/W1C	0h	SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
7	SOC7OVF	R-0/W1C	0h	SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
6	SOC6OVF	R-0/W1C	0h	SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
5	SOC5OVF	R-0/W1C	0h	SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
4	SOC4OVF	R-0/W1C	0h	SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
3	SOC3OVF	R-0/W1C	0h	SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
2	SOC2OVF	R-0/W1C	0h	SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
1	SOC1OVF	R-0/W1C	0h	SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
0	SOC0OVF	R-0/W1C	0h	SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn

15.12.2.14 ADCSOC0CTL Register (Offset = 4Ch) [Reset = 00000000h]

ADCSOC0CTL is shown in Figure 15-34 and described in Table 15-30.

Return to the Summary Table.

ADC SOC0 Control Register

Figure 15-34 ADCSOC0CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-30 ADCSOC0CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC0 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.15 ADCSOC1CTL Register (Offset = 50h) [Reset = 00000000h]

ADCSOC1CTL is shown in Figure 15-35 and described in Table 15-31.

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ADC SOC1 Control Register

Figure 15-35 ADCSOC1CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-31 ADCSOC1CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC1 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.16 ADCSOC2CTL Register (Offset = 54h) [Reset = 00000000h]

ADCSOC2CTL is shown in Figure 15-36 and described in Table 15-32.

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ADC SOC2 Control Register

Figure 15-36 ADCSOC2CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-32 ADCSOC2CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC2 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.17 ADCSOC3CTL Register (Offset = 58h) [Reset = 00000000h]

ADCSOC3CTL is shown in Figure 15-37 and described in Table 15-33.

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ADC SOC3 Control Register

Figure 15-37 ADCSOC3CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-33 ADCSOC3CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC3 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.18 ADCSOC4CTL Register (Offset = 5Ch) [Reset = 00000000h]

ADCSOC4CTL is shown in Figure 15-38 and described in Table 15-34.

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ADC SOC4 Control Register

Figure 15-38 ADCSOC4CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-34 ADCSOC4CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC4 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.19 ADCSOC5CTL Register (Offset = 60h) [Reset = 00000000h]

ADCSOC5CTL is shown in Figure 15-39 and described in Table 15-35.

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ADC SOC5 Control Register

Figure 15-39 ADCSOC5CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-35 ADCSOC5CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC5 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.20 ADCSOC6CTL Register (Offset = 64h) [Reset = 00000000h]

ADCSOC6CTL is shown in Figure 15-40 and described in Table 15-36.

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ADC SOC6 Control Register

Figure 15-40 ADCSOC6CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-36 ADCSOC6CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC6 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.21 ADCSOC7CTL Register (Offset = 68h) [Reset = 00000000h]

ADCSOC7CTL is shown in Figure 15-41 and described in Table 15-37.

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ADC SOC7 Control Register

Figure 15-41 ADCSOC7CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-37 ADCSOC7CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC7 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.22 ADCSOC8CTL Register (Offset = 6Ch) [Reset = 00000000h]

ADCSOC8CTL is shown in Figure 15-42 and described in Table 15-38.

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ADC SOC8 Control Register

Figure 15-42 ADCSOC8CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-38 ADCSOC8CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC8 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.23 ADCSOC9CTL Register (Offset = 70h) [Reset = 00000000h]

ADCSOC9CTL is shown in Figure 15-43 and described in Table 15-39.

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ADC SOC9 Control Register

Figure 15-43 ADCSOC9CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-39 ADCSOC9CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC9 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.24 ADCSOC10CTL Register (Offset = 74h) [Reset = 00000000h]

ADCSOC10CTL is shown in Figure 15-44 and described in Table 15-40.

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ADC SOC10 Control Register

Figure 15-44 ADCSOC10CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-40 ADCSOC10CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC10 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.25 ADCSOC11CTL Register (Offset = 78h) [Reset = 00000000h]

ADCSOC11CTL is shown in Figure 15-45 and described in Table 15-41.

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ADC SOC11 Control Register

Figure 15-45 ADCSOC11CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-41 ADCSOC11CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC11 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.26 ADCSOC12CTL Register (Offset = 7Ch) [Reset = 00000000h]

ADCSOC12CTL is shown in Figure 15-46 and described in Table 15-42.

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ADC SOC12 Control Register

Figure 15-46 ADCSOC12CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-42 ADCSOC12CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC12 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.27 ADCSOC13CTL Register (Offset = 80h) [Reset = 00000000h]

ADCSOC13CTL is shown in Figure 15-47 and described in Table 15-43.

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ADC SOC13 Control Register

Figure 15-47 ADCSOC13CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-43 ADCSOC13CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC13 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.28 ADCSOC14CTL Register (Offset = 84h) [Reset = 00000000h]

ADCSOC14CTL is shown in Figure 15-48 and described in Table 15-44.

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ADC SOC14 Control Register

Figure 15-48 ADCSOC14CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-44 ADCSOC14CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC14 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.29 ADCSOC15CTL Register (Offset = 88h) [Reset = 00000000h]

ADCSOC15CTL is shown in Figure 15-49 and described in Table 15-45.

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ADC SOC15 Control Register

Figure 15-49 ADCSOC15CTL Register

31	30	29	28	27	26	25	24
RESERVED						COMPEN	RESERVED
R-0h						R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				CHSEL
R-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-45 ADCSOC15CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	COMPEN	R/W	0h	SOC15 Threshold comparator enable. Reset type: SYSRSn
24-20	RESERVED	R	0h	Reserved
19-15	CHSEL	R/W	0h	SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Reset type: SYSRSn
14-0	RESERVED	R	0h	Reserved

15.12.2.30 ADCEVTSTAT Register (Offset = CCh) [Reset = 00000000h]

ADCEVTSTAT is shown in Figure 15-50 and described in Table 15-46.

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ADC Event Status Register

Figure 15-50 ADCEVTSTAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
PPB4INLIMIT	PPB4ZERO	PPB4TRIPLO	PPB4TRIPHI	PPB3INLIMIT	PPB3ZERO	PPB3TRIPLO	PPB3TRIPHI
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
PPB2INLIMIT	PPB2ZERO	PPB2TRIPLO	PPB2TRIPHI	PPB1INLIMIT	PPB1ZERO	PPB1TRIPLO	PPB1TRIPHI
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 15-46 ADCEVTSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	PPB4INLIMIT	R	0h	Post Processing Block 4 Within trip limit Flag. When set indicates a digital compare within limit event has occurred. This will be set when the PPB result is either in between or equal to the TRIPHI and TRIPLO thresholds. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
14	PPB4ZERO	R	0h	Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
13	PPB4TRIPLO	R	0h	Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
12	PPB4TRIPHI	R	0h	Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
11	PPB3INLIMIT	R	0h	Post Processing Block 3 Within trip limit Flag. When set indicates a digital compare within limit event has occurred. This will be set when the PPB result is either in between or equal to the TRIPHI and TRIPLO thresholds. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
10	PPB3ZERO	R	0h	Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
9	PPB3TRIPLO	R	0h	Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
8	PPB3TRIPHI	R	0h	Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
7	PPB2INLIMIT	R	0h	Post Processing Block 2 Within trip limit Flag. When set indicates a digital compare within limit event has occurred. This will be set when the PPB result is either in between or equal to the TRIPHI and TRIPLO thresholds. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
6	PPB2ZERO	R	0h	Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
5	PPB2TRIPLO	R	0h	Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
4	PPB2TRIPHI	R	0h	Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
3	PPB1INLIMIT	R	0h	Post Processing Block 1 Within trip limit Flag. When set indicates a digital compare within limit event has occurred. This will be set when the PPB result is either in between or equal to the TRIPHI and TRIPLO thresholds. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
2	PPB1ZERO	R	0h	Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
1	PPB1TRIPLO	R	0h	Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
0	PPB1TRIPHI	R	0h	Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn

15.12.2.31 ADCEVTCLR Register (Offset = D0h) [Reset = 00000000h]

ADCEVTCLR is shown in Figure 15-51 and described in Table 15-47.

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ADC Event Clear Register

Figure 15-51 ADCEVTCLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
PPB4INLIMIT	PPB4ZERO	PPB4TRIPLO	PPB4TRIPHI	PPB3INLIMIT	PPB3ZERO	PPB3TRIPLO	PPB3TRIPHI
R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

7	6	5	4	3	2	1	0
PPB2INLIMIT	PPB2ZERO	PPB2TRIPLO	PPB2TRIPHI	PPB1INLIMIT	PPB1ZERO	PPB1TRIPLO	PPB1TRIPHI
R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

Table 15-47 ADCEVTCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	PPB4INLIMIT	R-0/W1C	0h	Post Processing Block 4 Within trip limit flag Clear, Clears the corresponding within trip limit flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
14	PPB4ZERO	R-0/W1C	0h	Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
13	PPB4TRIPLO	R-0/W1C	0h	Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
12	PPB4TRIPHI	R-0/W1C	0h	Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
11	PPB3INLIMIT	R-0/W1C	0h	Post Processing Block 3 Within trip limit flag Clear, Clears the corresponding within trip limit flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
10	PPB3ZERO	R-0/W1C	0h	Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
9	PPB3TRIPLO	R-0/W1C	0h	Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
8	PPB3TRIPHI	R-0/W1C	0h	Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
7	PPB2INLIMIT	R-0/W1C	0h	Post Processing Block 2 Within trip limit flag Clear, Clears the corresponding within trip limit flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
6	PPB2ZERO	R-0/W1C	0h	Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
5	PPB2TRIPLO	R-0/W1C	0h	Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
4	PPB2TRIPHI	R-0/W1C	0h	Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
3	PPB1INLIMIT	R-0/W1C	0h	Post Processing Block 1 Within trip limit flag Clear, Clears the corresponding within trip limit flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
2	PPB1ZERO	R-0/W1C	0h	Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
1	PPB1TRIPLO	R-0/W1C	0h	Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
0	PPB1TRIPHI	R-0/W1C	0h	Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn

15.12.2.32 ADCEVTSEL Register (Offset = D4h) [Reset = 00000000h]

ADCEVTSEL is shown in Figure 15-52 and described in Table 15-48.

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ADC Event Selection Register

Figure 15-52 ADCEVTSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
PPB4INLIMIT	PPB4ZERO	PPB4TRIPLO	PPB4TRIPHI	PPB3INLIMIT	PPB3ZERO	PPB3TRIPLO	PPB3TRIPHI
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
PPB2INLIMIT	PPB2ZERO	PPB2TRIPLO	PPB2TRIPHI	PPB1INLIMIT	PPB1ZERO	PPB1TRIPLO	PPB1TRIPHI
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 15-48 ADCEVTSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	PPB4INLIMIT	R/W	0h	Post Processing Block 4 Within trip limit event enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
14	PPB4ZERO	R/W	0h	Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
13	PPB4TRIPLO	R/W	0h	Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
12	PPB4TRIPHI	R/W	0h	Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
11	PPB3INLIMIT	R/W	0h	Post Processing Block 3 Within trip limit event enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
10	PPB3ZERO	R/W	0h	Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
9	PPB3TRIPLO	R/W	0h	Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
8	PPB3TRIPHI	R/W	0h	Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
7	PPB2INLIMIT	R/W	0h	Post Processing Block 2 Within trip limit event enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
6	PPB2ZERO	R/W	0h	Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
5	PPB2TRIPLO	R/W	0h	Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
4	PPB2TRIPHI	R/W	0h	Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
3	PPB1INLIMIT	R/W	0h	Post Processing Block 1 Within trip limit event enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
2	PPB1ZERO	R/W	0h	Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
1	PPB1TRIPLO	R/W	0h	Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
0	PPB1TRIPHI	R/W	0h	Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn

15.12.2.33 ADCEVTINTSEL Register (Offset = D8h) [Reset = 00000000h]

ADCEVTINTSEL is shown in Figure 15-53 and described in Table 15-49.

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ADC Event Interrupt Selection Register

Figure 15-53 ADCEVTINTSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
PPB4INLIMIT	PPB4ZERO	PPB4TRIPLO	PPB4TRIPHI	PPB3INLIMIT	PPB3ZERO	PPB3TRIPLO	PPB3TRIPHI
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
PPB2INLIMIT	PPB2ZERO	PPB2TRIPLO	PPB2TRIPHI	PPB1INLIMIT	PPB1ZERO	PPB1TRIPLO	PPB1TRIPHI
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 15-49 ADCEVTINTSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	PPB4INLIMIT	R/W	0h	Post Processing Block 4 Within trip limit Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
14	PPB4ZERO	R/W	0h	Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
13	PPB4TRIPLO	R/W	0h	Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
12	PPB4TRIPHI	R/W	0h	Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
11	PPB3INLIMIT	R/W	0h	Post Processing Block 3 Within trip limit Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
10	PPB3ZERO	R/W	0h	Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
9	PPB3TRIPLO	R/W	0h	Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
8	PPB3TRIPHI	R/W	0h	Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
7	PPB2INLIMIT	R/W	0h	Post Processing Block 2 Within trip limit Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
6	PPB2ZERO	R/W	0h	Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
5	PPB2TRIPLO	R/W	0h	Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
4	PPB2TRIPHI	R/W	0h	Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
3	PPB1INLIMIT	R/W	0h	Post Processing Block 1 Within trip limit Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
2	PPB1ZERO	R/W	0h	Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
1	PPB1TRIPLO	R/W	0h	Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn
0	PPB1TRIPHI	R/W	0h	Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the NVIC . The flag must be cleared before it can produce additional interrupts to the NVIC . Reset type: SYSRSn

15.12.2.34 ADCREV Register (Offset = E4h) [Reset = 00000006h]

ADCREV is shown in Figure 15-54 and described in Table 15-50.

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ADC Revision Register

Figure 15-54 ADCREV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV																								TYPE
R-0h																								R-6h

Table 15-50 ADCREV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	REV	R	0h	ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h. Reset type: SYSRSn
7-0	TYPE	R	6h	ADC Type. Always set to 6 for this HSADC-12b. Reset type: SYSRSn

15.12.2.35 ADCOFFTRIM Register (Offset = E8h) [Reset = 00000000h]

ADCOFFTRIM is shown in Figure 15-55 and described in Table 15-51.

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ADC Offset Trim Register 1

Figure 15-55 ADCOFFTRIM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								OFFTRIM
R-0h																								R/W-0h

Table 15-51 ADCOFFTRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	OFFTRIM	R/W	0h	ADC Offset Trim Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A factory trim setting will be loaded during device boot. Offset can be corrected in the range of +7 to -8 LSBs. Value is 16Offset in 8-bit 2's complement: 7 LSB (167) = 112 6 LSB (166) = 96 5 LSB (165) = 80 4 LSB (164) = 64 3 LSB (163) = 48 2 LSB (162) = 32 1 LSB (161) = 16 0 LSB (160) = 0 -1 LSB (16(-1)) = 240 : : -7LSB(16*(-7)) = 144 Reset type: XRSn

15.12.2.36 ADCPPB1CONFIG Register (Offset = 100h) [Reset = 00000000h]

ADCPPB1CONFIG is shown in Figure 15-56 and described in Table 15-52.

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ADC PPB1 Config Register

Figure 15-56 ADCPPB1CONFIG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	CBCEN	RESERVED
R/W-0h	R-0h	R/W-0h	R-0h

Table 15-52 ADCPPB1CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R	0h	Reserved
5	CBCEN	R/W	0h	ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn
4-0	RESERVED	R	0h	Reserved

15.12.2.37 ADCPPB1TRIPHI Register (Offset = 110h) [Reset = 00000000h]

ADCPPB1TRIPHI is shown in Figure 15-57 and described in Table 15-53.

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ADC PPB1 Trip High Register

Figure 15-57 ADCPPB1TRIPHI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																LIMITHI
R-0h																R/W-0h

Table 15-53 ADCPPB1TRIPHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	LIMITHI	R/W	0h	ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[15:13] will be ignored Reset type: SYSRSn

15.12.2.38 ADCPPB1TRIPLO Register (Offset = 114h) [Reset = 00000000h]

ADCPPB1TRIPLO is shown in Figure 15-58 and described in Table 15-54.

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ADC PPB1 Trip Low/Trigger Time Stamp Register

Figure 15-58 ADCPPB1TRIPLO Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																LIMITLO
R-0h																R/W-0h

Table 15-54 ADCPPB1TRIPLO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	LIMITLO	R/W	0h	ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO[15:13] will be ignored in 12 bit mode Reset type: SYSRSn

15.12.2.39 ADCPPB2CONFIG Register (Offset = 120h) [Reset = 00000000h]

ADCPPB2CONFIG is shown in Figure 15-59 and described in Table 15-55.

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ADC PPB2 Config Register

Figure 15-59 ADCPPB2CONFIG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	CBCEN	RESERVED
R/W-0h	R-0h	R/W-0h	R-0h

Table 15-55 ADCPPB2CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R	0h	Reserved
5	CBCEN	R/W	0h	ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn
4-0	RESERVED	R	0h	Reserved

15.12.2.40 ADCPPB2TRIPHI Register (Offset = 130h) [Reset = 00000000h]

ADCPPB2TRIPHI is shown in Figure 15-60 and described in Table 15-56.

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ADC PPB2 Trip High Register

Figure 15-60 ADCPPB2TRIPHI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																LIMITHI
R-0h																R/W-0h

Table 15-56 ADCPPB2TRIPHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	LIMITHI	R/W	0h	ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[15:13] will be ignored Reset type: SYSRSn

15.12.2.41 ADCPPB2TRIPLO Register (Offset = 134h) [Reset = 00000000h]

ADCPPB2TRIPLO is shown in Figure 15-61 and described in Table 15-57.

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ADC PPB2 Trip Low/Trigger Time Stamp Register

Figure 15-61 ADCPPB2TRIPLO Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																LIMITLO
R-0h																R/W-0h

Table 15-57 ADCPPB2TRIPLO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	LIMITLO	R/W	0h	ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO[15:13] will be ignored in 12 bit mode Reset type: SYSRSn

15.12.2.42 ADCPPB3CONFIG Register (Offset = 140h) [Reset = 00000000h]

ADCPPB3CONFIG is shown in Figure 15-62 and described in Table 15-58.

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ADC PPB3 Config Register

Figure 15-62 ADCPPB3CONFIG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	CBCEN	RESERVED
R/W-0h	R-0h	R/W-0h	R-0h

Table 15-58 ADCPPB3CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R	0h	Reserved
5	CBCEN	R/W	0h	ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn
4-0	RESERVED	R	0h	Reserved

15.12.2.43 ADCPPB3TRIPHI Register (Offset = 150h) [Reset = 00000000h]

ADCPPB3TRIPHI is shown in Figure 15-63 and described in Table 15-59.

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ADC PPB3 Trip High Register

Figure 15-63 ADCPPB3TRIPHI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																LIMITHI
R-0h																R/W-0h

Table 15-59 ADCPPB3TRIPHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	LIMITHI	R/W	0h	ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[15:13] will be ignored Reset type: SYSRSn

15.12.2.44 ADCPPB3TRIPLO Register (Offset = 154h) [Reset = 00000000h]

ADCPPB3TRIPLO is shown in Figure 15-64 and described in Table 15-60.

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ADC PPB3 Trip Low/Trigger Time Stamp Register

Figure 15-64 ADCPPB3TRIPLO Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																LIMITLO
R-0h																R/W-0h

Table 15-60 ADCPPB3TRIPLO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	LIMITLO	R/W	0h	ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO[15:13] will be ignored in 12 bit mode Reset type: SYSRSn

15.12.2.45 ADCPPB4CONFIG Register (Offset = 160h) [Reset = 00000000h]

ADCPPB4CONFIG is shown in Figure 15-65 and described in Table 15-61.

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ADC PPB4 Config Register

Figure 15-65 ADCPPB4CONFIG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	CBCEN	RESERVED
R/W-0h	R-0h	R/W-0h	R-0h

Table 15-61 ADCPPB4CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R	0h	Reserved
5	CBCEN	R/W	0h	ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn
4-0	RESERVED	R	0h	Reserved

15.12.2.46 ADCPPB4TRIPHI Register (Offset = 170h) [Reset = 00000000h]

ADCPPB4TRIPHI is shown in Figure 15-66 and described in Table 15-62.

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ADC PPB4 Trip High Register

Figure 15-66 ADCPPB4TRIPHI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																LIMITHI
R-0h																R/W-0h

Table 15-62 ADCPPB4TRIPHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	LIMITHI	R/W	0h	ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[15:13] will be ignored Reset type: SYSRSn

15.12.2.47 ADCPPB4TRIPLO Register (Offset = 174h) [Reset = 00000000h]

ADCPPB4TRIPLO is shown in Figure 15-67 and described in Table 15-63.

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ADC PPB4 Trip Low/Trigger Time Stamp Register

Figure 15-67 ADCPPB4TRIPLO Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																LIMITLO
R-0h																R/W-0h

Table 15-63 ADCPPB4TRIPLO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	LIMITLO	R/W	0h	ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO[15:13] will be ignored in 12 bit mode Reset type: SYSRSn

15.12.2.48 ADCINTCYCLE Register (Offset = 180h) [Reset = 00000000h]

ADCINTCYCLE is shown in Figure 15-68 and described in Table 15-64.

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ADC Early Interrupt Generation Cycle

Figure 15-68 ADCINTCYCLE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										DELAY
R-0h																										R/W-0h

Table 15-64 ADCINTCYCLE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-0	DELAY	R/W	0h	ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles, for the interrupt to be generated. Reset type: SYSRSn

15.12.2.49 ADCREV2 Register (Offset = 19Ch) [Reset = 00000006h]

ADCREV2 is shown in Figure 15-69 and described in Table 15-65.

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ADC Wrapper Revision Register

Figure 15-69 ADCREV2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRAPPERREV
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRAPPERREV								WRAPPERTYPE
R-0h								R-6h

Table 15-65 ADCREV2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	WRAPPERREV	R	0h	ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h. Reset type: SYSRSn
7-0	WRAPPERTYPE	R	6h	ADC Wrapper Type. Always set to 6 for this ADC. Reset type: SYSRSn

15.12.2.50 ADCPPB1LIMIT Register (Offset = 200h) [Reset = 00000000h]

ADCPPB1LIMIT is shown in Figure 15-70 and described in Table 15-66.

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ADC PPB1Conversion Count Limit Register

Figure 15-70 ADCPPB1LIMIT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														LIMIT
R-0h														R/W-0h

Table 15-66 ADCPPB1LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	LIMIT	R/W	0h	Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. 0 = No - accumulation 1 = 2 conversions are accumulated 2 = 4 conversions are accumulated 3 = 8 conversions are accumulated Reset type: SYSRSn

15.12.2.51 ADCPPB1PCOUNT Register (Offset = 204h) [Reset = 00000000h]

ADCPPB1PCOUNT is shown in Figure 15-71 and described in Table 15-67.

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ADC PPB1 Partial Conversion Count Register

Figure 15-71 ADCPPB1PCOUNT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													PCOUNT
R-0h													R-0h

Table 15-67 ADCPPB1PCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	PCOUNT	R	0h	Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 MCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 MCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn

15.12.2.52 ADCPPB1CONFIG2 Register (Offset = 208h) [Reset = 00000000h]

ADCPPB1CONFIG2 is shown in Figure 15-72 and described in Table 15-68.

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ADC PPB1 Sum Shift Register

Figure 15-72 ADCPPB1CONFIG2 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
COMPSEL	RESERVED		RESERVED	SWSYNC	RESERVED		SYNCINSEL
R/W-0h	R-0h		R/W-0h	R-0/W1S-0h	R-0h		R/W-0h

7	6	5	4	3	2	1	0
SYNCINSEL				RESERVED	SHIFT
R/W-0h				R-0h	R/W-0h

Table 15-68 ADCPPB1CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	COMPSEL	R/W	0h	Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT or ADCPPB1SUM is used for the threshold compare. 0 = ADCPPB1RESULT is used for compare logic 1 = ADCPPB1SUM is used for compare logic Reset type: SYSRSn
14-13	RESERVED	R	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	SWSYNC	R-0/W1S	0h	PPB 1 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn
10-9	RESERVED	R	0h	Reserved
8-4	SYNCINSEL	R/W	0h	PPB 1 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details Reset type: SYSRSn
3	RESERVED	R	0h	Reserved
2-0	SHIFT	R/W	0h	Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 7 : SUM = PSUM >> 7 Reset type: SYSRSn

15.12.2.53 ADCPPB1PSUM Register (Offset = 20Ch) [Reset = 00000000h]

ADCPPB1PSUM is shown in Figure 15-73 and described in Table 15-69.

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ADC PPB1 Partial Sum Register

Figure 15-73 ADCPPB1PSUM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN																PSUM
R-0h																R-0h

Table 15-69 ADCPPB1PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 15. Reset type: SYSRSn
15-0	PSUM	R	0h	Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 MCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 MCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 MCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 MCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn

15.12.2.54 ADCPPB2LIMIT Register (Offset = 240h) [Reset = 00000000h]

ADCPPB2LIMIT is shown in Figure 15-74 and described in Table 15-70.

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ADC PPB2Conversion Count Limit Register

Figure 15-74 ADCPPB2LIMIT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														LIMIT
R-0h														R/W-0h

Table 15-70 ADCPPB2LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	LIMIT	R/W	0h	Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. 0 = No - accumulation 1 = 2 conversions are accumulated 2 = 4 conversions are accumulated 3 = 8 conversions are accumulated Reset type: SYSRSn

15.12.2.55 ADCPPB2PCOUNT Register (Offset = 244h) [Reset = 00000000h]

ADCPPB2PCOUNT is shown in Figure 15-75 and described in Table 15-71.

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ADC PPB2 Partial Conversion Count Register

Figure 15-75 ADCPPB2PCOUNT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													PCOUNT
R-0h													R-0h

Table 15-71 ADCPPB2PCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	PCOUNT	R	0h	Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 MCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 MCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn

15.12.2.56 ADCPPB2CONFIG2 Register (Offset = 248h) [Reset = 00000000h]

ADCPPB2CONFIG2 is shown in Figure 15-76 and described in Table 15-72.

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ADC PPB2 Sum Shift Register

Figure 15-76 ADCPPB2CONFIG2 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
COMPSEL	RESERVED		RESERVED	SWSYNC	RESERVED		SYNCINSEL
R/W-0h	R-0h		R/W-0h	R-0/W1S-0h	R-0h		R/W-0h

7	6	5	4	3	2	1	0
SYNCINSEL				RESERVED	SHIFT
R/W-0h				R-0h	R/W-0h

Table 15-72 ADCPPB2CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	COMPSEL	R/W	0h	Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT or ADCPPB2SUM is used for the threshold compare. 0 = ADCPPB2RESULT is used for compare logic 1 = ADCPPB2SUM is used for compare logic Reset type: SYSRSn
14-13	RESERVED	R	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	SWSYNC	R-0/W1S	0h	PPB 2 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn
10-9	RESERVED	R	0h	Reserved
8-4	SYNCINSEL	R/W	0h	PPB 2 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details Reset type: SYSRSn
3	RESERVED	R	0h	Reserved
2-0	SHIFT	R/W	0h	Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 7 : SUM = PSUM >> 7 Reset type: SYSRSn

15.12.2.57 ADCPPB2PSUM Register (Offset = 24Ch) [Reset = 00000000h]

ADCPPB2PSUM is shown in Figure 15-77 and described in Table 15-73.

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ADC PPB2 Partial Sum Register

Figure 15-77 ADCPPB2PSUM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN																PSUM
R-0h																R-0h

Table 15-73 ADCPPB2PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 15. Reset type: SYSRSn
15-0	PSUM	R	0h	Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 MCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 MCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 MCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 MCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn

15.12.2.58 ADCPPB3LIMIT Register (Offset = 280h) [Reset = 00000000h]

ADCPPB3LIMIT is shown in Figure 15-78 and described in Table 15-74.

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ADC PPB3Conversion Count Limit Register

Figure 15-78 ADCPPB3LIMIT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														LIMIT
R-0h														R/W-0h

Table 15-74 ADCPPB3LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	LIMIT	R/W	0h	Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. 0 = No - accumulation 1 = 2 conversions are accumulated 2 = 4 conversions are accumulated 3 = 8 conversions are accumulated Reset type: SYSRSn

15.12.2.59 ADCPPB3PCOUNT Register (Offset = 284h) [Reset = 00000000h]

ADCPPB3PCOUNT is shown in Figure 15-79 and described in Table 15-75.

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ADC PPB3 Partial Conversion Count Register

Figure 15-79 ADCPPB3PCOUNT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													PCOUNT
R-0h													R-0h

Table 15-75 ADCPPB3PCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	PCOUNT	R	0h	Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 MCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 MCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn

15.12.2.60 ADCPPB3CONFIG2 Register (Offset = 288h) [Reset = 00000000h]

ADCPPB3CONFIG2 is shown in Figure 15-80 and described in Table 15-76.

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ADC PPB3 Sum Shift Register

Figure 15-80 ADCPPB3CONFIG2 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
COMPSEL	RESERVED		RESERVED	SWSYNC	RESERVED		SYNCINSEL
R/W-0h	R-0h		R/W-0h	R-0/W1S-0h	R-0h		R/W-0h

7	6	5	4	3	2	1	0
SYNCINSEL				RESERVED	SHIFT
R/W-0h				R-0h	R/W-0h

Table 15-76 ADCPPB3CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	COMPSEL	R/W	0h	Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT or ADCPPB3SUM is used for the threshold compare. 0 = ADCPPB3RESULT is used for compare logic 1 = ADCPPB3SUM is used for compare logic Reset type: SYSRSn
14-13	RESERVED	R	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	SWSYNC	R-0/W1S	0h	PPB 3 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn
10-9	RESERVED	R	0h	Reserved
8-4	SYNCINSEL	R/W	0h	PPB 3 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details Reset type: SYSRSn
3	RESERVED	R	0h	Reserved
2-0	SHIFT	R/W	0h	Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 7 : SUM = PSUM >> 7 Reset type: SYSRSn

15.12.2.61 ADCPPB3PSUM Register (Offset = 28Ch) [Reset = 00000000h]

ADCPPB3PSUM is shown in Figure 15-81 and described in Table 15-77.

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ADC PPB3 Partial Sum Register

Figure 15-81 ADCPPB3PSUM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN																PSUM
R-0h																R-0h

Table 15-77 ADCPPB3PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 15. Reset type: SYSRSn
15-0	PSUM	R	0h	Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 MCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 MCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 MCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 MCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn

15.12.2.62 ADCPPB4LIMIT Register (Offset = 2C0h) [Reset = 00000000h]

ADCPPB4LIMIT is shown in Figure 15-82 and described in Table 15-78.

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ADC PPB4Conversion Count Limit Register

Figure 15-82 ADCPPB4LIMIT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														LIMIT
R-0h														R/W-0h

Table 15-78 ADCPPB4LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	LIMIT	R/W	0h	Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. 0 = No - accumulation 1 = 2 conversions are accumulated 2 = 4 conversions are accumulated 3 = 8 conversions are accumulated Reset type: SYSRSn

15.12.2.63 ADCPPB4PCOUNT Register (Offset = 2C4h) [Reset = 00000000h]

ADCPPB4PCOUNT is shown in Figure 15-83 and described in Table 15-79.

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ADC PPB4 Partial Conversion Count Register

Figure 15-83 ADCPPB4PCOUNT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													PCOUNT
R-0h													R-0h

Table 15-79 ADCPPB4PCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	PCOUNT	R	0h	Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 MCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 MCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn

15.12.2.64 ADCPPB4CONFIG2 Register (Offset = 2C8h) [Reset = 00000000h]

ADCPPB4CONFIG2 is shown in Figure 15-84 and described in Table 15-80.

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ADC PPB4 Sum Shift Register

Figure 15-84 ADCPPB4CONFIG2 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
COMPSEL	RESERVED		RESERVED	SWSYNC	RESERVED		SYNCINSEL
R/W-0h	R-0h		R/W-0h	R-0/W1S-0h	R-0h		R/W-0h

7	6	5	4	3	2	1	0
SYNCINSEL				RESERVED	SHIFT
R/W-0h				R-0h	R/W-0h

Table 15-80 ADCPPB4CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	COMPSEL	R/W	0h	Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT or ADCPPB4SUM is used for the threshold compare. 0 = ADCPPB4RESULT is used for compare logic 1 = ADCPPB4SUM is used for compare logic Reset type: SYSRSn
14-13	RESERVED	R	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	SWSYNC	R-0/W1S	0h	PPB 4 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn
10-9	RESERVED	R	0h	Reserved
8-4	SYNCINSEL	R/W	0h	PPB 4 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details Reset type: SYSRSn
3	RESERVED	R	0h	Reserved
2-0	SHIFT	R/W	0h	Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 7 : SUM = PSUM >> 7 Reset type: SYSRSn

15.12.2.65 ADCPPB4PSUM Register (Offset = 2CCh) [Reset = 00000000h]

ADCPPB4PSUM is shown in Figure 15-85 and described in Table 15-81.

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ADC PPB4 Partial Sum Register

Figure 15-85 ADCPPB4PSUM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN																PSUM
R-0h																R-0h

Table 15-81 ADCPPB4PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 15. Reset type: SYSRSn
15-0	PSUM	R	0h	Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 MCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 MCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 MCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 MCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn

15.12.2.66 ADCSEQCTL Register (Offset = 320h) [Reset = 00000000h]

ADCSEQCTL is shown in Figure 15-86 and described in Table 15-82.

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ADC Sequencer common control Register

Figure 15-86 ADCSEQCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED						SEQPREEMPT
R-0h						R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				SEQEND
R-0h				R/W-0h

Table 15-82 ADCSEQCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	0h	Reserved
17-16	SEQPREEMPT	R/W	0h	SoC Sequence PREEMPT 0X: Pre-empt disabled 10: Pre-empt enabled and will not restart aborted Sequence 11: Pre-empt enabled and will restart aborted Sequence Reset type: SYSRSn
15-4	RESERVED	R	0h	Reserved
3-0	SEQEND	R/W	0h	END SOC of last enabled sequence Reset type: SYSRSn

15.12.2.67 ADCSEQ1CONFIG_AM13E2X Register (Offset = 324h) [Reset = 00000200h]

ADCSEQ1CONFIG_AM13E2X is shown in Figure 15-87 and described in Table 15-83.

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ADC Sequencer 1 Config register

Figure 15-87 ADCSEQ1CONFIG_AM13E2X Register

31	30	29	28	27	26	25	24
SEQENABLE	SEQSWFRC	RESERVED					TRIGSEL
R/W-0h	R-0/W1S-0h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				RESERVED	SEQSTART
R/W-0h				R-0h	R/W-0h

15	14	13	12	11	10	9	8
SEQSTART	RESERVED				SAMPCAPRESETSEL	SAMPCAPRESETDISABLE	RESERVED
R/W-0h	R-0h				R/W-0h	R/W-1h	R-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 15-83 ADCSEQ1CONFIG_AM13E2X Register Field Descriptions

Bit	Field	Type	Reset	Description
31	SEQENABLE	R/W	0h	SEQ1Enable Indicates whether the Sequence1 is enabled or not Reset type: SYSRSn
30	SEQSWFRC	R-0/W1S	0h	Write 1 to force a trigger to Sequencer 1 regardless of the value of Hardware TRIGGER. Always reads 0. Reset type: SYSRSn
29-25	RESERVED	R	0h	Reserved
24-20	TRIGSEL	R/W	0h	SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 0h ADCTRIG0 - Software only 1h - 31h Hardware triggers Reset type: SYSRSn
19	RESERVED	R	0h	Reserved
18-15	SEQSTART	R/W	0h	Beginning SOC of SEQ1 Reset type: SYSRSn
14-11	RESERVED	R	0h	Reserved
10	SAMPCAPRESETSEL	R/W	0h	SOC1 Sample Cap Reset Select : Resets sample cap after conversion to either vrefhi/2 or vreflo 0 - The sample cap is reset to Vreflo after each conversion 1 - The sample cap is reset to Vrefhi/2 after each conversion Reset type: SYSRSn
9	SAMPCAPRESETDISABLE	R/W	1h	SOC1 Sample Cap Reset enable : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8	RESERVED	R	0h	Reserved
7-0	ACQPS	R/W	0h	SOC1 Acquisition Prescale. Controls the sample and hold window for each SOC in this Seqeunce. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values If ACQPS[7:6] value is "00" S+H window = ACQPS[5:0] + 1 MCLK cycles "01" S+H window = 64 + ((ACQPS[5:0] +1) * 2) MCLK cycles "10" S+H window = 192 + ((ACQPS[5:0] +1) * 4) MCLK cycles "11" S+H window = 448 + ((ACQPS[5:0] +1) * 16) MCLK cycles Reset type: SYSRSn

15.12.2.68 ADCSEQ2CONFIG_AM13E2X Register (Offset = 328h) [Reset = 00000200h]

ADCSEQ2CONFIG_AM13E2X is shown in Figure 15-88 and described in Table 15-84.

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ADC Sequencer 2 Config register

Figure 15-88 ADCSEQ2CONFIG_AM13E2X Register

31	30	29	28	27	26	25	24
SEQENABLE	SEQSWFRC	RESERVED					TRIGSEL
R/W-0h	R-0/W1S-0h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				RESERVED	SEQSTART
R/W-0h				R-0h	R/W-0h

15	14	13	12	11	10	9	8
SEQSTART	RESERVED				SAMPCAPRESETSEL	SAMPCAPRESETDISABLE	RESERVED
R/W-0h	R-0h				R/W-0h	R/W-1h	R-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 15-84 ADCSEQ2CONFIG_AM13E2X Register Field Descriptions

Bit	Field	Type	Reset	Description
31	SEQENABLE	R/W	0h	SEQ2Enable Indicates whether the Sequence2 is enabled or not Reset type: SYSRSn
30	SEQSWFRC	R-0/W1S	0h	Write 1 to force a trigger to Sequencer 2 regardless of the value of Hardware TRIGGER. Always reads 0. Reset type: SYSRSn
29-25	RESERVED	R	0h	Reserved
24-20	TRIGSEL	R/W	0h	SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 0h ADCTRIG0 - Software only 1h - 31h Hardware triggers Reset type: SYSRSn
19	RESERVED	R	0h	Reserved
18-15	SEQSTART	R/W	0h	Beginning SOC of SEQ2 Reset type: SYSRSn
14-11	RESERVED	R	0h	Reserved
10	SAMPCAPRESETSEL	R/W	0h	SOC2 Sample Cap Reset Select : Resets sample cap after conversion to either vrefhi/2 or vreflo 0 - The sample cap is reset to Vreflo after each conversion 1 - The sample cap is reset to Vrefhi/2 after each conversion Reset type: SYSRSn
9	SAMPCAPRESETDISABLE	R/W	1h	SOC2 Sample Cap Reset enable : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8	RESERVED	R	0h	Reserved
7-0	ACQPS	R/W	0h	SOC2 Acquisition Prescale. Controls the sample and hold window for each SOC in this Seqeunce. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values If ACQPS[7:6] value is "00" S+H window = ACQPS[5:0] + 1 MCLK cycles "01" S+H window = 64 + ((ACQPS[5:0] +1) * 2) MCLK cycles "10" S+H window = 192 + ((ACQPS[5:0] +1) * 4) MCLK cycles "11" S+H window = 448 + ((ACQPS[5:0] +1) * 16) MCLK cycles Reset type: SYSRSn

15.12.2.69 ADCSEQ3CONFIG_AM13E2X Register (Offset = 32Ch) [Reset = 00000200h]

ADCSEQ3CONFIG_AM13E2X is shown in Figure 15-89 and described in Table 15-85.

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ADC Sequencer 3 Config register

Figure 15-89 ADCSEQ3CONFIG_AM13E2X Register

31	30	29	28	27	26	25	24
SEQENABLE	SEQSWFRC	RESERVED					TRIGSEL
R/W-0h	R-0/W1S-0h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				RESERVED	SEQSTART
R/W-0h				R-0h	R/W-0h

15	14	13	12	11	10	9	8
SEQSTART	RESERVED				SAMPCAPRESETSEL	SAMPCAPRESETDISABLE	RESERVED
R/W-0h	R-0h				R/W-0h	R/W-1h	R-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 15-85 ADCSEQ3CONFIG_AM13E2X Register Field Descriptions

Bit	Field	Type	Reset	Description
31	SEQENABLE	R/W	0h	SEQ3Enable Indicates whether the Sequence3 is enabled or not Reset type: SYSRSn
30	SEQSWFRC	R-0/W1S	0h	Write 1 to force a trigger to Sequencer 3 regardless of the value of Hardware TRIGGER. Always reads 0. Reset type: SYSRSn
29-25	RESERVED	R	0h	Reserved
24-20	TRIGSEL	R/W	0h	SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 0h ADCTRIG0 - Software only 1h - 31h Hardware triggers Reset type: SYSRSn
19	RESERVED	R	0h	Reserved
18-15	SEQSTART	R/W	0h	Beginning SOC of SEQ3 Reset type: SYSRSn
14-11	RESERVED	R	0h	Reserved
10	SAMPCAPRESETSEL	R/W	0h	SOC3 Sample Cap Reset Select : Resets sample cap after conversion to either vrefhi/2 or vreflo 0 - The sample cap is reset to Vreflo after each conversion 1 - The sample cap is reset to Vrefhi/2 after each conversion Reset type: SYSRSn
9	SAMPCAPRESETDISABLE	R/W	1h	SOC3 Sample Cap Reset enable : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8	RESERVED	R	0h	Reserved
7-0	ACQPS	R/W	0h	SOC3 Acquisition Prescale. Controls the sample and hold window for each SOC in this Seqeunce. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values If ACQPS[7:6] value is "00" S+H window = ACQPS[5:0] + 1 MCLK cycles "01" S+H window = 64 + ((ACQPS[5:0] +1) * 2) MCLK cycles "10" S+H window = 192 + ((ACQPS[5:0] +1) * 4) MCLK cycles "11" S+H window = 448 + ((ACQPS[5:0] +1) * 16) MCLK cycles Reset type: SYSRSn

15.12.2.70 ADCSEQ4CONFIG_AM13E2X Register (Offset = 330h) [Reset = 00000200h]

ADCSEQ4CONFIG_AM13E2X is shown in Figure 15-90 and described in Table 15-86.

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ADC Sequencer 4 Config register

Figure 15-90 ADCSEQ4CONFIG_AM13E2X Register

31	30	29	28	27	26	25	24
SEQENABLE	SEQSWFRC	RESERVED					TRIGSEL
R/W-0h	R-0/W1S-0h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				RESERVED	SEQSTART
R/W-0h				R-0h	R/W-0h

15	14	13	12	11	10	9	8
SEQSTART	RESERVED				SAMPCAPRESETSEL	SAMPCAPRESETDISABLE	RESERVED
R/W-0h	R-0h				R/W-0h	R/W-1h	R-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 15-86 ADCSEQ4CONFIG_AM13E2X Register Field Descriptions

Bit	Field	Type	Reset	Description
31	SEQENABLE	R/W	0h	SEQ4Enable Indicates whether the Sequence4 is enabled or not Reset type: SYSRSn
30	SEQSWFRC	R-0/W1S	0h	Write 1 to force a trigger to Sequencer 4 regardless of the value of Hardware TRIGGER. Always reads 0. Reset type: SYSRSn
29-25	RESERVED	R	0h	Reserved
24-20	TRIGSEL	R/W	0h	SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 0h ADCTRIG0 - Software only 1h - 31h Hardware triggers Reset type: SYSRSn
19	RESERVED	R	0h	Reserved
18-15	SEQSTART	R/W	0h	Beginning SOC of SEQ4 Reset type: SYSRSn
14-11	RESERVED	R	0h	Reserved
10	SAMPCAPRESETSEL	R/W	0h	SOC4 Sample Cap Reset Select : Resets sample cap after conversion to either vrefhi/2 or vreflo 0 - The sample cap is reset to Vreflo after each conversion 1 - The sample cap is reset to Vrefhi/2 after each conversion Reset type: SYSRSn
9	SAMPCAPRESETDISABLE	R/W	1h	SOC4 Sample Cap Reset enable : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8	RESERVED	R	0h	Reserved
7-0	ACQPS	R/W	0h	SOC4 Acquisition Prescale. Controls the sample and hold window for each SOC in this Seqeunce. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values If ACQPS[7:6] value is "00" S+H window = ACQPS[5:0] + 1 MCLK cycles "01" S+H window = 64 + ((ACQPS[5:0] +1) * 2) MCLK cycles "10" S+H window = 192 + ((ACQPS[5:0] +1) * 4) MCLK cycles "11" S+H window = 448 + ((ACQPS[5:0] +1) * 16) MCLK cycles Reset type: SYSRSn

15.12.2.71 PWREN Register (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 15-91 and described in Table 15-87.

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Figure 15-91 PWREN Register

31	30	29	28	27	26	25	24
KEY
W-0h

23	22	21	20	19	18	17	16
RESERVED
R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED							ENABLE
R/W-0h							R/WK-0h

Table 15-87 PWREN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	KEY	W	0h	KEY to allow Power State Change 26h = KEY to allow write access to this register
23-1	RESERVED	R/W	0h
0	ENABLE	R/WK	0h	Enable the power [EXT_GPRCM.GPRCM.PWREN.KEY] must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power

15.12.2.72 RSTCTL Register (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 15-92 and described in Table 15-88.

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Figure 15-92 RSTCTL Register

31	30	29	28	27	26	25	24
KEY
W-0h

23	22	21	20	19	18	17	16
RESERVED
W-0h

15	14	13	12	11	10	9	8
RESERVED
W-0h

7	6	5	4	3	2	1	0
RESERVED						RESETSTKYCLR	RESETASSERT
W-0h						WK-0h	WK-0h

Table 15-88 RSTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	KEY	W	0h	Unlock key B1h = KEY to allow write access to this register
23-2	RESERVED	W	0h
1	RESETSTKYCLR	WK	0h	Clear the RESETSTKY bit in the STAT register [EXT_GPRCM.GPRCM.RSTCTL.KEY] must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit
0	RESETASSERT	WK	0h	Assert reset to the peripheral [EXT_GPRCM.GPRCM.RSTCTL.KEY] must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset

15.12.2.73 STAT Register (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 15-93 and described in Table 15-89.

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peripheral enable and reset status

Figure 15-93 STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							RESETSTKYCLR
R-0h							R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 15-89 STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h
16	RESETSTKYCLR	R	0h	This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear
15-0	RESERVED	R	0h