SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

18.11.2 MCPWM_6CH_REGS Registers

Table 18-14 lists the memory-mapped registers for the MCPWM_6CH_REGS registers. All register offset addresses not listed in Table 18-14 should be considered as reserved locations and the register contents should not be modified.

Table 18-14 MCPWM_6CH_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hREVISIONIP revision id registerGo
10hTBCTLTime base control registerGo
14hTBPRDTime base period registerGo
18hTBPRDSTime base period shadow registerGo
1ChTBPHSTime base phase offset registerGo
20hTBSTSTime base status registerGo
24hTBSTSCLRTime base status clear registerGo
28hTBCTRTime base counter registerGo
30hCMPCTLCounter compare control registerGo
40hCMPCCounter compare C registerGo
44hCMPDCounter compare D registerGo
48hCMPCSCounter compare C shadow registerGo
4ChCMPDSCounter compare D shadow registerGo
50hAQCTLAction qualifier control registerGo
60hSOCENStart of conversion enableGo
64hSOCSELStart of conversion selectionGo
68hSOCPERIODStart of conversion periodGo
6ChSOCCNTStart of conversion countGo
70hSOCFLAGStart of conversion flagGo
74hSOCCLRStart of conversion clearGo
80hETSELEvent trigger selectionGo
84hETPERIODEvent trigger periodGo
88hETCNTEvent trigger countGo
90hINTENInterrupt Enable RegisterEALLOWGo
94hINTFLAGInterrupt Flag RegisterGo
98hINTCLRInterrupt Clear RegisterEALLOWGo
9ChINTFRCInterrupt Force RegisterEALLOWGo
A0hTZSELTrip Zone SelectionEALLOWGo
AChTZCTLTrip Zone controlEALLOWGo
B0hTZCBCOSTFLAGTrip Zone CBC and OST Flag RegisterGo
B4hTZCBCOSTCLRTrip Zone CBC and OST Clear RegisterEALLOWGo
C0hDBCTLDead band control registerGo
D0hDBFEDDead band fall edge delayGo
D4hDBREDDead band rise edge delayGo
D8hDBFEDSDead band fall edge delay shadow registerGo
DChDBREDSDead band rise edge delay shadow registerGo
F0hGLDCTLGlobal load control registerEALLOWGo
F4hGLDOSHTCTLGlobal load one shot control registerGo
F8hGLDOSHTSTSGlobal load one shot status registerGo
100hPWM1_CMPAPWM1 counter compare A registerGo
104hPWM1_CMPASPWM1 counter compare A shadow registerGo
108hPWM1_CMPBPWM1 counter compare B registerGo
10ChPWM1_CMPBSPWM1 counter compare B shadow registerGo
120hPWM1_AQCTLAPWM1 action qualifier A registerGo
124hPWM1_AQCTLASPWM1 action qualifier A shadow registerGo
128hPWM1_AQCTLBPWM1 action qualifier B registerGo
12ChPWM1_AQCTLBSPWM1 action qualifier B shadow registerGo
130hPWM1_AQSFRCPWM1 action qualifier software forceGo
134hPWM1_AQOTSFRCPWM1 action qualifier one time software forceGo
300hPWM2_CMPAPWM2 counter compare A registerGo
304hPWM2_CMPASPWM2 counter compare A shadow registerGo
308hPWM2_CMPBPWM2 counter compare B registerGo
30ChPWM2_CMPBSPWM2 counter compare B shadow registerGo
320hPWM2_AQCTLAPWM2 action qualifier A registerGo
324hPWM2_AQCTLASPWM2 action qualifier A shadow registerGo
328hPWM2_AQCTLBPWM2 action qualifier B registerGo
32ChPWM2_AQCTLBSPWM2 action qualifier B shadow registerGo
330hPWM2_AQSFRCPWM2 action qualifier software forceGo
334hPWM2_AQOTSFRCPWM2 action qualifier one time software forceGo
500hPWM3_CMPAPWM3 counter compare A registerGo
504hPWM3_CMPASPWM3 counter compare A shadow registerGo
508hPWM3_CMPBPWM3 counter compare B registerGo
50ChPWM3_CMPBSPWM3 counter compare B shadow registerGo
520hPWM3_AQCTLAPWM3 action qualifier A registerGo
524hPWM3_AQCTLASPWM3 action qualifier A shadow registerGo
528hPWM3_AQCTLBPWM3 action qualifier B registerGo
52ChPWM3_AQCTLBSPWM3 action qualifier B shadow registerGo
530hPWM3_AQSFRCPWM3 action qualifier software forceGo
534hPWM3_AQOTSFRCPWM3 action qualifier one time software forceGo

Complex bit access types are encoded to fit into small table cells. Table 18-15 shows the codes that are used for access types in this section.

Table 18-15 MCPWM_6CH_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

18.11.2.1 REVISION Register (Offset = 0h) [Reset = 00000007h]

REVISION is shown in Figure 18-40 and described in Table 18-16.

Return to the Summary Table.

IP revision id register

Figure 18-40 REVISION Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCAP_PRESENTCMPCD_PRESENTPWM3_PRESENTPWM2_PRESENT
R-0-0hR-0hR-1hR-1hR-1h
Table 18-16 REVISION Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3CAP_PRESENTR0hThis hardcoded field defines the presence of Capture mode feature.

Reset type: SYSRSn

2CMPCD_PRESENTR1hThis hardcoded field defines the presence of Compare C and D registers.

Reset type: SYSRSn

1PWM3_PRESENTR1hThis hardcoded field defines the presence of PWM3 channels.

Reset type: SYSRSn

0PWM2_PRESENTR1hThis hardcoded field defines the presence of PWM2 channels.

Reset type: SYSRSn

18.11.2.2 TBCTL Register (Offset = 10h) [Reset = 00000002h]

TBCTL is shown in Figure 18-41 and described in Table 18-17.

Return to the Summary Table.

Time base control register

Figure 18-41 TBCTL Register
3130292827262524
RESERVEDSYNCISELSYNCPERSEL
R-0-0hR/W-0hR/W-0h
2322212019181716
SYNCPERSELFREE_SOFTRESERVEDSYNCOSEL
R/W-0hR/W-0hR-0-0hR/W-0h
15141312111098
SWSYNCRESERVEDPHSDIRPHSENRESERVEDPRDLD
R-0/W1S-0hR-0-0hR/W-0hR/W-0hR-0-0hR/W-0h
76543210
RESERVEDCLKDIVCTRMODE
R-0-0hR/W-0hR/W-2h
Table 18-17 TBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR-00hReserved
29-25SYNCISELR/W0hThese bits determines the source of SYNCIN signal.
0x0 : Disabled using SOC tieoff.
0x1-0x1F : Refer to PWM chapter of TRM.

Reset type: SYSRSn

24-22SYNCPERSELR/W0hSync peripheral Select

000: Reserved (Disabled)
001: Reserved (Disabled)
010: CTR = PRD
011: CTR = 0
100: CTR = CMPC, Count direction Up
101: CTR = CMPC, Count direction Down
110: CTR = CMPD, Count direction Up
111: CTR = CMPD, Count direction Down

Reset type: SYSRSn

21-20FREE_SOFTR/W0hEmulation Mode Bits. These bits select the behavior of the time-base counter during emulation events

00: Stop after the next time-base counter increment or decrement
01: Stop when counter completes a whole cycle:
- Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
- Up-down-count mode: stop when the time-base counter = 0x00 (TBCTR = 0x00)
1x: Free run

Reset type: SYSRSn

19RESERVEDR-00hReserved
18-16SYNCOSELR/W0hSync Output Select

000: SWFSYNC
001: CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)
010: CTR = CMPC : Time-base counter equal to counter-compare C (TBCTR = CMPC)
011: CTR = CMPD : Time-base counter equal to counter-compare D (TBCTR = CMPD)
1xx: Disabled MCPWMxSYNCO sync signal

Reset type: SYSRSn

15SWSYNCR-0/W1S0hSoftware Forced Sync Pulse

0: Writing a 0 has no effect and reads always return a 0.
1: Writing a 1 forces a one-time synchronization pulse to be generated.

Reset type: SYSRSn

14-12RESERVEDR-00hReserved
11PHSDIRR/W0hPhase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. In the up-count mode, this bit is ignored.

The bit indicates the direction of the time-base counter (TBCTR) after a sync event occurs and a new phase value is loaded from the phase (TBPHS) register.
0: Count down after the sync event.
1: Count up after the sync event.

Reset type: SYSRSn

10PHSENR/W0hLoad Phase register to time-base counter(TBCNTR)

0: Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS).
1: Allow Counter to be loaded from the Phase register (TBPHS) when an MCPWMxSYNCI input signal occurs or a software-forced sync (SWSYNC).

Reset type: SYSRSn

9RESERVEDR-00hReserved
8PRDLDR/W0hShadow to Active load of TBPRD register

0: Shadow to Active Load of TBPRD occurs when TBCTR = 0
1 : Disabled shadow to active load of TBPRD

Reset type: SYSRSn

7-6RESERVEDR-00hReserved
5-2CLKDIVR/W0hTime Base Clock Pre-Scale Bits
These bits select the time base clock pre-scale value (TBCLK = MCPWMCLK/CLKDIV):

0000: /1 (default on reset)
0001: /2
0010: /4
0011: /8
0100: /16
0101: /32
0110: /64
0111: /128
1000: /256
1001: /512
1010: /1024
1011: /2048
1100: /4096
1101: /8192
1110: /16384
1111: /32768

Reset type: SYSRSn

1-0CTRMODER/W2hThe time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows:
00: Up-count mode
01: Up-down count mode
1x: Freeze counter operation (default on reset)

Reset type: SYSRSn

18.11.2.3 TBPRD Register (Offset = 14h) [Reset = 00000000h]

TBPRD is shown in Figure 18-42 and described in Table 18-18.

Return to the Summary Table.

Time base period register

Figure 18-42 TBPRD Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPRD
R-0-0hR/W-0h
Table 18-18 TBPRD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0TBPRDR/W0hTime Base Period Register

These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed.
- If TBCTL[PRDLD] = 0, then the shadow is enabled. This register will also loaded from the shadow register when the time-base counter equals zero.
- If TBCTL[PRDLD] = 1, then the shadow is disabled.

Reset type: SYSRSn

18.11.2.4 TBPRDS Register (Offset = 18h) [Reset = 00000000h]

TBPRDS is shown in Figure 18-43 and described in Table 18-19.

Return to the Summary Table.

Time base period shadow register

Figure 18-43 TBPRDS Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPRDS
R-0-0hR/W-0h
Table 18-19 TBPRDS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0TBPRDSR/W0hTime Base Period Shadow Register

The value in the TBPRDS register is loaded into TBPRD register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.5 TBPHS Register (Offset = 1Ch) [Reset = 00000000h]

TBPHS is shown in Figure 18-44 and described in Table 18-20.

Return to the Summary Table.

Time base phase offset register

Figure 18-44 TBPHS Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPHS
R-0-0hR/W-0h
Table 18-20 TBPHS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0TBPHSR/W0hPhase Offset Register

These bits set time-base counter phase of the PWM relative to the sync (MCPWMxSYNCI / SWFSYNC)

- If TBCTL[PHSEN] = 0, then the sync event is ignored.
- If TBCTL[PHSEN] = 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS) when a sync event occurs. The sync event can be initiated by the input sync signal (MCPWMxSYNCI) or by a software forced sync.

Reset type: SYSRSn

18.11.2.6 TBSTS Register (Offset = 20h) [Reset = 00000000h]

TBSTS is shown in Figure 18-45 and described in Table 18-21.

Return to the Summary Table.

Time base status register

Figure 18-45 TBSTS Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSYNCICTRDIR
R-0-0hR-0hR-0h
Table 18-21 TBSTS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1SYNCIR0hInput Synchronization Latched Status Bit

0: No external sync event has occurred.
1: External sync event has occurred (MCPWMxSYNCI).

Reset type: SYSRSn

0CTRDIRR0hTime Base Counter Direction Status Bit

0: Time-Base Counter is currently counting up.
1: Time-Base Counter is currently counting down.

Note: This bit is only valid when the counter is not frozen.

Reset type: SYSRSn

18.11.2.7 TBSTSCLR Register (Offset = 24h) [Reset = 00000000h]

TBSTSCLR is shown in Figure 18-46 and described in Table 18-22.

Return to the Summary Table.

Time base status clear register

Figure 18-46 TBSTSCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSYNCIRESERVED
R-0-0hR-0/W1S-0hR-0-0h
Table 18-22 TBSTSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1SYNCIR-0/W1S0hInput Synchronization Latched Status Clear

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TBSTS[SYNCI] bit.

Reset type: SYSRSn

0RESERVEDR-00hReserved

18.11.2.8 TBCTR Register (Offset = 28h) [Reset = 00000000h]

TBCTR is shown in Figure 18-47 and described in Table 18-23.

Return to the Summary Table.

Time base counter register

Figure 18-47 TBCTR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBCTR
R-0-0hR/W-0h
Table 18-23 TBCTR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0TBCTRR/W0hTime Base Counter Register

Reset type: SYSRSn

18.11.2.9 CMPCTL Register (Offset = 30h) [Reset = 00000000h]

CMPCTL is shown in Figure 18-48 and described in Table 18-24.

Return to the Summary Table.

Counter compare control register

Figure 18-48 CMPCTL Register
3130292827262524
RESERVEDLOADDMODELOADCMODE
R-0-0hR/W-0hR/W-0h
2322212019181716
RESERVEDPWM3_LOADBMODEPWM3_LOADAMODE
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVEDPWM2_LOADBMODEPWM2_LOADAMODE
R-0-0hR/W-0hR/W-0h
76543210
RESERVEDPWM1_LOADBMODEPWM1_LOADAMODE
R-0-0hR/W-0hR/W-0h
Table 18-24 CMPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR-00hReserved
27-26LOADDMODER/W0hShadow to Active load of CMPD register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter CCM_CD_PRESENT = 1

Reset type: SYSRSn

25-24LOADCMODER/W0hShadow to Active load of CMPC register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter CCM_CD_PRESENT = 1

Reset type: SYSRSn

23-20RESERVEDR-00hReserved
19-18PWM3_LOADBMODER/W0hShadow to Active load of PWM3_CMPB register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter PWM3_PRESENT = 1

Reset type: SYSRSn

17-16PWM3_LOADAMODER/W0hShadow to Active load of PWM3_CMPA register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter PWM3_PRESENT = 1

Reset type: SYSRSn

15-12RESERVEDR-00hReserved
11-10PWM2_LOADBMODER/W0hShadow to Active load of PWM2_CMPB register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter PWM2_PRESENT = 1

Reset type: SYSRSn

9-8PWM2_LOADAMODER/W0hShadow to Active load of PWM2_CMPA register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter PWM2_PRESENT = 1

Reset type: SYSRSn

7-4RESERVEDR-00hReserved
3-2PWM1_LOADBMODER/W0hShadow to Active load of PWM1_CMPB register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

1-0PWM1_LOADAMODER/W0hShadow to Active load of PWM1_CMPA register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

18.11.2.10 CMPC Register (Offset = 40h) [Reset = 00000000h]

CMPC is shown in Figure 18-49 and described in Table 18-25.

Return to the Summary Table.

Counter compare C register

Figure 18-49 CMPC Register
313029282726252423222120191817161514131211109876543210
RESERVEDCMPC
R-0-0hR/W-0h
Table 18-25 CMPC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CMPCR/W0hCompare C register

The value in the CMPC register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a 'time-base counter equal to counter compare C' event.

Shadowing of this register is enabled and disabled by the CMPCTL[LOADCMODE] field. By default this register is shadowed.

Reset type: SYSRSn

18.11.2.11 CMPD Register (Offset = 44h) [Reset = 00000000h]

CMPD is shown in Figure 18-50 and described in Table 18-26.

Return to the Summary Table.

Counter compare D register

Figure 18-50 CMPD Register
313029282726252423222120191817161514131211109876543210
RESERVEDCMPD
R-0-0hR/W-0h
Table 18-26 CMPD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CMPDR/W0hCompare D register

The value in the CMPD register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a 'time-base counter equal to counter compare D' event.

Shadowing of this register is enabled and disabled by the CMPCTL[LOADDMODE] field. By default this register is shadowed.

Reset type: SYSRSn

18.11.2.12 CMPCS Register (Offset = 48h) [Reset = 00000000h]

CMPCS is shown in Figure 18-51 and described in Table 18-27.

Return to the Summary Table.

Counter compare C shadow register

Figure 18-51 CMPCS Register
313029282726252423222120191817161514131211109876543210
RESERVEDCMPCS
R-0-0hR/W-0h
Table 18-27 CMPCS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CMPCSR/W0hCompare C Shadow Register

The value in the CMPCS register is loaded into CMPC register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.13 CMPDS Register (Offset = 4Ch) [Reset = 00000000h]

CMPDS is shown in Figure 18-52 and described in Table 18-28.

Return to the Summary Table.

Counter compare D shadow register

Figure 18-52 CMPDS Register
313029282726252423222120191817161514131211109876543210
RESERVEDCMPDS
R-0-0hR/W-0h
Table 18-28 CMPDS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CMPDSR/W0hCompare D Shadow Register

The value in the CMPDS register is loaded into CMPD register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.14 AQCTL Register (Offset = 50h) [Reset = 00000000h]

AQCTL is shown in Figure 18-53 and described in Table 18-29.

Return to the Summary Table.

Action qualifier control register

Figure 18-53 AQCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDPWM3_LDAQBMODEPWM3_LDAQAMODE
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVEDPWM2_LDAQBMODEPWM2_LDAQAMODE
R-0-0hR/W-0hR/W-0h
76543210
RESERVEDPWM1_LDAQBMODEPWM1_LDAQAMODE
R-0-0hR/W-0hR/W-0h
Table 18-29 AQCTL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19-18PWM3_LDAQBMODER/W0hShadow to Active load of PWM3_AQCTLB register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter PWM3_PRESENT = 1

Reset type: SYSRSn

17-16PWM3_LDAQAMODER/W0hShadow to Active load of PWM3_AQCTLA register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter PWM3_PRESENT = 1

Reset type: SYSRSn

15-12RESERVEDR-00hReserved
11-10PWM2_LDAQBMODER/W0hShadow to Active load of PWM2_AQCTLB register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter PWM2_PRESENT = 1

Reset type: SYSRSn

9-8PWM2_LDAQAMODER/W0hShadow to Active load of PWM2_AQCTLA register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter PWM2_PRESENT = 1

Reset type: SYSRSn

7-4RESERVEDR-00hReserved
3-2PWM1_LDAQBMODER/W0hShadow to Active load of PWM1_AQCTLB register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

1-0PWM1_LDAQAMODER/W0hShadow to Active load of PWM1_AQCTLA register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

18.11.2.15 SOCEN Register (Offset = 60h) [Reset = 00000000h]

SOCEN is shown in Figure 18-54 and described in Table 18-30.

Return to the Summary Table.

Start of conversion enable

Figure 18-54 SOCEN Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSOCD_ENABLESOCC_ENABLESOCB_ENABLESOCA_ENABLE
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-30 SOCEN Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3SOCD_ENABLER/W0hSOCD Selection Enable

0 - SOCD disable
1- SOCD enable

Reset type: SYSRSn

2SOCC_ENABLER/W0hSOCC Selection Enable

0 - SOCC disable
1- SOCC enable

Reset type: SYSRSn

1SOCB_ENABLER/W0hSOCB Selection Enable

0 - SOCB disable
1- SOCB enable

Reset type: SYSRSn

0SOCA_ENABLER/W0hSOCA Selection Enable

0 - SOCA disable
1- SOCA enable

Reset type: SYSRSn

18.11.2.16 SOCSEL Register (Offset = 64h) [Reset = 00000000h]

SOCSEL is shown in Figure 18-55 and described in Table 18-31.

Return to the Summary Table.

Start of conversion selection

Figure 18-55 SOCSEL Register
31302928272625242322212019181716
RESERVEDSOCD_SELRESERVEDSOCC_SEL
R-0-0hR/W-0hR-0-0hR/W-0h
1514131211109876543210
RESERVEDSOCB_SELRESERVEDSOCA_SEL
R-0-0hR/W-0hR-0-0hR/W-0h
Table 18-31 SOCSEL Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR-00hReserved
28-24SOCD_SELR/W0hSOCD Selection Options

These bits determine when SOCD pulse will be generated.

00000: Reserved (SOC D disabled)
00001: Reserved (SOC D disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (SOC D disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (SOC D disabled)

Reset type: SYSRSn

23-21RESERVEDR-00hReserved
20-16SOCC_SELR/W0hSOCC Selection Options

These bits determine when SOCC pulse will be generated.

00000: Reserved (SOC C disabled)
00001: Reserved (SOC C disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (SOC C disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (SOC C disabled)

Reset type: SYSRSn

15-13RESERVEDR-00hReserved
12-8SOCB_SELR/W0hSOCB Selection Options

These bits determine when SOCB pulse will be generated.

00000: Reserved (SOC B disabled)
00001: Reserved (SOC B disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (SOC B disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (SOC B disabled)

Reset type: SYSRSn

7-5RESERVEDR-00hReserved
4-0SOCA_SELR/W0hSOCA Selection Options

These bits determine when SOCA pulse will be generated.

00000: Reserved (SOC A disabled)
00001: Reserved (SOC A disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (SOC A disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (SOC A disabled)

Reset type: SYSRSn

18.11.2.17 SOCPERIOD Register (Offset = 68h) [Reset = 00000000h]

SOCPERIOD is shown in Figure 18-56 and described in Table 18-32.

Return to the Summary Table.

Start of conversion period

Figure 18-56 SOCPERIOD Register
3130292827262524
RESERVEDSOCD_PERIOD
R-0-0hR/W-0h
2322212019181716
RESERVEDSOCC_PERIOD
R-0-0hR/W-0h
15141312111098
RESERVEDSOCB_PERIOD
R-0-0hR/W-0h
76543210
RESERVEDSOCA_PERIOD
R-0-0hR/W-0h
Table 18-32 SOCPERIOD Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR-00hReserved
26-24SOCD_PERIODR/W0hSOCD Period

These bits determine how many selected SOCSEL[SOCD_SEL] events need to occur before an SOCD pulse is generated. To be generated, the pulse must be enabled (SOCEN[SOCD_ENABLE] = 1). The SOCD pulse will be generated even if the status flag is set from a previous start of conversion (SOCFLAG[SOCD] = 1). Once the SOCD pulse is generated, the SOCCNT[SOCD_CNT] bits will automatically be cleared.

Reset type: SYSRSn

23-19RESERVEDR-00hReserved
18-16SOCC_PERIODR/W0hSOCC Period

These bits determine how many selected SOCSEL[SOCC_SEL] events need to occur before an SOCC pulse is generated. To be generated, the pulse must be enabled (SOCEN[SOCC_ENABLE] = 1). The SOCC pulse will be generated even if the status flag is set from a previous start of conversion (SOCFLAG[SOCC] = 1). Once the SOCC pulse is generated, the SOCCNT[SOCC_CNT] bits will automatically be cleared.

Reset type: SYSRSn

15-11RESERVEDR-00hReserved
10-8SOCB_PERIODR/W0hSOCB Period

These bits determine how many selected SOCSEL[SOCB_SEL] events need to occur before an SOCB pulse is generated. To be generated, the pulse must be enabled (SOCEN[SOCB_ENABLE] = 1). The SOCB pulse will be generated even if the status flag is set from a previous start of conversion (SOCFLAG[SOCB] = 1). Once the SOCB pulse is generated, the SOCCNT[SOCB_CNT] bits will automatically be cleared.

Reset type: SYSRSn

7-3RESERVEDR-00hReserved
2-0SOCA_PERIODR/W0hSOCA Period

These bits determine how many selected SOCSEL[SOCA_SEL] events need to occur before an SOCA pulse is generated. To be generated, the pulse must be enabled (SOCEN[SOCA_ENABLE] = 1). The SOCA pulse will be generated even if the status flag is set from a previous start of conversion (SOCFLAG[SOCA] = 1). Once the SOCA pulse is generated, the SOCCNT[SOCA_CNT] bits will automatically be cleared.

Reset type: SYSRSn

18.11.2.18 SOCCNT Register (Offset = 6Ch) [Reset = 00000000h]

SOCCNT is shown in Figure 18-57 and described in Table 18-33.

Return to the Summary Table.

Start of conversion count

Figure 18-57 SOCCNT Register
31302928272625242322212019181716
RESERVEDSOCD_CNTRESERVEDSOCC_CNT
R-0-0hR-0hR-0-0hR-0h
1514131211109876543210
RESERVEDSOCB_CNTRESERVEDSOCA_CNT
R-0-0hR-0hR-0-0hR-0h
Table 18-33 SOCCNT Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR-00hReserved
26-24SOCD_CNTR0hSOC D Counter Register

These bits indicate how many selected SOCSEL[SOCD_SEL] events have occurred. These bits are automatically cleared when a SOCD pulse is generated.

Reset type: SYSRSn

23-19RESERVEDR-00hReserved
18-16SOCC_CNTR0hSOC C Counter Register

These bits indicate how many selected SOCSEL[SOCC_SEL] events have occurred. These bits are automatically cleared when a SOCC pulse is generated.

Reset type: SYSRSn

15-11RESERVEDR-00hReserved
10-8SOCB_CNTR0hSOC B Counter Register

These bits indicate how many selected SOCSEL[SOCB_SEL] events have occurred. These bits are automatically cleared when a SOCB pulse is generated.

Reset type: SYSRSn

7-3RESERVEDR-00hReserved
2-0SOCA_CNTR0hSOC A Counter Register

These bits indicate how many selected SOCSEL[SOCA_SEL] events have occurred. These bits are automatically cleared when a SOCA pulse is generated.

Reset type: SYSRSn

18.11.2.19 SOCFLAG Register (Offset = 70h) [Reset = 00000000h]

SOCFLAG is shown in Figure 18-58 and described in Table 18-34.

Return to the Summary Table.

Start of conversion flag

Figure 18-58 SOCFLAG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSOCDSOCCSOCBSOCA
R-0-0hR-0hR-0hR-0hR-0h
Table 18-34 SOCFLAG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3SOCDR0hLatched SOC D Status Flag

SOCD output will continue to pulse even if the flag bit is set.

0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on SOCD. The SOCD output will continue to be generated even if the flag bit is set.

Reset type: SYSRSn

2SOCCR0hLatched SOC C Status Flag

SOCC output will continue to pulse even if the flag bit is set.

0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on SOCC. The SOCC output will continue to be generated even if the flag bit is set.

Reset type: SYSRSn

1SOCBR0hLatched SOC B Status Flag

SOCB output will continue to pulse even if the flag bit is set.

0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on SOCB. The SOCB output will continue to be generated even if the flag bit is set.

Reset type: SYSRSn

0SOCAR0hLatched SOC A Status Flag

SOCA output will continue to pulse even if the flag bit is set.

0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on SOCA. The SOCA output will continue to be generated even if the flag bit is set.

Reset type: SYSRSn

18.11.2.20 SOCCLR Register (Offset = 74h) [Reset = 00000000h]

SOCCLR is shown in Figure 18-59 and described in Table 18-35.

Return to the Summary Table.

Start of conversion clear

Figure 18-59 SOCCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSOCDSOCCSOCBSOCA
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 18-35 SOCCLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3SOCDR-0/W1S0hClear SOC D Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the SOCFLAG[SOCD] bit.

Reset type: SYSRSn

2SOCCR-0/W1S0hClear SOC C Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the SOCFLAG[SOCC] bit.

Reset type: SYSRSn

1SOCBR-0/W1S0hClear SOC B Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the SOCFLAG[SOCB] bit.

Reset type: SYSRSn

0SOCAR-0/W1S0hClear SOC A Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the SOCFLAG[SOCA] bit.

Reset type: SYSRSn

18.11.2.21 ETSEL Register (Offset = 80h) [Reset = 00000000h]

ETSEL is shown in Figure 18-60 and described in Table 18-36.

Return to the Summary Table.

Event trigger selection

Figure 18-60 ETSEL Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDET2_SELRESERVEDET1_SEL
R-0-0hR/W-0hR-0-0hR/W-0h
Table 18-36 ETSEL Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR-00hReserved
12-8ET2_SELR/W0hEvent trigger2 Selection Options

These bits determine when event trigger pulse will be generated.

00000: Reserved (ET2 Disabled)
00001: Reserved (ET2 Disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (ET2 Disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (ET2 Disabled)

Reset type: SYSRSn

7-5RESERVEDR-00hReserved
4-0ET1_SELR/W0hEvent trigger1 Selection Options

These bits determine when event trigger pulse will be generated.

00000: Reserved (ET1 Disabled)
00001: Reserved (ET1 Disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (ET1 Disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (ET1 Disabled)

Reset type: SYSRSn

18.11.2.22 ETPERIOD Register (Offset = 84h) [Reset = 00000000h]

ETPERIOD is shown in Figure 18-61 and described in Table 18-37.

Return to the Summary Table.

Event trigger period

Figure 18-61 ETPERIOD Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDET2_PERIOD
R-0-0hR/W-0h
76543210
RESERVEDET1_PERIOD
R-0-0hR/W-0h
Table 18-37 ETPERIOD Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR-00hReserved
10-8ET2_PERIODR/W0hThese bits determine how many selected ETSEL[ET2_SEL] events need to occur before an interrupt is generated. If the interrupt status flag is set from a previous interrupt (INTFLG[ET2] = 1) then no interrupt will be generated until the flag is cleared via the INTCLR[ET2] bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETCNT[ET2_CNT] bits will automatically be cleared.

Writing a PERIOD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear.

Writing a PERIOD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero PERIOD value is written, the counter is incremented.

Reset type: SYSRSn

7-3RESERVEDR-00hReserved
2-0ET1_PERIODR/W0hThese bits determine how many selected ETSEL[ET1_SEL] events need to occur before an interrupt is generated. If the interrupt status flag is set from a previous interrupt (INTFLG[ET1] = 1) then no interrupt will be generated until the flag is cleared via the INTCLR[ET1] bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETCNT[ET1_CNT] bits will automatically be cleared.

Writing a PERIOD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear.

Writing a PERIOD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero PERIOD value is written, the counter is incremented.

Reset type: SYSRSn

18.11.2.23 ETCNT Register (Offset = 88h) [Reset = 00000000h]

ETCNT is shown in Figure 18-62 and described in Table 18-38.

Return to the Summary Table.

Event trigger count

Figure 18-62 ETCNT Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDET2_CNTRESERVEDET1_CNT
R-0-0hR-0hR-0-0hR-0h
Table 18-38 ETCNT Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR-00hReserved
10-8ET2_CNTR0hEvent trigger2 Counter Register

These bits indicate how many selected ET_SEL[ET2_SEL] events have occurred. These bits are automatically cleared once INTFLAG.ET2 is generated (irrespective of INTEN.ET2 configuration).

Reset type: SYSRSn

7-3RESERVEDR-00hReserved
2-0ET1_CNTR0hEvent trigger1 Counter Register

These bits indicate how many selected ET_SEL[ET1_SEL] events have occurred. These bits are automatically cleared once INTFLAG.ET1 is generated (irrespective of INTEN.ET1 configuration).

Reset type: SYSRSn

18.11.2.24 INTEN Register (Offset = 90h) [Reset = 00000000h]

INTEN is shown in Figure 18-63 and described in Table 18-39.

Return to the Summary Table.

Interrupt Enable Register

Figure 18-63 INTEN Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCNT_OVFET2ET1OSTCBCRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 18-39 INTEN Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5CNT_OVFR/W0hCounter Overflow Interrupt Enable
1 : Enables CNT_OVF interrupt
0 : Disable CNT_OVF interrupt

Reset type: SYSRSn

4ET2R/W0hEvent Trigger 2 Interrupt Enable
1 : Enables ET2 interrupt
0 : Disable ET2 interrupt

Reset type: SYSRSn

3ET1R/W0hEvent Trigger 1 Interrupt Enable
1 : Enables ET1 interrupt
0 : Disable ET1 interrupt

Reset type: SYSRSn

2OSTR/W0hTrip-zone One-Shot Interrupt Enable
1 : Enables OST interrupt
0 : Disable OST interrupt

Reset type: SYSRSn

1CBCR/W0hTrip-zone Cycle-by-Cycle Interrupt Enable
1 : Enables CBC interrupt
0 : Disable CBC interrupt

Reset type: SYSRSn

0RESERVEDR0hReserved

18.11.2.25 INTFLAG Register (Offset = 94h) [Reset = 00000000h]

INTFLAG is shown in Figure 18-64 and described in Table 18-40.

Return to the Summary Table.

Interrupt Flag Register

Figure 18-64 INTFLAG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCNT_OVFET2ET1OSTCBCINT
R-0-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 18-40 INTFLAG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5CNT_OVFR0hLatched Status Flag for A Counter Overflow Event
1 : CNT_OVF flag is set
0 : CNT_OVF flag is not set

Reset type: SYSRSn

4ET2R0hLatched Status Flag for A Event Trigger 2 Event
1: ET2 flag is set
0: ET2 flag is not set

Reset type: SYSRSn

3ET1R0hLatched Status Flag for A Event Trigger 1 Event
1: ET1 flag is set
0: ET1 flag is not set

Reset type: SYSRSn

2OSTR0hLatched Status Flag for A One-Shot Trip Event
1: OST flag is set
0: OST flag is not set

Reset type: SYSRSn

1CBCR0hLatched Status Flag for Cycle-By-Cycle Trip Event
1: CBC flag is set
0: CBC flag is not set

Reset type: SYSRSn

0INTR0hGlobal Interrupt Status Flag
1: Global flag is set
0: Global flag is not set

Reset type: SYSRSn

18.11.2.26 INTCLR Register (Offset = 98h) [Reset = 00000000h]

INTCLR is shown in Figure 18-65 and described in Table 18-41.

Return to the Summary Table.

Interrupt Clear Register

Figure 18-65 INTCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCNT_OVFET2ET1OSTCBCINT
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 18-41 INTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5CNT_OVFR-0/W1S0hClear Counter Overflow Flag
Writing '1' will clear INTFLAG[CNT_OVF] register.

Reset type: SYSRSn

4ET2R-0/W1S0hClear Event Trigger 2 Flag
Writing '1' will clear INTFLAG[ET2] register.

Reset type: SYSRSn

3ET1R-0/W1S0hClear Event Trigger 1 Flag
Writing '1' will clear INTFLAG[ET1] register.

Reset type: SYSRSn

2OSTR-0/W1S0hClear One-Shot Trip Latch
Writing '1' will clear INTFLAG[OST] register.

Reset type: SYSRSn

1CBCR-0/W1S0hClear Cycle-by-Cycle Trip Latch
Writing '1' will clear INTFLAG[CBC] register.

Reset type: SYSRSn

0INTR-0/W1S0hClear Global Interrupt Flag
Writing '1' will clear INTFLAG[INT] register.

Reset type: SYSRSn

18.11.2.27 INTFRC Register (Offset = 9Ch) [Reset = 00000000h]

INTFRC is shown in Figure 18-66 and described in Table 18-42.

Return to the Summary Table.

Interrupt Force Register

Figure 18-66 INTFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCNT_OVFET2ET1OSTCBCRESERVED
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0h
Table 18-42 INTFRC Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5CNT_OVFR-0/W1S0hForce Counter Overflow Interrupt
Writing '1' will set INTFLAG[CNT_OVF] register.

Reset type: SYSRSn

4ET2R-0/W1S0hForce Event Trigger 2 Interrupt
Writing '1' will set INTFLAG[ET2] register.

Reset type: SYSRSn

3ET1R-0/W1S0hForce Event Trigger 1 Interrupt
Writing '1' will set INTFLAG[ET1] register.

Reset type: SYSRSn

2OSTR-0/W1S0hForce One-Shot Trip Interrupt
Writing '1' will set INTFLAG[OST] register.

Reset type: SYSRSn

1CBCR-0/W1S0hForce Cycle-by-Cycle Trip Interrupt
Writing '1' will set INTFLAG[CBC] register.

Reset type: SYSRSn

0RESERVEDR0hReserved

18.11.2.28 TZSEL Register (Offset = A0h) [Reset = 00000000h]

TZSEL is shown in Figure 18-67 and described in Table 18-43.

Return to the Summary Table.

Trip Zone Selection

Figure 18-67 TZSEL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
OST8OST7OST6OST5OST4OST3OST2OST1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
CBC8CBC7CBC6CBC5CBC4CBC3CBC2CBC1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-43 TZSEL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR-00hReserved
23OST8R/W0hSelect Trip-zone 8 (TZ8) for OST generation

0: Disable TZ8 as a OST trip source for this MCPWM module
1: Enable TZ8 as a OST trip source for this MCPWM module

Reset type: SYSRSn

22OST7R/W0hSelect Trip-zone 7 (TZ7) for OST generation

0: Disable TZ7 as a OST trip source for this MCPWM module
1: Enable TZ7 as a OST trip source for this MCPWM module

Reset type: SYSRSn

21OST6R/W0hSelect Trip-zone 6 (TZ6) for OST generation

0: Disable TZ6 as a OST trip source for this MCPWM module
1: Enable TZ6 as a OST trip source for this MCPWM module

Reset type: SYSRSn

20OST5R/W0hSelect Trip-zone 5 (TZ5) for OST generation

0: Disable TZ5 as a OST trip source for this MCPWM module
1: Enable TZ5 as a OST trip source for this MCPWM module

Reset type: SYSRSn

19OST4R/W0hSelect Trip-zone 4 (TZ4) for OST generation

0: Disable TZ4 as a OST trip source for this MCPWM module
1: Enable TZ4 as a OST trip source for this MCPWM module

Reset type: SYSRSn

18OST3R/W0hSelect Trip-zone 3 (TZ3) for OST generation

0: Disable TZ3 as a OST trip source for this MCPWM module
1: Enable TZ3 as a OST trip source for this MCPWM module

Reset type: SYSRSn

17OST2R/W0hSelect Trip-zone 2 (TZ2) for OST generation

0: Disable TZ2 as a OST trip source for this MCPWM module
1: Enable TZ2 as a OST trip source for this MCPWM module

Reset type: SYSRSn

16OST1R/W0hSelect Trip-zone 1 (TZ1) for OST generation

0: Disable TZ1 as a OST trip source for this MCPWM module
1: Enable TZ1 as a OST trip source for this MCPWM module

Reset type: SYSRSn

15-8RESERVEDR-00hReserved
7CBC8R/W0hSelect Trip-zone 8 (TZ8) for CBC generation

0: Disable TZ8 as a CBC trip source for this MCPWM module
1: Enable TZ8 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

6CBC7R/W0hSelect Trip-zone 7 (TZ7) for CBC generation

0: Disable TZ7 as a CBC trip source for this MCPWM module
1: Enable TZ7 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

5CBC6R/W0hSelect Trip-zone 6 (TZ6) for CBC generation

0: Disable TZ6 as a CBC trip source for this MCPWM module
1: Enable TZ6 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

4CBC5R/W0hSelect Trip-zone 5 (TZ5) for CBC generation

0: Disable TZ5 as a CBC trip source for this MCPWM module
1: Enable TZ5 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

3CBC4R/W0hSelect Trip-zone 4 (TZ4) for CBC generation

0: Disable TZ4 as a CBC trip source for this MCPWM module
1: Enable TZ4 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

2CBC3R/W0hSelect Trip-zone 3 (TZ3) for CBC generation

0: Disable TZ3 as a CBC trip source for this MCPWM module
1: Enable TZ3 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

1CBC2R/W0hSelect Trip-zone 2 (TZ2) for CBC generation

0: Disable TZ2 as a CBC trip source for this MCPWM module
1: Enable TZ2 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

0CBC1R/W0hSelect Trip-zone 1 (TZ1) for CBC generation

0: Disable TZ1 as a CBC trip source for this MCPWM module
1: Enable TZ1 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

18.11.2.29 TZCTL Register (Offset = ACh) [Reset = 00000010h]

TZCTL is shown in Figure 18-68 and described in Table 18-44.

Return to the Summary Table.

Trip Zone control

Figure 18-68 TZCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCBCPULSETZBTZA
R-0-0hR/W-1hR/W-0hR/W-0h
Table 18-44 TZCTL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5-4CBCPULSER/W1hClear Pulse for Cycle-By-Cycle (CBC) Trip Latch

This bit field determines which pulse clears the CBC trip latch.

00: CBC trip latch is not cleared
01: CTR = ZERO pulse clears CBC trip latch
10: CTR = PRD pulse clears CBC trip latch
11: CTR = ZERO or CTR = PRD pulse clears CBC trip latch

Reset type: SYSRSn

3-2TZBR/W0hTrip action on PWMxB

00: High-impedance (PWMxB = High-impedance state)
01: Force PWMxB to a high state
10: Force PWMxB to a low state
11: Do nothing, no action is taken on PWMxB.

Reset type: SYSRSn

1-0TZAR/W0hTrip action on PWMxA

00: High-impedance (PWMxA = High-impedance state)
01: Force PWMxA to a high state
10: Force PWMxA to a low state
11: Do nothing, no action is taken on PWMxA.

Reset type: SYSRSn

18.11.2.30 TZCBCOSTFLAG Register (Offset = B0h) [Reset = 00000000h]

TZCBCOSTFLAG is shown in Figure 18-69 and described in Table 18-45.

Return to the Summary Table.

Trip Zone CBC and OST Flag Register

Figure 18-69 TZCBCOSTFLAG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
OST8OST7OST6OST5OST4OST3OST2OST1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0-0h
76543210
CBC8CBC7CBC6CBC5CBC4CBC3CBC2CBC1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 18-45 TZCBCOSTFLAG Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR-00hReserved
23OST8R0hLatched Status Flag for OST TZ8 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ8.
1: Reading a 1 indicates a OST trip has occured by TZ8.

Reset type: SYSRSn

22OST7R0hLatched Status Flag for OST TZ7 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ7.
1: Reading a 1 indicates a OST trip has occured by TZ7.

Reset type: SYSRSn

21OST6R0hLatched Status Flag for OST TZ6 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ6.
1: Reading a 1 indicates a OST trip has occured by TZ6.

Reset type: SYSRSn

20OST5R0hLatched Status Flag for OST TZ5 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ5.
1: Reading a 1 indicates a OST trip has occured by TZ5.

Reset type: SYSRSn

19OST4R0hLatched Status Flag for OST TZ4 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ4.
1: Reading a 1 indicates a OST trip has occured by TZ4.

Reset type: SYSRSn

18OST3R0hLatched Status Flag for OST TZ3 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ3.
1: Reading a 1 indicates a OST trip has occured by TZ3.

Reset type: SYSRSn

17OST2R0hLatched Status Flag for OST TZ2 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ2.
1: Reading a 1 indicates a OST trip has occured by TZ2.

Reset type: SYSRSn

16OST1R0hLatched Status Flag for OST TZ1 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ1.
1: Reading a 1 indicates a OST trip has occured by TZ1.

Reset type: SYSRSn

15-8RESERVEDR-00hReserved
7CBC8R0hLatched Status Flag for CBC TZ8 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ8.
1: Reading a 1 indicates a CBC trip has occured by TZ8.

Reset type: SYSRSn

6CBC7R0hLatched Status Flag for CBC TZ7 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ7.
1: Reading a 1 indicates a CBC trip has occured by TZ7.

Reset type: SYSRSn

5CBC6R0hLatched Status Flag for CBC TZ6 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ6.
1: Reading a 1 indicates a CBC trip has occured by TZ6.

Reset type: SYSRSn

4CBC5R0hLatched Status Flag for CBC TZ5 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ5.
1: Reading a 1 indicates a CBC trip has occured by TZ5.

Reset type: SYSRSn

3CBC4R0hLatched Status Flag for CBC TZ4 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ4.
1: Reading a 1 indicates a CBC trip has occured by TZ4.

Reset type: SYSRSn

2CBC3R0hLatched Status Flag for CBC TZ3 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ3.
1: Reading a 1 indicates a CBC trip has occured by TZ3.

Reset type: SYSRSn

1CBC2R0hLatched Status Flag for CBC TZ2 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ2.
1: Reading a 1 indicates a CBC trip has occured by TZ2.

Reset type: SYSRSn

0CBC1R0hLatched Status Flag for CBC TZ1 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ1.
1: Reading a 1 indicates a CBC trip has occured by TZ1.

Reset type: SYSRSn

18.11.2.31 TZCBCOSTCLR Register (Offset = B4h) [Reset = 00000000h]

TZCBCOSTCLR is shown in Figure 18-70 and described in Table 18-46.

Return to the Summary Table.

Trip Zone CBC and OST Clear Register

Figure 18-70 TZCBCOSTCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
OST8OST7OST6OST5OST4OST3OST2OST1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
RESERVED
R-0-0h
76543210
CBC8CBC7CBC6CBC5CBC4CBC3CBC2CBC1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 18-46 TZCBCOSTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR-00hReserved
23OST8R-0/W1S0hClear OST TZ8 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST8] bit.

Reset type: SYSRSn

22OST7R-0/W1S0hClear OST TZ7 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST7] bit.

Reset type: SYSRSn

21OST6R-0/W1S0hClear OST TZ6 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST6] bit.

Reset type: SYSRSn

20OST5R-0/W1S0hClear OST TZ5 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST5] bit.

Reset type: SYSRSn

19OST4R-0/W1S0hClear OST TZ4 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST4] bit.

Reset type: SYSRSn

18OST3R-0/W1S0hClear OST TZ3 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST3] bit.

Reset type: SYSRSn

17OST2R-0/W1S0hClear OST TZ2 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST2] bit.

Reset type: SYSRSn

16OST1R-0/W1S0hClear OST TZ1 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST1] bit.

Reset type: SYSRSn

15-8RESERVEDR-00hReserved
7CBC8R-0/W1S0hClear CBC TZ8 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC8] bit.

Reset type: SYSRSn

6CBC7R-0/W1S0hClear CBC TZ7 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC7] bit.

Reset type: SYSRSn

5CBC6R-0/W1S0hClear CBC TZ6 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC6] bit.

Reset type: SYSRSn

4CBC5R-0/W1S0hClear CBC TZ5 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC5] bit.

Reset type: SYSRSn

3CBC4R-0/W1S0hClear CBC TZ4 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC4] bit.

Reset type: SYSRSn

2CBC3R-0/W1S0hClear CBC TZ3 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC3] bit.

Reset type: SYSRSn

1CBC2R-0/W1S0hClear CBC TZ2 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC2] bit.

Reset type: SYSRSn

0CBC1R-0/W1S0hClear CBC TZ1 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC1] bit.

Reset type: SYSRSn

18.11.2.32 DBCTL Register (Offset = C0h) [Reset = 00000000h]

DBCTL is shown in Figure 18-71 and described in Table 18-47.

Return to the Summary Table.

Dead band control register

Figure 18-71 DBCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDLOADREDMODELOADFEDMODE
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVEDDEDB_MODE
R-0-0hR/W-0h
76543210
OUTSWAPIN_MODEPOLSELOUT_MODE
R/W-0hR/W-0hR/W-0hR/W-0h
Table 18-47 DBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19-18LOADREDMODER/W0hShadow to Active load of DBRED register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

17-16LOADFEDMODER/W0hShadow to Active load of DBFED register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

15-9RESERVEDR-00hReserved
8DEDB_MODER/W0hDead Band Dual-Edge B Mode Control (S8 switch)

0: Rising edge delay applied to InA/InB as selected by S4 switch (IN-MODE bits) on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch (INMODE bits) on B signal path only.
1: Rising edge delay and falling edge delay applied to source selected by S4 switch (INMODE bits) and output to B signal path only. Note: When this bit is set to 1, user should always either set OUT_MODE bits such that Apath = InA OR OUTSWAP bits such that OutA=Bpath
otherwise, OutA will be invalid.

Reset type: SYSRSn

7-6OUTSWAPR/W0hDead Band Output Swap Control

Bit 7 controls the S6 switch and bit 6 controls the S7 switch.

00: OutA and OutB signals are as defined by OUT-MODE bits.
01: OutA = A-path as defined by OUT-MODE bits.
OutB = A-path as defined by OUT-MODE bits (rising edge delay or delay-bypassed A signal path).
10: OutA = B-path as defined by OUT-MODE bits (falling edge delay or delay-bypassed B signal path).
OutB = B-path as defined by OUT-MODE bits.
11: OutA = B-path as defined by OUT-MODE bits (falling edge delay or delay-bypassed B signal path).
OutB = A-path as defined by OUT-MODE bits (rising edge delay or delay-bypassed A signal path).

Reset type: SYSRSn

5-4IN_MODER/W0hDead-Band Input Mode Control

Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is PWMxA In is the source for both falling and rising-edge delays.

00: PWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
01: PWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
PWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
10: PWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
PWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
11: PWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal.

Reset type: SYSRSn

3-2POLSELR/W0hPolarity Select Control

Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0x0. Other enhanced modes are also possible, but not regarded as typical usage modes.

00: Active high (AH) mode. Neither PWMxA nor PWMxB is inverted (default).
01: Active low complementary (ALC) mode. PWMxA is inverted.
10: Active high complementary (AHC). PWMxB is inverted.
11: Active low (AL) mode. Both PWMxA and PWMxB are inverted.

Reset type: SYSRSn

1-0OUT_MODER/W0hDead-Band Output Mode Control

Bit 1 controls the S1 switch and bit 0 controls the S0 switch.

00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect.
01: Apath = InA (delay is by-passed for A signal path)
Bpath = FED (Falling Edge Delay in B signal path)
10: Apath = RED (Rising Edge Delay in A signal path)
Bpath = InB (delay is by-passed for B signal path)
11: DBM is fully enabled (i.e. both RED and FED active)

Reset type: SYSRSn

18.11.2.33 DBFED Register (Offset = D0h) [Reset = 00000000h]

DBFED is shown in Figure 18-72 and described in Table 18-48.

Return to the Summary Table.

Dead band fall edge delay

Figure 18-72 DBFED Register
313029282726252423222120191817161514131211109876543210
RESERVEDDBFED
R-0-0hR/W-0h
Table 18-48 DBFED Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR-00hReserved
13-0DBFEDR/W0hFalling Edge Delay Count

14-bit counter

Reset type: SYSRSn

18.11.2.34 DBRED Register (Offset = D4h) [Reset = 00000000h]

DBRED is shown in Figure 18-73 and described in Table 18-49.

Return to the Summary Table.

Dead band rise edge delay

Figure 18-73 DBRED Register
313029282726252423222120191817161514131211109876543210
RESERVEDDBRED
R-0-0hR/W-0h
Table 18-49 DBRED Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR-00hReserved
13-0DBREDR/W0hRising Edge Delay Count

14-bit counter

Reset type: SYSRSn

18.11.2.35 DBFEDS Register (Offset = D8h) [Reset = 00000000h]

DBFEDS is shown in Figure 18-74 and described in Table 18-50.

Return to the Summary Table.

Dead band fall edge delay shadow register

Figure 18-74 DBFEDS Register
313029282726252423222120191817161514131211109876543210
RESERVEDDBFEDS
R-0-0hR/W-0h
Table 18-50 DBFEDS Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR-00hReserved
13-0DBFEDSR/W0hDBFED Shadow Register

The value in the DBFEDS register is loaded into DBFED register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.36 DBREDS Register (Offset = DCh) [Reset = 00000000h]

DBREDS is shown in Figure 18-75 and described in Table 18-51.

Return to the Summary Table.

Dead band rise edge delay shadow register

Figure 18-75 DBREDS Register
313029282726252423222120191817161514131211109876543210
RESERVEDDBREDS
R-0-0hR/W-0h
Table 18-51 DBREDS Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR-00hReserved
13-0DBREDSR/W0hDBRED Shadow Register

The value in the DBREDS register is loaded into DBRED register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.37 GLDCTL Register (Offset = F0h) [Reset = 00000000h]

GLDCTL is shown in Figure 18-76 and described in Table 18-52.

Return to the Summary Table.

Global load control register

Figure 18-76 GLDCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDGLDMODERESERVEDOSHTMODEGLD
R-0-0hR/W-0hR-0-0hR/W-0hR/W-0h
Table 18-52 GLDCTL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5-4GLDMODER/W0hSelect global load event

00: CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: CTR = Zero or CTR = PRD
11: GLDOSHTCTL[GFRCLD] - Softwrae load

Reset type: SYSRSn

3-2RESERVEDR-00hReserved
1OSHTMODER/W0hGlobal load one-shot enable

0: Disable global load one-shot
1: Enable global load one-shot

Reset type: SYSRSn

0GLDR/W0hGlobal load enable

0: Disable global load
1: Enable global load

Reset type: SYSRSn

18.11.2.38 GLDOSHTCTL Register (Offset = F4h) [Reset = 00000000h]

GLDOSHTCTL is shown in Figure 18-77 and described in Table 18-53.

Return to the Summary Table.

Global load one shot control register

Figure 18-77 GLDOSHTCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDGFRCLDOSHTCLROSHTLD
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 18-53 GLDOSHTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR-00hReserved
2GFRCLDR-0/W1S0hForce Load Event in One Shot Mode

0: Writing of 0 will be ignored. Always reads back a 0.
1: Force load event. This bit is intended to be used for testing and/or software force loading of the events in global load mode.

Reset type: SYSRSn

1OSHTCLRR-0/W1S0hClear One Shot latch

0: Writing of 0 will be ignored. Always reads back a 0.
1: Turns the one shot latch condition OFF.

Reset type: SYSRSn

0OSHTLDR-0/W1S0hEnable Reload Event in One Shot Mode

0: Writing of 0 will be ignored. Always reads back a 0.
1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe, one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow one load strobe event to pass through and block further strobe events.

Reset type: SYSRSn

18.11.2.39 GLDOSHTSTS Register (Offset = F8h) [Reset = 00000000h]

GLDOSHTSTS is shown in Figure 18-78 and described in Table 18-54.

Return to the Summary Table.

Global load one shot status register

Figure 18-78 GLDOSHTSTS Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDOSHTLATCH
R-0-0hR-0h
Table 18-54 GLDOSHTSTS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0OSHTLATCHR0hOne shot latch output

0: one shot latch condition is OFF.
1: one shot latch condition is ON.

Reset type: SYSRSn

18.11.2.40 PWM1_CMPA Register (Offset = 100h) [Reset = 00000000h]

PWM1_CMPA is shown in Figure 18-79 and described in Table 18-55.

Return to the Summary Table.

PWM1 counter compare A register

Figure 18-79 PWM1_CMPA Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM1_CMPA
R-0-0hR/W-0h
Table 18-55 PWM1_CMPA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM1_CMPAR/W0hPWM1 Compare A register

The value in the PWM1_CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the PWM1 counter-compare module generates a 'time-base counter equal to CMP A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the PWM1A or the PWM1B output depending on the configuration of the PWM1_AQCTLA and PWM1_AQCTLB registers

Shadowing of this register is enabled and disabled by the CMPCTL[PWM1_LOADAMODE] field. By default this register is shadowed.

Reset type: SYSRSn

18.11.2.41 PWM1_CMPAS Register (Offset = 104h) [Reset = 00000000h]

PWM1_CMPAS is shown in Figure 18-80 and described in Table 18-56.

Return to the Summary Table.

PWM1 counter compare A shadow register

Figure 18-80 PWM1_CMPAS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM1_CMPAS
R-0-0hR/W-0h
Table 18-56 PWM1_CMPAS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM1_CMPASR/W0hPWM1 Compare A Shadow Register

The value in the PWM1_CMPAS register is loaded into PWM!_CMPA register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.42 PWM1_CMPB Register (Offset = 108h) [Reset = 00000000h]

PWM1_CMPB is shown in Figure 18-81 and described in Table 18-57.

Return to the Summary Table.

PWM1 counter compare B register

Figure 18-81 PWM1_CMPB Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM1_CMPB
R-0-0hR/W-0h
Table 18-57 PWM1_CMPB Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM1_CMPBR/W0hPWM1 Compare B register

The value in the PWM1_CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the PWM1 counter-compare module generates a 'time-base counter equal to CMP B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the PWM1A or the PWM1B output depending on the configuration of the PWM1_AQCTLA and PWM1_AQCTLB registers

Shadowing of this register is enabled and disabled by the CMPCTL[PWM1_LOADBMODE] field. By default this register is shadowed.

Reset type: SYSRSn

18.11.2.43 PWM1_CMPBS Register (Offset = 10Ch) [Reset = 00000000h]

PWM1_CMPBS is shown in Figure 18-82 and described in Table 18-58.

Return to the Summary Table.

PWM1 counter compare B shadow register

Figure 18-82 PWM1_CMPBS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM1_CMPBS
R-0-0hR/W-0h
Table 18-58 PWM1_CMPBS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM1_CMPBSR/W0hPWM1 Compare B Shadow Register

The value in the PWM1 CMPBS register is loaded into PWM1 CMPB register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.44 PWM1_AQCTLA Register (Offset = 120h) [Reset = 00000000h]

PWM1_AQCTLA is shown in Figure 18-83 and described in Table 18-59.

Return to the Summary Table.

PWM1 action qualifier A register

Figure 18-83 PWM1_AQCTLA Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-59 PWM1_AQCTLA Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM1_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM1_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM1_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM1_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.45 PWM1_AQCTLAS Register (Offset = 124h) [Reset = 00000000h]

PWM1_AQCTLAS is shown in Figure 18-84 and described in Table 18-60.

Return to the Summary Table.

PWM1 action qualifier A shadow register

Figure 18-84 PWM1_AQCTLAS Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-60 PWM1_AQCTLAS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM1_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM1_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM1_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM1_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.46 PWM1_AQCTLB Register (Offset = 128h) [Reset = 00000000h]

PWM1_AQCTLB is shown in Figure 18-85 and described in Table 18-61.

Return to the Summary Table.

PWM1 action qualifier B register

Figure 18-85 PWM1_AQCTLB Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-61 PWM1_AQCTLB Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM1_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM1_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM1_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM1_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.47 PWM1_AQCTLBS Register (Offset = 12Ch) [Reset = 00000000h]

PWM1_AQCTLBS is shown in Figure 18-86 and described in Table 18-62.

Return to the Summary Table.

PWM1 action qualifier B shadow register

Figure 18-86 PWM1_AQCTLBS Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-62 PWM1_AQCTLBS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM1_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM1_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM1_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM1_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.48 PWM1_AQSFRC Register (Offset = 130h) [Reset = 00000000h]

PWM1_AQSFRC is shown in Figure 18-87 and described in Table 18-63.

Return to the Summary Table.

PWM1 action qualifier software force

Figure 18-87 PWM1_AQSFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMBRESERVEDPWMA
R-0-0hR/W-0hR-0-0hR/W-0h
Table 18-63 PWM1_AQSFRC Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR-00hReserved
6-4PWMBR/W0hAction qualifier software force on PWMB

000: Does nothing (softwrae force disabled)
001: Forces a continuous low on output B
010: Forces a continuous high on output B
011: Does nothing (softwrae force disabled)
100: Does nothing (softwrae force disabled)
101: Clear (low) when PWM1_AQOTSFRC[PWMB] = '1'.
110: Set (high) when PWM1_AQOTSFRC[PWMB] = '1'.
111: Toggle (Low -> High, High -> Low) when PWM1_AQOTSFRC[PWMB] = '1'.

Reset type: SYSRSn

3RESERVEDR-00hReserved
2-0PWMAR/W0hAction qualifier software force on PWMA

000: Does nothing (softwrae force disabled)
001: Forces a continuous low on output A
010: Forces a continuous high on output A
011: Does nothing (softwrae force disabled)
100: Does nothing (softwrae force disabled)
101: Clear (low) when PWM1_AQOTSFRC[PWMA] = '1'.
110: Set (high) when PWM1_AQOTSFRC[PWMA] = '1'.
111: Toggle (Low -> High, High -> Low) when PWM1_AQOTSFRC[PWMA] = '1'.

Reset type: SYSRSn

18.11.2.49 PWM1_AQOTSFRC Register (Offset = 134h) [Reset = 00000000h]

PWM1_AQOTSFRC is shown in Figure 18-88 and described in Table 18-64.

Return to the Summary Table.

PWM1 action qualifier one time software force

Figure 18-88 PWM1_AQOTSFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMBRESERVEDPWMA
R-0-0hR-0/W1S-0hR-0-0hR-0/W1S-0h
Table 18-64 PWM1_AQOTSFRC Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR-00hReserved
4PWMBR-0/W1S0hAction qualifier one time software force on PWMB

0: Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on PWMB.
1: Initiates a single software forced event

Reset type: SYSRSn

3-1RESERVEDR-00hReserved
0PWMAR-0/W1S0hAction qualifier one time software force on PWMA

0: Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on PWMA.
1: Initiates a single software forced event

Reset type: SYSRSn

18.11.2.50 PWM2_CMPA Register (Offset = 300h) [Reset = 00000000h]

PWM2_CMPA is shown in Figure 18-89 and described in Table 18-65.

Return to the Summary Table.

PWM2 counter compare A register

Figure 18-89 PWM2_CMPA Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM2_CMPA
R-0-0hR/W-0h
Table 18-65 PWM2_CMPA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM2_CMPAR/W0hPWM2 Compare A register

The value in the PWM2_CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the PWM2 counter-compare module generates a 'time-base counter equal to CMP A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the PWM2A or the PWM2B output depending on the configuration of the PWM2_AQCTLA and PWM2_AQCTLB registers

Shadowing of this register is enabled and disabled by the CMPCTL[PWM2_LOADAMODE] field. By default this register is shadowed.

Reset type: SYSRSn

18.11.2.51 PWM2_CMPAS Register (Offset = 304h) [Reset = 00000000h]

PWM2_CMPAS is shown in Figure 18-90 and described in Table 18-66.

Return to the Summary Table.

PWM2 counter compare A shadow register

Figure 18-90 PWM2_CMPAS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM2_CMPAS
R-0-0hR/W-0h
Table 18-66 PWM2_CMPAS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM2_CMPASR/W0hPWM2 Compare A Shadow Register

The value in the PWM2_CMPAS register is loaded into PWM2_CMPA register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.52 PWM2_CMPB Register (Offset = 308h) [Reset = 00000000h]

PWM2_CMPB is shown in Figure 18-91 and described in Table 18-67.

Return to the Summary Table.

PWM2 counter compare B register

Figure 18-91 PWM2_CMPB Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM2_CMPB
R-0-0hR/W-0h
Table 18-67 PWM2_CMPB Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM2_CMPBR/W0hPWM2 Compare B register

The value in the PWM2_CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the PWM2 counter-compare module generates a 'time-base counter equal to CMP B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the PWM2A or the PWM2B output depending on the configuration of the PWM2_AQCTLA and PWM2_AQCTLB registers

Shadowing of this register is enabled and disabled by the CMPCTL[PWM2_LOADBMODE] field. By default this register is shadowed.

Reset type: SYSRSn

18.11.2.53 PWM2_CMPBS Register (Offset = 30Ch) [Reset = 00000000h]

PWM2_CMPBS is shown in Figure 18-92 and described in Table 18-68.

Return to the Summary Table.

PWM2 counter compare B shadow register

Figure 18-92 PWM2_CMPBS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM2_CMPBS
R-0-0hR/W-0h
Table 18-68 PWM2_CMPBS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM2_CMPBSR/W0hPWM2 Compare B Shadow Register

The value in the PWM2_CMPBS register is loaded into PWM2_CMPB register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.54 PWM2_AQCTLA Register (Offset = 320h) [Reset = 00000000h]

PWM2_AQCTLA is shown in Figure 18-93 and described in Table 18-69.

Return to the Summary Table.

PWM2 action qualifier A register

Figure 18-93 PWM2_AQCTLA Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-69 PWM2_AQCTLA Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM2_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM2_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM2_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM2_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.55 PWM2_AQCTLAS Register (Offset = 324h) [Reset = 00000000h]

PWM2_AQCTLAS is shown in Figure 18-94 and described in Table 18-70.

Return to the Summary Table.

PWM2 action qualifier A shadow register

Figure 18-94 PWM2_AQCTLAS Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-70 PWM2_AQCTLAS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM2_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM2_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM2_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM2_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM2A output low.
10: Set: force PWM2A output high.
11: Toggle PWM2A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.56 PWM2_AQCTLB Register (Offset = 328h) [Reset = 00000000h]

PWM2_AQCTLB is shown in Figure 18-95 and described in Table 18-71.

Return to the Summary Table.

PWM2 action qualifier B register

Figure 18-95 PWM2_AQCTLB Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-71 PWM2_AQCTLB Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM2_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM2_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM2_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM2_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.57 PWM2_AQCTLBS Register (Offset = 32Ch) [Reset = 00000000h]

PWM2_AQCTLBS is shown in Figure 18-96 and described in Table 18-72.

Return to the Summary Table.

PWM2 action qualifier B shadow register

Figure 18-96 PWM2_AQCTLBS Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-72 PWM2_AQCTLBS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM2_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM2_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM2_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM2_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM2B output low.
10: Set: force PWM2B output high.
11: Toggle PWM2B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.58 PWM2_AQSFRC Register (Offset = 330h) [Reset = 00000000h]

PWM2_AQSFRC is shown in Figure 18-97 and described in Table 18-73.

Return to the Summary Table.

PWM2 action qualifier software force

Figure 18-97 PWM2_AQSFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMBRESERVEDPWMA
R-0-0hR/W-0hR-0-0hR/W-0h
Table 18-73 PWM2_AQSFRC Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR-00hReserved
6-4PWMBR/W0hAction qualifier software force on PWMB

000: Does nothing (softwrae force disabled)
001: Forces a continuous low on output B
010: Forces a continuous high on output B
011: Does nothing (softwrae force disabled)
100: Does nothing (softwrae force disabled)
101: Clear (low) when PWM2_AQOTSFRC[PWMB] = '1'.
110: Set (high) when PWM2_AQOTSFRC[PWMB] = '1'.
111: Toggle (Low -> High, High -> Low) when PWM2_AQOTSFRC[PWMB] = '1'.

Reset type: SYSRSn

3RESERVEDR-00hReserved
2-0PWMAR/W0hAction qualifier software force on PWMA

000: Does nothing (softwrae force disabled)
001: Forces a continuous low on output A
010: Forces a continuous high on output A
011: Does nothing (softwrae force disabled)
100: Does nothing (softwrae force disabled)
101: Clear (low) when PWM2_AQOTSFRC[PWMA] = '1'.
110: Set (high) when PWM2_AQOTSFRC[PWMA] = '1'.
111: Toggle (Low -> High, High -> Low) when PWM2_AQOTSFRC[PWMA] = '1'.

Reset type: SYSRSn

18.11.2.59 PWM2_AQOTSFRC Register (Offset = 334h) [Reset = 00000000h]

PWM2_AQOTSFRC is shown in Figure 18-98 and described in Table 18-74.

Return to the Summary Table.

PWM2 action qualifier one time software force

Figure 18-98 PWM2_AQOTSFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMBRESERVEDPWMA
R-0-0hR-0/W1S-0hR-0-0hR-0/W1S-0h
Table 18-74 PWM2_AQOTSFRC Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR-00hReserved
4PWMBR-0/W1S0hAction qualifier one time software force on PWMB

0: Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on PWMB.
1: Initiates a single software forced event

Reset type: SYSRSn

3-1RESERVEDR-00hReserved
0PWMAR-0/W1S0hAction qualifier one time software force on PWMA

0: Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on PWMA.
1: Initiates a single software forced event

Reset type: SYSRSn

18.11.2.60 PWM3_CMPA Register (Offset = 500h) [Reset = 00000000h]

PWM3_CMPA is shown in Figure 18-99 and described in Table 18-75.

Return to the Summary Table.

PWM3 counter compare A register

Figure 18-99 PWM3_CMPA Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM3_CMPA
R-0-0hR/W-0h
Table 18-75 PWM3_CMPA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM3_CMPAR/W0hPWM3 Compare A register

The value in the PWM3_CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the PWM3 counter-compare module generates a 'time-base counter equal to CMP A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the PWM3A or the PWM3B output depending on the configuration of the PWM3_AQCTLA and PWM3_AQCTLB registers

Shadowing of this register is enabled and disabled by the CMPCTL[PWM3_LOADAMODE] field. By default this register is shadowed.

Reset type: SYSRSn

18.11.2.61 PWM3_CMPAS Register (Offset = 504h) [Reset = 00000000h]

PWM3_CMPAS is shown in Figure 18-100 and described in Table 18-76.

Return to the Summary Table.

PWM3 counter compare A shadow register

Figure 18-100 PWM3_CMPAS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM3_CMPAS
R-0-0hR/W-0h
Table 18-76 PWM3_CMPAS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM3_CMPASR/W0hPWM3 Compare A Shadow Register

The value in the PWM3_CMPAS register is loaded into PWM3_CMPA register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.62 PWM3_CMPB Register (Offset = 508h) [Reset = 00000000h]

PWM3_CMPB is shown in Figure 18-101 and described in Table 18-77.

Return to the Summary Table.

PWM3 counter compare B register

Figure 18-101 PWM3_CMPB Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM3_CMPB
R-0-0hR/W-0h
Table 18-77 PWM3_CMPB Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM3_CMPBR/W0hPWM3 Compare B register

The value in the PWM3_CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the PWM3 counter-compare module generates a 'time-base counter equal to CMP B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the PWM3A or the PWM3B output depending on the configuration of the PWM3_AQCTLA and PWM3_AQCTLB registers

Shadowing of this register is enabled and disabled by the CMPCTL[PWM3_LOADBMODE] field. By default this register is shadowed.

Reset type: SYSRSn

18.11.2.63 PWM3_CMPBS Register (Offset = 50Ch) [Reset = 00000000h]

PWM3_CMPBS is shown in Figure 18-102 and described in Table 18-78.

Return to the Summary Table.

PWM3 counter compare B shadow register

Figure 18-102 PWM3_CMPBS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM3_CMPBS
R-0-0hR/W-0h
Table 18-78 PWM3_CMPBS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM3_CMPBSR/W0hPWM3 Compare B Shadow Register

The value in the PWM3 CMPBS register is loaded into PWM3 CMPB register when shadow to active load occurs.

Reset type: SYSRSn

18.11.2.64 PWM3_AQCTLA Register (Offset = 520h) [Reset = 00000000h]

PWM3_AQCTLA is shown in Figure 18-103 and described in Table 18-79.

Return to the Summary Table.

PWM3 action qualifier A register

Figure 18-103 PWM3_AQCTLA Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-79 PWM3_AQCTLA Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM3_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM3_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM3_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM3_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.65 PWM3_AQCTLAS Register (Offset = 524h) [Reset = 00000000h]

PWM3_AQCTLAS is shown in Figure 18-104 and described in Table 18-80.

Return to the Summary Table.

PWM3 action qualifier A shadow register

Figure 18-104 PWM3_AQCTLAS Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-80 PWM3_AQCTLAS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM3_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM3_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM3_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM3_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM3A output low.
10: Set: force PWM3A output high.
11: Toggle PWM3A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.66 PWM3_AQCTLB Register (Offset = 528h) [Reset = 00000000h]

PWM3_AQCTLB is shown in Figure 18-105 and described in Table 18-81.

Return to the Summary Table.

PWM3 action qualifier B register

Figure 18-105 PWM3_AQCTLB Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-81 PWM3_AQCTLB Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM3_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM3_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM3_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM3_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.67 PWM3_AQCTLBS Register (Offset = 52Ch) [Reset = 00000000h]

PWM3_AQCTLBS is shown in Figure 18-106 and described in Table 18-82.

Return to the Summary Table.

PWM3 action qualifier B shadow register

Figure 18-106 PWM3_AQCTLBS Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-82 PWM3_AQCTLBS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM3_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM3_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM3_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM3_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM3B output low.
10: Set: force PWM3B output high.
11: Toggle PWM3B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

18.11.2.68 PWM3_AQSFRC Register (Offset = 530h) [Reset = 00000000h]

PWM3_AQSFRC is shown in Figure 18-107 and described in Table 18-83.

Return to the Summary Table.

PWM3 action qualifier software force

Figure 18-107 PWM3_AQSFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMBRESERVEDPWMA
R-0-0hR/W-0hR-0-0hR/W-0h
Table 18-83 PWM3_AQSFRC Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR-00hReserved
6-4PWMBR/W0hAction qualifier software force on PWMB

000: Does nothing (softwrae force disabled)
001: Forces a continuous low on output B
010: Forces a continuous high on output B
011: Does nothing (softwrae force disabled)
100: Does nothing (softwrae force disabled)
101: Clear (low) when PWM3_AQOTSFRC[PWMB] = '1'.
110: Set (high) when PWM3_AQOTSFRC[PWMB] = '1'.
111: Toggle (Low -> High, High -> Low) when PWM3_AQOTSFRC[PWMB] = '1'.

Reset type: SYSRSn

3RESERVEDR-00hReserved
2-0PWMAR/W0hAction qualifier software force on PWMA

000: Does nothing (softwrae force disabled)
001: Forces a continuous low on output A
010: Forces a continuous high on output A
011: Does nothing (softwrae force disabled)
100: Does nothing (softwrae force disabled)
101: Clear (low) when PWM3_AQOTSFRC[PWMA] = '1'.
110: Set (high) when PWM3_AQOTSFRC[PWMA] = '1'.
111: Toggle (Low -> High, High -> Low) when PWM3_AQOTSFRC[PWMA] = '1'.

Reset type: SYSRSn

18.11.2.69 PWM3_AQOTSFRC Register (Offset = 534h) [Reset = 00000000h]

PWM3_AQOTSFRC is shown in Figure 18-108 and described in Table 18-84.

Return to the Summary Table.

PWM3 action qualifier one time software force

Figure 18-108 PWM3_AQOTSFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMBRESERVEDPWMA
R-0-0hR-0/W1S-0hR-0-0hR-0/W1S-0h
Table 18-84 PWM3_AQOTSFRC Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR-00hReserved
4PWMBR-0/W1S0hAction qualifier one time software force on PWMB

0: Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on PWMB.
1: Initiates a single software forced event

Reset type: SYSRSn

3-1RESERVEDR-00hReserved
0PWMAR-0/W1S0hAction qualifier one time software force on PWMA

0: Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on PWMA.
1: Initiates a single software forced event

Reset type: SYSRSn