SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

26.2.2 MCAN_REGS Registers

Table 26-19 lists the memory-mapped registers for the MCAN_REGS registers. All register offset addresses not listed in Table 26-19 should be considered as reserved locations and the register contents should not be modified.

Table 26-19 MCAN_REGS Registers
OffsetAcronymRegister NameSection
6004hCANRXCAN RX IOGo
6008hCANTXCAN TX IOGo
6204hCANRXFUPDATE version of CANRXGo
6208hCANTXFUPDATE version of CANTXGo
6480hCPU_CONNECT_0CPU ConnectGo
6800hPWRENPower enableGo
6804hRSTCTLReset ControlGo
6814hSTATStatus RegisterGo
7000hMCAN_CRELMCAN Core Release RegisterGo
7004hMCAN_ENDNMCAN Endian RegisterGo
700ChMCAN_DBTPMCAN Data Bit Timing and Prescaler RegisterGo
7010hMCAN_TESTMCAN Test RegisterGo
7014hMCAN_RWDMCAN RAM WatchdogGo
7018hMCAN_CCCRMCAN CC Control RegisterGo
701ChMCAN_NBTPMCAN Nominal Bit Timing and Prescaler RegisterGo
7020hMCAN_TSCCMCAN Timestamp Counter ConfigurationGo
7024hMCAN_TSCVMCAN Timestamp Counter ValueGo
7028hMCAN_TOCCMCAN Timeout Counter ConfigurationGo
702ChMCAN_TOCVMCAN Timeout Counter ValueGo
7040hMCAN_ECRMCAN Error Counter RegisterGo
7044hMCAN_PSRMCAN Protocol Status RegisterGo
7048hMCAN_TDCRMCAN Transmitter Delay Compensation RegisterGo
7050hMCAN_IRMCAN Interrupt RegisterGo
7054hMCAN_IEMCAN Interrupt EnableGo
7058hMCAN_ILSMCAN Interrupt Line SelectGo
705ChMCAN_ILEMCAN Interrupt Line EnableGo
7080hMCAN_GFCMCAN Global Filter ConfigurationGo
7084hMCAN_SIDFCMCAN Standard ID Filter ConfigurationGo
7088hMCAN_XIDFCMCAN Extended ID Filter ConfigurationGo
7090hMCAN_XIDAMMCAN Extended ID and MaskGo
7094hMCAN_HPMSMCAN High Priority Message StatusGo
7098hMCAN_NDAT1MCAN New Data 1Go
709ChMCAN_NDAT2MCAN New Data 2Go
70A0hMCAN_RXF0CMCAN Rx FIFO 0 ConfigurationGo
70A4hMCAN_RXF0SMCAN Rx FIFO 0 StatusGo
70A8hMCAN_RXF0AMCAN Rx FIFO 0 AcknowledgeGo
70AChMCAN_RXBCMCAN Rx Buffer ConfigurationGo
70B0hMCAN_RXF1CMCAN Rx FIFO 1 ConfigurationGo
70B4hMCAN_RXF1SMCAN Rx FIFO 1 StatusGo
70B8hMCAN_RXF1AMCAN Rx FIFO 1 AcknowledgeGo
70BChMCAN_RXESCMCAN Rx Buffer / FIFO Element Size ConfigurationGo
70C0hMCAN_TXBCMCAN Tx Buffer ConfigurationGo
70C4hMCAN_TXFQSMCAN Tx FIFO / Queue StatusGo
70C8hMCAN_TXESCMCAN Tx Buffer Element Size ConfigurationGo
70CChMCAN_TXBRPMCAN Tx Buffer Request PendingGo
70D0hMCAN_TXBARMCAN Tx Buffer Add RequestGo
70D4hMCAN_TXBCRMCAN Tx Buffer Cancellation RequestGo
70D8hMCAN_TXBTOMCAN Tx Buffer Transmission OccurredGo
70DChMCAN_TXBCFMCAN Tx Buffer Cancellation FinishedGo
70E0hMCAN_TXBTIEMCAN Tx Buffer Transmission Interrupt EnableGo
70E4hMCAN_TXBCIEMCAN Tx Buffer Cancellation Finished Interrupt EnableGo
70F0hMCAN_TXEFCMCAN Tx Event FIFO ConfigurationGo
70F4hMCAN_TXEFSMCAN Tx Event FIFO StatusGo
70F8hMCAN_TXEFAMCAN Tx Event FIFO AcknowledgeGo
7200hMCANSS_PIDMCAN Subsystem Revision RegisterGo
7204hMCANSS_CTRLMCAN Subsystem Control RegisterGo
7208hMCANSS_STATMCAN Subsystem Status RegisterGo
720ChMCANSS_ICSMCAN Subsystem Interrupt Clear Shadow RegisterGo
7210hMCANSS_IRSMCAN Subsystem Interrupt Raw Satus RegisterGo
7214hMCANSS_IECSMCAN Subsystem Interrupt Enable Clear Shadow RegisterGo
7218hMCANSS_IEMCAN Subsystem Interrupt Enable RegisterGo
721ChMCANSS_IESMCAN Subsystem Interrupt Enable StatusGo
7220hMCANSS_EOIMCAN Subsystem End of InterruptGo
7224hMCANSS_EXT_TS_PRESCALERMCAN Subsystem External Timestamp Prescaler 0Go
7228hMCANSS_EXT_TS_UNSERVICED_INTR_CNTRMCAN Subsystem External Timestamp Unserviced Interrupts CounterGo
7400hMCANERR_REVMCAN Error Aggregator Revision RegisterGo
7408hMCANERR_VECTORMCAN ECC Vector RegisterGo
740ChMCANERR_STATMCAN Error Misc StatusGo
7410hMCANERR_WRAP_REVMCAN ECC Wrapper Revision RegisterGo
7414hMCANERR_CTRLMCAN ECC ControlGo
7418hMCANERR_ERR_CTRL1MCAN ECC Error Control 1 RegisterGo
741ChMCANERR_ERR_CTRL2MCAN ECC Error Control 2 RegisterGo
7420hMCANERR_ERR_STAT1MCAN ECC Error Status 1 RegisterGo
7424hMCANERR_ERR_STAT2MCAN ECC Error Status 2 RegisterGo
7428hMCANERR_ERR_STAT3MCAN ECC Error Status 3 RegisterGo
743ChMCANERR_SEC_EOIMCAN Single Error Corrected End of Interrupt RegisterGo
7440hMCANERR_SEC_STATUSMCAN Single Error Corrected Interrupt Status RegisterGo
7480hMCANERR_SEC_ENABLE_SETMCAN Single Error Corrected Interrupt Enable Set RegisterGo
74C0hMCANERR_SEC_ENABLE_CLRMCAN Single Error Corrected Interrupt Enable Clear RegisterGo
753ChMCANERR_DED_EOIMCAN Double Error Detected End of Interrupt RegisterGo
7540hMCANERR_DED_STATUSMCAN Double Error Detected Interrupt Status RegisterGo
7580hMCANERR_DED_ENABLE_SETMCAN Double Error Detected Interrupt Enable Set RegisterGo
75C0hMCANERR_DED_ENABLE_CLRMCAN Double Error Detected Interrupt Enable Clear RegisterGo
7600hMCANERR_AGGR_ENABLE_SETMCAN Error Aggregator Enable Set RegisterGo
7604hMCANERR_AGGR_ENABLE_CLRMCAN Error Aggregator Enable Clear RegisterGo
7608hMCANERR_AGGR_STATUS_SETMCAN Error Aggregator Status Set RegisterGo
760ChMCANERR_AGGR_STATUS_CLRMCAN Error Aggregator Status Clear RegisterGo
7820hIIDXInterrupt Index RegisterGo
7828hIMASKInterrupt maskGo
7830hRISRaw interrupt statusGo
7838hMISMasked interrupt statusGo
7840hISETInterrupt setGo
7848hICLRInterrupt clearGo
78E0hEVT_MODEEvent ModeGo
78FChDESCModule DescriptionGo
7900hMCANSS_CLKENMCAN module clock enableGo
7904hMCANSS_CLKDIVClock dividerGo
7908hMCANSS_CLKCTLMCAN-SS clock stop control registerGo
790ChMCANSS_CLKSTSMCANSS clock stop status registerGo

Complex bit access types are encoded to fit into small table cells. Table 26-20 shows the codes that are used for access types in this section.

Table 26-20 MCAN_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
RCR
C		Read
to Clear
RSR
S		Read
to Set
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
W1SQW
1S
Q		Write
1 to set
Qualified. A condition must be met for this operation to occur.
WDW
D		Write
Decrement. Decrements the specified bit field by the amount written.
WIW
I		Write
Increment. Increments the specified bit field by the amount written.
WKW
K		Write
Write protected by a key
WQW
Q		Write
Qualified. A condition must be met for this operation to occur.
Reset or Default Value
-nValue after reset or the default value

26.2.2.1 CANRX Register (Offset = 6004h) [Reset = 00000000h]

CANRX is shown in Figure 26-27 and described in Table 26-21.

Return to the Summary Table.

CAN RX IO

Figure 26-27 CANRX Register
3130292827262524
RESERVEDGFLTSLEWWCOMPWUENINVHIGHZ1HIGHZ0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDDRVHYSTENINENAPIPUPIPD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GSTATERESERVED
R/W-0hR/W-0h
76543210
PSTATERESERVED
R/W-0hR/W-0h
Table 26-21 CANRX Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h
30GFLTR/W0hGlitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29SLEWR/W0hReserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28WCOMPR/W0hWake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27WUENR/W0hWake up enable
0h = Wake up not enabled
1h = Wake up enabled
26INVR/W0hInvert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25HIGHZ1R/W0hHigh-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24HIGHZ0R/W0hHigh-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23RESERVEDR/W0h
22-20DRVR/W0hDrive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19HYSTENR/W0hHysteresis enable
0h = No hysteresis
1h = Hysteresis on
18INENAR/W0hInput enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17PIPUR/W0hPull up enable
0h = No pull up
1h = Pull up
16PIPDR/W0hPull down enable
0h = No pull down
1h = Pull down
15-14GSTATER/W0hGPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8RESERVEDR/W0h
7-6PSTATER/W0hPeripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0RESERVEDR/W0h

26.2.2.2 CANTX Register (Offset = 6008h) [Reset = 00000000h]

CANTX is shown in Figure 26-28 and described in Table 26-22.

Return to the Summary Table.

CAN TX IO

Figure 26-28 CANTX Register
3130292827262524
RESERVEDGFLTSLEWWCOMPWUENINVHIGHZ1HIGHZ0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDDRVHYSTENINENAPIPUPIPD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GSTATERESERVED
R/W-0hR/W-0h
76543210
PSTATERESERVED
R/W-0hR/W-0h
Table 26-22 CANTX Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h
30GFLTR/W0hGlitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29SLEWR/W0hReserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28WCOMPR/W0hWake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27WUENR/W0hWake up enable
0h = Wake up not enabled
1h = Wake up enabled
26INVR/W0hInvert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25HIGHZ1R/W0hHigh-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24HIGHZ0R/W0hHigh-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23RESERVEDR/W0h
22-20DRVR/W0hDrive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19HYSTENR/W0hHysteresis enable
0h = No hysteresis
1h = Hysteresis on
18INENAR/W0hInput enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17PIPUR/W0hPull up enable
0h = No pull up
1h = Pull up
16PIPDR/W0hPull down enable
0h = No pull down
1h = Pull down
15-14GSTATER/W0hGPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8RESERVEDR/W0h
7-6PSTATER/W0hPeripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0RESERVEDR/W0h

26.2.2.3 CANRX Register (Offset = 6204h) [Reset = 00000000h]

CANRX is shown in Figure 26-29 and described in Table 26-23.

Return to the Summary Table.

FUPDATE version of CANRX

Figure 26-29 CANRX Register
3130292827262524
RESERVEDIOADDR
R/W-0hW-0h
2322212019181716
IOADDR
W-0h
15141312111098
IOADDR
W-0h
76543210
IOADDRLOCKGSEL
W-0hW-0hW-0h
Table 26-23 CANRX Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0h
27-2IOADDRW0hIO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the "Full Write" subregion of the pinmux subregion.
1LOCKW0hSets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0GSELW0hGPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update

0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

26.2.2.4 CANTX Register (Offset = 6208h) [Reset = 00000000h]

CANTX is shown in Figure 26-30 and described in Table 26-24.

Return to the Summary Table.

FUPDATE version of CANTX

Figure 26-30 CANTX Register
3130292827262524
RESERVEDIOADDR
R/W-0hW-0h
2322212019181716
IOADDR
W-0h
15141312111098
IOADDR
W-0h
76543210
IOADDRLOCKGSEL
W-0hW-0hW-0h
Table 26-24 CANTX Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0h
27-2IOADDRW0hIO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the "Full Write" subregion of the pinmux subregion.
1LOCKW0hSets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0GSELW0hGPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update

0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

26.2.2.5 CPU_CONNECT_0 Register (Offset = 6480h) [Reset = 00000000h]

CPU_CONNECT_0 is shown in Figure 26-31 and described in Table 26-25.

Return to the Summary Table.

Directly connect peripheral publisher port to application processor

Figure 26-31 CPU_CONNECT_0 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
Table 26-25 CPU_CONNECT_0 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1RESERVEDR/W0hReserved
0RESERVEDR/W0h

26.2.2.6 PWREN Register (Offset = 6800h) [Reset = 00000000h]

PWREN is shown in Figure 26-32 and described in Table 26-26.

Return to the Summary Table.

Register to control the power state

Figure 26-32 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE
R/W-0hR/WK-0h
Table 26-26 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR/W0h
0ENABLER/WK0hEnable the power

[EXT_GPRCM.PWREN.KEY] must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

26.2.2.7 RSTCTL Register (Offset = 6804h) [Reset = 00000000h]

RSTCTL is shown in Figure 26-33 and described in Table 26-27.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 26-33 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-0hWK-0hWK-0h
Table 26-27 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDW0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

[EXT_GPRCM.RSTCTL.KEY] must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

[EXT_GPRCM.RSTCTL.KEY] must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

26.2.2.8 STAT Register (Offset = 6814h) [Reset = 00000000h]

STAT is shown in Figure 26-34 and described in Table 26-28.

Return to the Summary Table.

peripheral enable and reset status

Figure 26-34 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 26-28 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

26.2.2.9 MCAN_CREL Register (Offset = 7000h) [Reset = 32380608h]

MCAN_CREL is shown in Figure 26-35 and described in Table 26-29.

Return to the Summary Table.

MCAN Core Release Register

Figure 26-35 MCAN_CREL Register
31302928272625242322212019181716
RELSTEPSUBSTEPYEAR
R-3hR-2hR-3hR-8h
1514131211109876543210
MONDAY
R-6hR-8h
Table 26-29 MCAN_CREL Register Field Descriptions
BitFieldTypeResetDescription
31-28RELR3hCore Release. One digit, BCD-coded.
27-24STEPR2hStep of Core Release. One digit, BCD-coded.
23-20SUBSTEPR3hSub-Step of Core Release. One digit, BCD-coded.
19-16YEARR8hTime Stamp Year. One digit, BCD-coded.
15-8MONR6hTime Stamp Month. Two digits, BCD-coded.
7-0DAYR8hTime Stamp Day. Two digits, BCD-coded.

26.2.2.10 MCAN_ENDN Register (Offset = 7004h) [Reset = 87654321h]

MCAN_ENDN is shown in Figure 26-36 and described in Table 26-30.

Return to the Summary Table.

MCAN Endian Register

Figure 26-36 MCAN_ENDN Register
313029282726252423222120191817161514131211109876543210
ETV
R-87654321h
Table 26-30 MCAN_ENDN Register Field Descriptions
BitFieldTypeResetDescription
31-0ETVR87654321hEndianess Test Value. Reading the constant value maintained in this register allows software to determine the endianess of the host CPU.

26.2.2.11 MCAN_DBTP Register (Offset = 700Ch) [Reset = 00000A33h]

MCAN_DBTP is shown in Figure 26-37 and described in Table 26-31.

Return to the Summary Table.

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 m_can_cclk periods. tq = (DBRP + 1) mtq.

DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2.

Therefore the length of the bit time is (programmed values) (DTSEG1 + DTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq.

The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Figure 26-37 MCAN_DBTP Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
TDCRESERVEDDBRP
R/WQ-0hR/W-0hR/WQ-0h
15141312111098
RESERVEDDTSEG1
R/W-0hR/WQ-Ah
76543210
DTSEG2DSJW
R/WQ-3hR/WQ-3h
Table 26-31 MCAN_DBTP Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0h
23TDCR/WQ0hTransmitter Delay Compensation
0 Transmitter Delay Compensation disabled
1 Transmitter Delay Compensation enabled
22-21RESERVEDR/W0h
20-16DBRPR/WQ0hData Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-13RESERVEDR/W0h
12-8DTSEG1R/WQAhData Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7-4DTSEG2R/WQ3hData Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-0DSJWR/WQ3hData Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.12 MCAN_TEST Register (Offset = 7010h) [Reset = 000000X0h]

MCAN_TEST is shown in Figure 26-38 and described in Table 26-32.

Return to the Summary Table.

Write access to the Test Register has to be enabled by setting bit CCCR.TEST to '1'. All Test Register functions are set to their reset values when bit CCCR.TEST is reset.

Loop Back Mode and software control of the internal CAN TX pin are hardware test modes.

Figure 26-38 MCAN_TEST Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RXTXLBCKRESERVED
R-XhR/WQ-0hR/WQ-0hR/W-0h
Table 26-32 MCAN_TEST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7RXRXhReceive Pin. Monitors the actual value of the CAN receive pin.
0h = DOMINANT : The CAN bus is dominant (CAN RX pin = '0')
1h = RECESSIVE : The CAN bus is recessive (CAN RX pin = '1')
6-5TXR/WQ0hControl of Transmit Pin
00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time
01 Sample Point can be monitored at CAN TX pin
10 Dominant ('0') level at CAN TX pin
11 Recessive ('1') at CAN TX pin

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
4LBCKR/WQ0hLoop Back Mode. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0h = DISABLE : Reset value, Loop Back Mode is disabled
1h = ENABLE : Loop Back Mode is enabled
3-0RESERVEDR/W0h

26.2.2.13 MCAN_RWD Register (Offset = 7014h) [Reset = 00000000h]

MCAN_RWD is shown in Figure 26-39 and described in Table 26-33.

Return to the Summary Table.

MCAN RAM Watchdog

Figure 26-39 MCAN_RWD Register
313029282726252423222120191817161514131211109876543210
RESERVEDWDVWDC
R/W-0hR-0hR/WQ-0h
Table 26-33 MCAN_RWD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-8WDVR0hWatchdog Value. Acutal Message RAM Watchdog Counter Value.

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock.
7-0WDCR/WQ0hWatchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.14 MCAN_CCCR Register (Offset = 7018h) [Reset = 00000001h]

MCAN_CCCR is shown in Figure 26-40 and described in Table 26-34.

Return to the Summary Table.

MCAN CC Control Register

Figure 26-40 MCAN_CCCR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
NISOTXPEFBIPXHDRESERVEDBRSEFDOE
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/W-0hR/WQ-0hR/WQ-0h
76543210
TESTDARMONCSRCSAASMCCEINIT
R/W1SQ-0hR/WQ-0hR/W1SQ-0hR/W-0hR-0hR/W1SQ-0hR/WQ-0hR/W-1h
Table 26-34 MCAN_CCCR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15NISOR/WQ0hNon ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
0 CAN FD frame format according to ISO 11898-1:2015
1 CAN FD frame format according to Bosch CAN FD Specification V1.0
14TXPR/WQ0hTransmit Pause. If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame.
0 Transmit pause disabled
1 Transmit pause enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
13EFBIR/WQ0hEdge Filtering during Bus Integration
0 Edge filtering disabled
1 Two consecutive dominant tq required to detect an edge for hard synchronization

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
12PXHDR/WQ0hProtocol Exception Handling Disable
0 Protocol exception handling enabled
1 Protocol exception handling disabled
Note: When protocol exception handling is disabled, the MCAN will transmit an error frame when it detects a protocol exception condition.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
11-10RESERVEDR/W0h
9BRSER/WQ0hBit Rate Switch Enable
0 Bit rate switching for transmissions disabled
1 Bit rate switching for transmissions enabled
Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
8FDOER/WQ0hFlexible Datarate Operation Enable
0 FD operation disabled
1 FD operation enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7TESTR/W1SQ0hTest Mode Enable
0 Normal operation, register TEST holds reset values
1 Test Mode, write access to register TEST enabled

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
6DARR/WQ0hDisable Automatic Retransmission
0 Automatic retransmission of messages not transmitted successfully enabled
1 Automatic retransmission disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
5MONR/W1SQ0hBus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.
0 Bus Monitoring Mode is disabled
1 Bus Monitoring Mode is enabled

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
4CSRR/W0hClock Stop Request
0 No clock stop is requested
1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle.
3CSAR0hClock Stop Acknowledge
0 No clock stop acknowledged
1 MCAN may be set in power down by stopping the Host and CAN clocks
2ASMR/W1SQ0hRestricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.
0 Normal CAN operation
1 Restricted Operation Mode active

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1CCER/WQ0hConfiguration Change Enable
0 The CPU has no write access to the protected configuration registers
1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1')

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0INITR/W1hInitialization
0 Normal Operation
1 Initialization is started
Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.

26.2.2.15 MCAN_NBTP Register (Offset = 701Ch) [Reset = 06000A03h]

MCAN_NBTP is shown in Figure 26-41 and described in Table 26-35.

Return to the Summary Table.

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 m_can_cclk periods. tq = (NBRP + 1) mtq.

NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2.

Therefore the length of the bit time is (programmed values) (NTSEG1 + NTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq.

The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Note: With a CAN clock of 8 MHz, the reset value of 0x06000A03 configures the MCAN for a bit rate of 500 kBit/s.

Figure 26-41 MCAN_NBTP Register
3130292827262524
NSJWNBRP
R/WQ-3hR/WQ-0h
2322212019181716
NBRP
R/WQ-0h
15141312111098
NTSEG1
R/WQ-Ah
76543210
RESERVEDNTSEG2
R/W-0hR/WQ-3h
Table 26-35 MCAN_NBTP Register Field Descriptions
BitFieldTypeResetDescription
31-25NSJWR/WQ3hNominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
24-16NBRPR/WQ0hNominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-8NTSEG1R/WQAhNominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7RESERVEDR/W0h
6-0NTSEG2R/WQ3hNominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.16 MCAN_TSCC Register (Offset = 7020h) [Reset = 00000000h]

MCAN_TSCC is shown in Figure 26-42 and described in Table 26-36.

Return to the Summary Table.

MCAN Timestamp Counter Configuration

Figure 26-42 MCAN_TSCC Register
31302928272625242322212019181716
RESERVEDTCP
R/W-0hR/WQ-0h
1514131211109876543210
RESERVEDTSS
R/W-0hR/WQ-0h
Table 26-36 MCAN_TSCC Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
19-16TCPR/WQ0hTimestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Note: With CAN FD an external counter is required for timestamp generation (TSS = "10").

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2RESERVEDR/W0h
1-0TSSR/WQ0hTimestamp Select
00 Timestamp counter value always 0x0000
01 Timestamp counter value incremented according to TCP
10 External timestamp counter value used
11 Same as "00"

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.17 MCAN_TSCV Register (Offset = 7024h) [Reset = 00000000h]

MCAN_TSCV is shown in Figure 26-43 and described in Table 26-37.

Return to the Summary Table.

MCAN Timestamp Counter Value

Figure 26-43 MCAN_TSCV Register
313029282726252423222120191817161514131211109876543210
RESERVEDTSC
R/W-0hR/W-0h
Table 26-37 MCAN_TSCV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0TSCR/W0hTimestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01", the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = "10", TSC reflects the External Timestamp Counter value, and a write access has no impact.

Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not
caused by write access to MCAN_TSCV.

26.2.2.18 MCAN_TOCC Register (Offset = 7028h) [Reset = FFFF0000h]

MCAN_TOCC is shown in Figure 26-44 and described in Table 26-38.

Return to the Summary Table.

MCAN Timeout Counter Configuration

Figure 26-44 MCAN_TOCC Register
3130292827262524
TOP
R/WQ-FFFFh
2322212019181716
TOP
R/WQ-FFFFh
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDTOSETOC
R/W-0hR/WQ-0hR/WQ-0h
Table 26-38 MCAN_TOCC Register Field Descriptions
BitFieldTypeResetDescription
31-16TOPR/WQFFFFhTimeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-3RESERVEDR/W0h
2-1TOSR/WQ0hTimeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored.
00 Continuous operation
01 Timeout controlled by Tx Event FIFO
10 Timeout controlled by Rx FIFO 0
11 Timeout controlled by Rx FIFO 1

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0ETOCR/WQ0hEnable Timeout Counter
0 Timeout Counter disabled
1 Timeout Counter enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.19 MCAN_TOCV Register (Offset = 702Ch) [Reset = 0000FFFFh]

MCAN_TOCV is shown in Figure 26-45 and described in Table 26-39.

Return to the Summary Table.

MCAN Timeout Counter Value

Figure 26-45 MCAN_TOCV Register
313029282726252423222120191817161514131211109876543210
RESERVEDTOC
R/W-0hR/W-FFFFh
Table 26-39 MCAN_TOCV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0TOCR/WFFFFhTimeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.

26.2.2.20 MCAN_ECR Register (Offset = 7040h) [Reset = 00000000h]

MCAN_ECR is shown in Figure 26-46 and described in Table 26-40.

Return to the Summary Table.

MCAN Error Counter Register

Figure 26-46 MCAN_ECR Register
31302928272625242322212019181716
RESERVEDCEL
R-0hRC-0h
1514131211109876543210
RPRECTEC
R-0hR-0hR-0h
Table 26-40 MCAN_ECR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23-16CELRC0hCAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF
the next increment of TEC or REC sets interrupt flag IR.ELO.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
15RPR0hReceive Error Passive
0 The Receive Error Counter is below the error passive level of 128
1 The Receive Error Counter has reached the error passive level of 128
14-8RECR0hReceive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
7-0TECR0hTransmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

26.2.2.21 MCAN_PSR Register (Offset = 7044h) [Reset = 00000707h]

MCAN_PSR is shown in Figure 26-47 and described in Table 26-41.

Return to the Summary Table.

MCAN Protocol Status Register

Figure 26-47 MCAN_PSR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTDCV
R-0hR-0h
15141312111098
RESERVEDPXERFDFRBRSRESIDLEC
R-0hRC-0hRC-0hRC-0hRC-0hRS-7h
76543210
BOEWEPACTLEC
R-0hR-0hR-0hR-0hRS-7h
Table 26-41 MCAN_PSR Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h
22-16TDCVR0hTransmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.
15RESERVEDR0h
14PXERC0hProtocol Exception Event
0 No protocol exception event occurred since last read access
1 Protocol exception event occurred
13RFDFRC0hReceived a CAN FD Message. This bit is set independent of acceptance filtering.
0 Since this bit was reset by the CPU, no CAN FD message has been received
1 Message in CAN FD format with FDF flag set has been received
12RBRSRC0hBRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.
0 Last received CAN FD message did not have its BRS flag set
1 Last received CAN FD message had its BRS flag set
11RESIRC0hESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.
0 Last received CAN FD message did not have its ESI flag set
1 Last received CAN FD message had its ESI flag set
10-8DLECRS7hData Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
7BOR0hBus_Off Status
0 The M_CAN is not Bus_Off
1 The M_CAN is in Bus_Off state
6EWR0hWarning Status
0 Both error counters are below the Error_Warning limit of 96
1 At least one of error counter has reached the Error_Warning limit of 96
5EPR0hError Passive
0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
1 The M_CAN is in the Error_Passive state
4-3ACTR0hNode Activity. Monitors the module's CAN communication state.
00 Synchronizing - node is synchronizing on CAN communication
01 Idle - node is neither receiver nor transmitter
10 Receiver - node is operating as receiver
11 Transmitter - node is operating as transmitter

Note: ACT is set to "00" by a Protocol Exception Event.
2-0LECRS7hLast Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
0 No Error: No error occurred since LEC has been reset by successful reception or transmission.
1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
2 Form Error: A fixed format part of a received frame has the wrong format.
3 AckError: The message transmitted by the MCAN was not acknowledged by another node.
4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.
5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register.

Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.

26.2.2.22 MCAN_TDCR Register (Offset = 7048h) [Reset = 00000000h]

MCAN_TDCR is shown in Figure 26-48 and described in Table 26-42.

Return to the Summary Table.

MCAN Transmitter Delay Compensation Register

Figure 26-48 MCAN_TDCR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDTDCO
R/W-0hR/WQ-0h
76543210
RESERVEDTDCF
R/W-0hR/WQ-0h
Table 26-42 MCAN_TDCR Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W0h
14-8TDCOR/WQ0hTransmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7RESERVEDR/W0h
6-0TDCFR/WQ0hTransmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.23 MCAN_IR Register (Offset = 7050h) [Reset = 80000000h]

MCAN_IR is shown in Figure 26-49 and described in Table 26-43.

Return to the Summary Table.

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signalled.

Figure 26-49 MCAN_IR Register
3130292827262524
RESERVEDARAPEDPEAWDIBOEW
R/W-2hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
2322212019181716
EPELOBEURESERVEDDRXTOOMRAFTSW
R/W1C-0hR/W1C-0hR/W1C-0hR/W-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
TEFLTEFFTEFWTEFNTFETCFTCHPM
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
RF1LRF1FRF1WRF1NRF0LRF0FRF0WRF0N
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 26-43 MCAN_IR Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W2h
29ARAR/W1C0hAccess to Reserved Address
0 No access to reserved address occurred
1 Access to reserved address occurred
28PEDR/W1C0hProtocol Error in Data Phase (Data Bit Time is used)
0 No protocol error in data phase
1 Protocol error in data phase detected (PSR.DLEC ? 0,7)
27PEAR/W1C0hProtocol Error in Arbitration Phase (Nominal Bit Time is used)
0 No protocol error in arbitration phase
1 Protocol error in arbitration phase detected (PSR.LEC ? 0,7)
26WDIR/W1C0hWatchdog Interrupt
0 No Message RAM Watchdog event occurred
1 Message RAM Watchdog event due to missing READY
25BOR/W1C0hBus_Off Status
0 Bus_Off status unchanged
1 Bus_Off status changed
24EWR/W1C0hWarning Status
0 Error_Warning status unchanged
1 Error_Warning status changed
23EPR/W1C0hError Passive
0 Error_Passive status unchanged
1 Error_Passive status changed
22ELOR/W1C0hError Logging Overflow
0 CAN Error Logging Counter did not overflow
1 Overflow of CAN Error Logging Counter occurred
21BEUR/W1C0hBit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data.
0 No bit error detected when reading from Message RAM
1 Bit error detected, uncorrected (e.g. parity logic)
20RESERVEDR/W0h
19DRXR/W1C0hMessage Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
0 No Rx Buffer updated
1 At least one received message stored into an Rx Buffer
18TOOR/W1C0hTimeout Occurred
0 No timeout
1 Timeout reached
17MRAFR/W1C0hMessage RAM Access Failure. The flag is set, when the Rx Handler:
- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
- was not able to write a message to the Message RAM. In this case message storage is aborted.

In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.

The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM.
0 No Message RAM access failure occurred
1 Message RAM access failure occurred
16TSWR/W1C0hTimestamp Wraparound
0 No timestamp counter wrap-around
1 Timestamp counter wrapped around
15TEFLR/W1C0hTx Event FIFO Element Lost
0 No Tx Event FIFO element lost
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
14TEFFR/W1C0hTx Event FIFO Full
0 Tx Event FIFO not full
1 Tx Event FIFO full
13TEFWR/W1C0hTx Event FIFO Watermark Reached
0 Tx Event FIFO fill level below watermark
1 Tx Event FIFO fill level reached watermark
12TEFNR/W1C0hTx Event FIFO New Entry
0 Tx Event FIFO unchanged
1 Tx Handler wrote Tx Event FIFO element
11TFER/W1C0hTx FIFO Empty
0 Tx FIFO non-empty
1 Tx FIFO empty
10TCFR/W1C0hTransmission Cancellation Finished
0 No transmission cancellation finished
1 Transmission cancellation finished
9TCR/W1C0hTransmission Completed
0 No transmission completed
1 Transmission completed
8HPMR/W1C0hHigh Priority Message
0 No high priority message received
1 High priority message received
7RF1LR/W1C0hRx FIFO 1 Message Lost
0 No Rx FIFO 1 message lost
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
6RF1FR/W1C0hRx FIFO 1 Full
0 Rx FIFO 1 not full
1 Rx FIFO 1 full
5RF1WR/W1C0hRx FIFO 1 Watermark Reached
0 Rx FIFO 1 fill level below watermark
1 Rx FIFO 1 fill level reached watermark
4RF1NR/W1C0hRx FIFO 1 New Message
0 No new message written to Rx FIFO 1
1 New message written to Rx FIFO 1
3RF0LR/W1C0hRx FIFO 0 Message Lost
0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
2RF0FR/W1C0hRx FIFO 0 Full
0 Rx FIFO 0 not full
1 Rx FIFO 0 full
1RF0WR/W1C0hRx FIFO 0 Watermark Reached
0 Rx FIFO 0 fill level below watermark
1 Rx FIFO 0 fill level reached watermark
0RF0NR/W1C0hRx FIFO 0 New Message
0 No new message written to Rx FIFO 0
1 New message written to Rx FIFO 0

26.2.2.24 MCAN_IE Register (Offset = 7054h) [Reset = 00000000h]

MCAN_IE is shown in Figure 26-50 and described in Table 26-44.

Return to the Summary Table.

MCAN Interrupt Enable

Figure 26-50 MCAN_IE Register
3130292827262524
RESERVEDARAEPEDEPEAEWDIEBOEEWE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
EPEELOEBEUEBECEDRXETOOEMRAFETSWE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TEFLETEFFETEFWETEFNETFEETCFETCEHPME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RF1LERF1FERF1WERF1NERF0LERF0FERF0WERF0NE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 26-44 MCAN_IE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29ARAER/W0hAccess to Reserved Address Enable
28PEDER/W0hProtocol Error in Data Phase Enable
27PEAER/W0hProtocol Error in Arbitration Phase Enable
26WDIER/W0hWatchdog Interrupt Enable
25BOER/W0hBus_Off Status Enable
24EWER/W0hWarning Status Enable
23EPER/W0hError Passive Enable
22ELOER/W0hError Logging Overflow Enable
21BEUER/W0hBit Error Uncorrected Enable
20BECER/W0hBit Error Corrected Enable

A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave this bit cleared to '0'.
19DRXER/W0hMessage Stored to Dedicated Rx Buffer Enable
18TOOER/W0hTimeout Occurred Enable
17MRAFER/W0hMessage RAM Access Failure Enable
16TSWER/W0hTimestamp Wraparound Enable
15TEFLER/W0hTx Event FIFO Element Lost Enable
14TEFFER/W0hTx Event FIFO Full Enable
13TEFWER/W0hTx Event FIFO Watermark Reached Enable
12TEFNER/W0hTx Event FIFO New Entry Enable
11TFEER/W0hTx FIFO Empty Enable
10TCFER/W0hTransmission Cancellation Finished Enable
9TCER/W0hTransmission Completed Enable
8HPMER/W0hHigh Priority Message Enable
7RF1LER/W0hRx FIFO 1 Message Lost Enable
6RF1FER/W0hRx FIFO 1 Full Enable
5RF1WER/W0hRx FIFO 1 Watermark Reached Enable
4RF1NER/W0hRx FIFO 1 New Message Enable
3RF0LER/W0hRx FIFO 0 Message Lost Enable
2RF0FER/W0hRx FIFO 0 Full Enable
1RF0WER/W0hRx FIFO 0 Watermark Reached Enable
0RF0NER/W0hRx FIFO 0 New Message Enable

26.2.2.25 MCAN_ILS Register (Offset = 7058h) [Reset = 00000000h]

MCAN_ILS is shown in Figure 26-51 and described in Table 26-45.

Return to the Summary Table.

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1.

Figure 26-51 MCAN_ILS Register
3130292827262524
RESERVEDARALPEDLPEALWDILBOLEWL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
EPLELOLBEULBECLDRXLTOOLMRAFLTSWL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TEFLLTEFFLTEFWLTEFNLTFELTCFLTCLHPML
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RF1LLRF1FLRF1WLRF1NLRF0LLRF0FLRF0WLRF0NL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 26-45 MCAN_ILS Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29ARALR/W0hAccess to Reserved Address Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
28PEDLR/W0hProtocol Error in Data Phase Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
27PEALR/W0hProtocol Error in Arbitration Phase Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
26WDILR/W0hWatchdog Interrupt Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
25BOLR/W0hBus_Off Status Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
24EWLR/W0hWarning Status Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
23EPLR/W0hError Passive Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
22ELOLR/W0hError Logging Overflow Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
21BEULR/W0hBit Error Uncorrected Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
20BECLR/W0hBit Error Corrected Line

A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave the MCAN_IE.BECE bit cleared to '0' (disabled), thereby relegating this bit to not applicable.
19DRXLR/W0hMessage Stored to Dedicated Rx Buffer Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
18TOOLR/W0hTimeout Occurred Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
17MRAFLR/W0hMessage RAM Access Failure Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
16TSWLR/W0hTimestamp Wraparound Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
15TEFLLR/W0hTx Event FIFO Element Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
14TEFFLR/W0hTx Event FIFO Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
13TEFWLR/W0hTx Event FIFO Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
12TEFNLR/W0hTx Event FIFO New Entry Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
11TFELR/W0hTx FIFO Empty Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
10TCFLR/W0hTransmission Cancellation Finished Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
9TCLR/W0hTransmission Completed Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
8HPMLR/W0hHigh Priority Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
7RF1LLR/W0hRx FIFO 1 Message Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
6RF1FLR/W0hRx FIFO 1 Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
5RF1WLR/W0hRx FIFO 1 Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
4RF1NLR/W0hRx FIFO 1 New Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
3RF0LLR/W0hRx FIFO 0 Message Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
2RF0FLR/W0hRx FIFO 0 Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
1RF0WLR/W0hRx FIFO 0 Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
0RF0NLR/W0hRx FIFO 0 New Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

26.2.2.26 MCAN_ILE Register (Offset = 705Ch) [Reset = 00000000h]

MCAN_ILE is shown in Figure 26-52 and described in Table 26-46.

Return to the Summary Table.

MCAN Interrupt Line Enable

Figure 26-52 MCAN_ILE Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEINT1EINT0
R/W-0hR/W-0hR/W-0h
Table 26-46 MCAN_ILE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1EINT1R/W0hEnable Interrupt Line 1
0 Interrupt Line 1 is disabled
1 Interrupt Line 1 is enabled
0EINT0R/W0hEnable Interrupt Line 0
0 Interrupt Line 0 is disabled
1 Interrupt Line 0 is enabled

26.2.2.27 MCAN_GFC Register (Offset = 7080h) [Reset = 00000000h]

MCAN_GFC is shown in Figure 26-53 and described in Table 26-47.

Return to the Summary Table.

MCAN Global Filter Configuration

Figure 26-53 MCAN_GFC Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDANFSANFERRFSRRFE
R/W-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
Table 26-47 MCAN_GFC Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-4ANFSR/WQ0hAccept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated.
00 Accept in Rx FIFO 0
01 Accept in Rx FIFO 1
10 Reject
11 Reject

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-2ANFER/WQ0hAccept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated.
00 Accept in Rx FIFO 0
01 Accept in Rx FIFO 1
10 Reject
11 Reject

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1RRFSR/WQ0hReject Remote Frames Standard
0 Filter remote frames with 11-bit standard IDs
1 Reject all remote frames with 11-bit standard IDs

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0RRFER/WQ0hReject Remote Frames Extended
0 Filter remote frames with 29-bit extended IDs
1 Reject all remote frames with 29-bit extended IDs

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.28 MCAN_SIDFC Register (Offset = 7084h) [Reset = 00000000h]

MCAN_SIDFC is shown in Figure 26-54 and described in Table 26-48.

Return to the Summary Table.

MCAN Standard ID Filter Configuration

Figure 26-54 MCAN_SIDFC Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
LSS
R/WQ-0h
15141312111098
FLSSA
R/WQ-0h
76543210
FLSSARESERVED
R/WQ-0hR/W-0h
Table 26-48 MCAN_SIDFC Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0h
23-16LSSR/WQ0hList Size Standard
0 No standard Message ID filter
1-128 Number of standard Message ID filter elements
>128 Values greater than 128 are interpreted as 128
15-2FLSSAR/WQ0hFilter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address).
1-0RESERVEDR/W0h

26.2.2.29 MCAN_XIDFC Register (Offset = 7088h) [Reset = 00000000h]

MCAN_XIDFC is shown in Figure 26-55 and described in Table 26-49.

Return to the Summary Table.

MCAN Extended ID Filter Configuration

Figure 26-55 MCAN_XIDFC Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDLSE
R/W-0hR/WQ-0h
15141312111098
FLESA
R/WQ-0h
76543210
FLESARESERVED
R/WQ-0hR/W-0h
Table 26-49 MCAN_XIDFC Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W0h
22-16LSER/WQ0hFilter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2FLESAR/WQ0hList Size Extended
0 No extended Message ID filter
1-64 Number of extended Message ID filter elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0RESERVEDR/W0h

26.2.2.30 MCAN_XIDAM Register (Offset = 7090h) [Reset = 1FFFFFFFh]

MCAN_XIDAM is shown in Figure 26-56 and described in Table 26-50.

Return to the Summary Table.

MCAN Extended ID and Mask

Figure 26-56 MCAN_XIDAM Register
313029282726252423222120191817161514131211109876543210
RESERVEDEIDM
R/W-0hR/WQ-1FFFFFFFh
Table 26-50 MCAN_XIDAM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28-0EIDMR/WQ1FFFFFFFhExtended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.31 MCAN_HPMS Register (Offset = 7094h) [Reset = 00000000h]

MCAN_HPMS is shown in Figure 26-57 and described in Table 26-51.

Return to the Summary Table.

This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Figure 26-57 MCAN_HPMS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
FLSTFIDX
R-0hR-0h
76543210
MSIBIDX
R-0hR-0h
Table 26-51 MCAN_HPMS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15FLSTR0hFilter List. Indicates the filter list of the matching filter element.
0 Standard Filter List
1 Extended Filter List
14-8FIDXR0hFilter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.
7-6MSIR0hMessage Storage Indicator
00 No FIFO selected
01 FIFO message lost
10 Message stored in FIFO 0
11 Message stored in FIFO 1
5-0BIDXR0hBuffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'.

26.2.2.32 MCAN_NDAT1 Register (Offset = 7098h) [Reset = 00000000h]

MCAN_NDAT1 is shown in Figure 26-58 and described in Table 26-52.

Return to the Summary Table.

MCAN New Data 1

Figure 26-58 MCAN_NDAT1 Register
3130292827262524
ND31ND30ND29ND28ND27ND26ND25ND24
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
2322212019181716
ND23ND22ND21ND20ND19ND18ND17ND16
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
ND15ND14ND13ND12ND11ND10ND9ND8
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
ND7ND6ND5ND4ND3ND2ND1ND0
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 26-52 MCAN_NDAT1 Register Field Descriptions
BitFieldTypeResetDescription
31ND31R/W1C0hNew Data RX Buffer 31
0 Rx Buffer not updated
1 Rx Buffer updated from new message
30ND30R/W1C0hNew Data RX Buffer 30
0 Rx Buffer not updated
1 Rx Buffer updated from new message
29ND29R/W1C0hNew Data RX Buffer 29
0 Rx Buffer not updated
1 Rx Buffer updated from new message
28ND28R/W1C0hNew Data RX Buffer 28
0 Rx Buffer not updated
1 Rx Buffer updated from new message
27ND27R/W1C0hNew Data RX Buffer 27
0 Rx Buffer not updated
1 Rx Buffer updated from new message
26ND26R/W1C0hNew Data RX Buffer 26
0 Rx Buffer not updated
1 Rx Buffer updated from new message
25ND25R/W1C0hNew Data RX Buffer 25
0 Rx Buffer not updated
1 Rx Buffer updated from new message
24ND24R/W1C0hNew Data RX Buffer 24
0 Rx Buffer not updated
1 Rx Buffer updated from new message
23ND23R/W1C0hNew Data RX Buffer 23
0 Rx Buffer not updated
1 Rx Buffer updated from new message
22ND22R/W1C0hNew Data RX Buffer 22
0 Rx Buffer not updated
1 Rx Buffer updated from new message
21ND21R/W1C0hNew Data RX Buffer 21
0 Rx Buffer not updated
1 Rx Buffer updated from new message
20ND20R/W1C0hNew Data RX Buffer 20
0 Rx Buffer not updated
1 Rx Buffer updated from new message
19ND19R/W1C0hNew Data RX Buffer 19
0 Rx Buffer not updated
1 Rx Buffer updated from new message
18ND18R/W1C0hNew Data RX Buffer 18
0 Rx Buffer not updated
1 Rx Buffer updated from new message
17ND17R/W1C0hNew Data RX Buffer 17
0 Rx Buffer not updated
1 Rx Buffer updated from new message
16ND16R/W1C0hNew Data RX Buffer 16
0 Rx Buffer not updated
1 Rx Buffer updated from new message
15ND15R/W1C0hNew Data RX Buffer 15
0 Rx Buffer not updated
1 Rx Buffer updated from new message
14ND14R/W1C0hNew Data RX Buffer 14
0 Rx Buffer not updated
1 Rx Buffer updated from new message
13ND13R/W1C0hNew Data RX Buffer 13
0 Rx Buffer not updated
1 Rx Buffer updated from new message
12ND12R/W1C0hNew Data RX Buffer 12
0 Rx Buffer not updated
1 Rx Buffer updated from new message
11ND11R/W1C0hNew Data RX Buffer 11
0 Rx Buffer not updated
1 Rx Buffer updated from new message
10ND10R/W1C0hNew Data RX Buffer 10
0 Rx Buffer not updated
1 Rx Buffer updated from new message
9ND9R/W1C0hNew Data RX Buffer 9
0 Rx Buffer not updated
1 Rx Buffer updated from new message
8ND8R/W1C0hNew Data RX Buffer 8
0 Rx Buffer not updated
1 Rx Buffer updated from new message
7ND7R/W1C0hNew Data RX Buffer 7
0 Rx Buffer not updated
1 Rx Buffer updated from new message
6ND6R/W1C0hNew Data RX Buffer 6
0 Rx Buffer not updated
1 Rx Buffer updated from new message
5ND5R/W1C0hNew Data RX Buffer 5
0 Rx Buffer not updated
1 Rx Buffer updated from new message
4ND4R/W1C0hNew Data RX Buffer 4
0 Rx Buffer not updated
1 Rx Buffer updated from new message
3ND3R/W1C0hNew Data RX Buffer 3
0 Rx Buffer not updated
1 Rx Buffer updated from new message
2ND2R/W1C0hNew Data RX Buffer 2
0 Rx Buffer not updated
1 Rx Buffer updated from new message
1ND1R/W1C0hNew Data RX Buffer 1
0 Rx Buffer not updated
1 Rx Buffer updated from new message
0ND0R/W1C0hNew Data RX Buffer 0
0 Rx Buffer not updated
1 Rx Buffer updated from new message

26.2.2.33 MCAN_NDAT2 Register (Offset = 709Ch) [Reset = 00000000h]

MCAN_NDAT2 is shown in Figure 26-59 and described in Table 26-53.

Return to the Summary Table.

MCAN New Data 2

Figure 26-59 MCAN_NDAT2 Register
3130292827262524
ND63ND62ND61ND60ND59ND58ND57ND56
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
2322212019181716
ND55ND54ND53ND52ND51ND50ND49ND48
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
ND47ND46ND45ND44ND43ND42ND41ND40
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
ND39ND38ND37ND36ND35ND34ND33ND32
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 26-53 MCAN_NDAT2 Register Field Descriptions
BitFieldTypeResetDescription
31ND63R/W1C0hNew Data RX Buffer 63
0 Rx Buffer not updated
1 Rx Buffer updated from new message
30ND62R/W1C0hNew Data RX Buffer 62
0 Rx Buffer not updated
1 Rx Buffer updated from new message
29ND61R/W1C0hNew Data RX Buffer 61
0 Rx Buffer not updated
1 Rx Buffer updated from new message
28ND60R/W1C0hNew Data RX Buffer 60
0 Rx Buffer not updated
1 Rx Buffer updated from new message
27ND59R/W1C0hNew Data RX Buffer 59
0 Rx Buffer not updated
1 Rx Buffer updated from new message
26ND58R/W1C0hNew Data RX Buffer 58
0 Rx Buffer not updated
1 Rx Buffer updated from new message
25ND57R/W1C0hNew Data RX Buffer 57
0 Rx Buffer not updated
1 Rx Buffer updated from new message
24ND56R/W1C0hNew Data RX Buffer 56
0 Rx Buffer not updated
1 Rx Buffer updated from new message
23ND55R/W1C0hNew Data RX Buffer 55
0 Rx Buffer not updated
1 Rx Buffer updated from new message
22ND54R/W1C0hNew Data RX Buffer 54
0 Rx Buffer not updated
1 Rx Buffer updated from new message
21ND53R/W1C0hNew Data RX Buffer 53
0 Rx Buffer not updated
1 Rx Buffer updated from new message
20ND52R/W1C0hNew Data RX Buffer 52
0 Rx Buffer not updated
1 Rx Buffer updated from new message
19ND51R/W1C0hNew Data RX Buffer 51
0 Rx Buffer not updated
1 Rx Buffer updated from new message
18ND50R/W1C0hNew Data RX Buffer 50
0 Rx Buffer not updated
1 Rx Buffer updated from new message
17ND49R/W1C0hNew Data RX Buffer 49
0 Rx Buffer not updated
1 Rx Buffer updated from new message
16ND48R/W1C0hNew Data RX Buffer 48
0 Rx Buffer not updated
1 Rx Buffer updated from new message
15ND47R/W1C0hNew Data RX Buffer 47
0 Rx Buffer not updated
1 Rx Buffer updated from new message
14ND46R/W1C0hNew Data RX Buffer 46
0 Rx Buffer not updated
1 Rx Buffer updated from new message
13ND45R/W1C0hNew Data RX Buffer 45
0 Rx Buffer not updated
1 Rx Buffer updated from new message
12ND44R/W1C0hNew Data RX Buffer 44
0 Rx Buffer not updated
1 Rx Buffer updated from new message
11ND43R/W1C0hNew Data RX Buffer 43
0 Rx Buffer not updated
1 Rx Buffer updated from new message
10ND42R/W1C0hNew Data RX Buffer 42
0 Rx Buffer not updated
1 Rx Buffer updated from new message
9ND41R/W1C0hNew Data RX Buffer 41
0 Rx Buffer not updated
1 Rx Buffer updated from new message
8ND40R/W1C0hNew Data RX Buffer 40
0 Rx Buffer not updated
1 Rx Buffer updated from new message
7ND39R/W1C0hNew Data RX Buffer 39
0 Rx Buffer not updated
1 Rx Buffer updated from new message
6ND38R/W1C0hNew Data RX Buffer 38
0 Rx Buffer not updated
1 Rx Buffer updated from new message
5ND37R/W1C0hNew Data RX Buffer 37
0 Rx Buffer not updated
1 Rx Buffer updated from new message
4ND36R/W1C0hNew Data RX Buffer 36
0 Rx Buffer not updated
1 Rx Buffer updated from new message
3ND35R/W1C0hNew Data RX Buffer 35
0 Rx Buffer not updated
1 Rx Buffer updated from new message
2ND34R/W1C0hNew Data RX Buffer 34
0 Rx Buffer not updated
1 Rx Buffer updated from new message
1ND33R/W1C0hNew Data RX Buffer 33
0 Rx Buffer not updated
1 Rx Buffer updated from new message
0ND32R/W1C0hNew Data RX Buffer 32
0 Rx Buffer not updated
1 Rx Buffer updated from new message

26.2.2.34 MCAN_RXF0C Register (Offset = 70A0h) [Reset = 00000000h]

MCAN_RXF0C is shown in Figure 26-60 and described in Table 26-54.

Return to the Summary Table.

MCAN Rx FIFO 0 Configuration

Figure 26-60 MCAN_RXF0C Register
3130292827262524
F0OMF0WM
R/WQ-0hR/WQ-0h
2322212019181716
RESERVEDF0S
R/W-0hR/WQ-0h
15141312111098
F0SA
R/WQ-0h
76543210
F0SARESERVED
R/WQ-0hR/W-0h
Table 26-54 MCAN_RXF0C Register Field Descriptions
BitFieldTypeResetDescription
31F0OMR/WQ0hFIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode.
0 FIFO 0 blocking mode
1 FIFO 0 overwrite mode

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
30-24F0WMR/WQ0hRx FIFO 0 Watermark
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W)
>64 Watermark interrupt disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23RESERVEDR/W0h
22-16F0SR/WQ0hRx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1.
0 No Rx FIFO 0
1-64 Number of Rx FIFO 0 elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2F0SAR/WQ0hRx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0RESERVEDR/W0h

26.2.2.35 MCAN_RXF0S Register (Offset = 70A4h) [Reset = 00000000h]

MCAN_RXF0S is shown in Figure 26-61 and described in Table 26-55.

Return to the Summary Table.

MCAN Rx FIFO 0 Status

Figure 26-61 MCAN_RXF0S Register
3130292827262524
RESERVEDRF0LF0F
R-0hR-0hR-0h
2322212019181716
RESERVEDF0PI
R-0hR-0h
15141312111098
RESERVEDF0GI
R-0hR-0h
76543210
RESERVEDF0FL
R-0hR-0h
Table 26-55 MCAN_RXF0S Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25RF0LR0hRx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset.
0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag.
24F0FR0hRx FIFO 0 Full
0 Rx FIFO 0 not full
1 Rx FIFO 0 full
23-22RESERVEDR0h
21-16F0PIR0hRx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63.
15-14RESERVEDR0h
13-8F0GIR0hRx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63.
7RESERVEDR0h
6-0F0FLR0hRx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64.

26.2.2.36 MCAN_RXF0A Register (Offset = 70A8h) [Reset = 00000000h]

MCAN_RXF0A is shown in Figure 26-62 and described in Table 26-56.

Return to the Summary Table.

MCAN Rx FIFO 0 Acknowledge

Figure 26-62 MCAN_RXF0A Register
313029282726252423222120191817161514131211109876543210
RESERVEDF0AI
R/W-0hR/W-0h
Table 26-56 MCAN_RXF0A Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-0F0AIR/W0hRx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.

26.2.2.37 MCAN_RXBC Register (Offset = 70ACh) [Reset = 00000000h]

MCAN_RXBC is shown in Figure 26-63 and described in Table 26-57.

Return to the Summary Table.

MCAN Rx Buffer Configuration

Figure 26-63 MCAN_RXBC Register
313029282726252423222120191817161514131211109876543210
RESERVEDRBSARESERVED
R/W-0hR/WQ-0hR/W-0h
Table 26-57 MCAN_RXBC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-2RBSAR/WQ0hRx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).
1-0RESERVEDR/W0h

26.2.2.38 MCAN_RXF1C Register (Offset = 70B0h) [Reset = 00000000h]

MCAN_RXF1C is shown in Figure 26-64 and described in Table 26-58.

Return to the Summary Table.

MCAN Rx FIFO 1 Configuration

Figure 26-64 MCAN_RXF1C Register
3130292827262524
F1OMF1WM
R/WQ-0hR/WQ-0h
2322212019181716
RESERVEDF1S
R/W-0hR/WQ-0h
15141312111098
F1SA
R/WQ-0h
76543210
F1SARESERVED
R/WQ-0hR/W-0h
Table 26-58 MCAN_RXF1C Register Field Descriptions
BitFieldTypeResetDescription
31F1OMR/WQ0hFIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode.
0 FIFO 1 blocking mode
1 FIFO 1 overwrite mode

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
30-24F1WMR/WQ0hRx FIFO 1 Watermark
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
>64 Watermark interrupt disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23RESERVEDR/W0h
22-16F1SR/WQ0hRx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1.
0 No Rx FIFO 1
1-64 Number of Rx FIFO 1 elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2F1SAR/WQ0hRx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address).
1-0RESERVEDR/W0h

26.2.2.39 MCAN_RXF1S Register (Offset = 70B4h) [Reset = 00000000h]

MCAN_RXF1S is shown in Figure 26-65 and described in Table 26-59.

Return to the Summary Table.

MCAN Rx FIFO 1 Status

Figure 26-65 MCAN_RXF1S Register
3130292827262524
DMSRESERVEDRF1LF1F
R-0hR-0hR-0hR-0h
2322212019181716
RESERVEDF1PI
R-0hR-0h
15141312111098
RESERVEDF1GI
R-0hR-0h
76543210
RESERVEDF1FL
R-0hR-0h
Table 26-59 MCAN_RXF1S Register Field Descriptions
BitFieldTypeResetDescription
31-30DMSR0hDebug Message Status
00 Idle state, wait for reception of debug messages
01 Debug message A received
10 Debug messages A, B received
11 Debug messages A, B, C received
29-26RESERVEDR0h
25RF1LR0hRx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
0 No Rx FIFO 1 message lost
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag.
24F1FR0hRx FIFO 1 Full
0 Rx FIFO 1 not full
1 Rx FIFO 1 full
23-22RESERVEDR0h
21-16F1PIR0hRx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63.
15-14RESERVEDR0h
13-8F1GIR0hRx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63.
7RESERVEDR0h
6-0F1FLR0hRx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64.

26.2.2.40 MCAN_RXF1A Register (Offset = 70B8h) [Reset = 00000000h]

MCAN_RXF1A is shown in Figure 26-66 and described in Table 26-60.

Return to the Summary Table.

MCAN Rx FIFO 1 Acknowledge

Figure 26-66 MCAN_RXF1A Register
313029282726252423222120191817161514131211109876543210
RESERVEDF1AI
R/W-0hR/W-0h
Table 26-60 MCAN_RXF1A Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-0F1AIR/W0hRx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.

26.2.2.41 MCAN_RXESC Register (Offset = 70BCh) [Reset = 00000000h]

MCAN_RXESC is shown in Figure 26-67 and described in Table 26-61.

Return to the Summary Table.

Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes >8 bytes are intended for CAN FD operation only.

Figure 26-67 MCAN_RXESC Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRBDS
R/W-0hR/WQ-0h
76543210
RESERVEDF1DSRESERVEDF0DS
R/W-0hR/WQ-0hR/W-0hR/WQ-0h
Table 26-61 MCAN_RXESC Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR/W0h
10-8RBDSR/WQ0hRx Buffer Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7RESERVEDR/W0h
6-4F1DSR/WQ0hRx FIFO 1 Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3RESERVEDR/W0h
2-0F0DSR/WQ0hRx FIFO 0 Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.42 MCAN_TXBC Register (Offset = 70C0h) [Reset = 00000000h]

MCAN_TXBC is shown in Figure 26-68 and described in Table 26-62.

Return to the Summary Table.

MCAN Tx Buffer Configuration

Figure 26-68 MCAN_TXBC Register
3130292827262524
RESERVEDTFQMTFQS
R/W-0hR/WQ-0hR/WQ-0h
2322212019181716
RESERVEDNDTB
R/W-0hR/WQ-0h
15141312111098
TBSA
R/WQ-0h
76543210
TBSARESERVED
R/WQ-0hR/W-0h
Table 26-62 MCAN_TXBC Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h
30TFQMR/WQ0hTx FIFO/Queue Mode
0 Tx FIFO operation
1 Tx Queue operation

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
29-24TFQSR/WQ0hTransmit FIFO/Queue Size
0 No Tx FIFO/Queue
1-32 Number of Tx Buffers used for Tx FIFO/Queue
>32 Values greater than 32 are interpreted as 32

Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23-22RESERVEDR/W0h
21-16NDTBR/WQ0hNumber of Dedicated Transmit Buffers
0 No Dedicated Tx Buffers
1-32 Number of Dedicated Tx Buffers
>32 Values greater than 32 are interpreted as 32

Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2TBSAR/WQ0hTx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0RESERVEDR/W0h

26.2.2.43 MCAN_TXFQS Register (Offset = 70C4h) [Reset = 00000000h]

MCAN_TXFQS is shown in Figure 26-69 and described in Table 26-63.

Return to the Summary Table.

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).

Figure 26-69 MCAN_TXFQS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTFQFTFQP
R-0hR-0hR-0h
15141312111098
RESERVEDTFGI
R-0hR-0h
76543210
RESERVEDTFFL
R-0hR-0h
Table 26-63 MCAN_TXFQS Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21TFQFR0hTx FIFO/Queue Full
0 Tx FIFO/Queue not full
1 Tx FIFO/Queue full
20-16TFQPR0hTx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31.

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
15-13RESERVEDR0h
12-8TFGIR0hTx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
7-6RESERVEDR0h
5-0TFFLR0hTx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

26.2.2.44 MCAN_TXESC Register (Offset = 70C8h) [Reset = 00000000h]

MCAN_TXESC is shown in Figure 26-70 and described in Table 26-64.

Return to the Summary Table.

Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only.

Figure 26-70 MCAN_TXESC Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDTBDS
R/W-0hR/WQ-0h
Table 26-64 MCAN_TXESC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0TBDSR/WQ0hTx Buffer Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as "0xCC" (padding bytes).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

26.2.2.45 MCAN_TXBRP Register (Offset = 70CCh) [Reset = 00000000h]

MCAN_TXBRP is shown in Figure 26-71 and described in Table 26-65.

Return to the Summary Table.

MCAN Tx Buffer Request Pending

Figure 26-71 MCAN_TXBRP Register
3130292827262524
TRP31TRP30TRP29TRP28TRP27TRP26TRP25TRP24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
TRP23TRP22TRP21TRP20TRP19TRP18TRP17TRP16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TRP15TRP14TRP13TRP12TRP11TRP10TRP9TRP8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TRP7TRP6TRP5TRP4TRP3TRP2TRP1TRP0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 26-65 MCAN_TXBRP Register Field Descriptions
BitFieldTypeResetDescription
31TRP31R0hTransmission Request Pending 31. See description for bit 0.
30TRP30R0hTransmission Request Pending 30. See description for bit 0.
29TRP29R0hTransmission Request Pending 29. See description for bit 0.
28TRP28R0hTransmission Request Pending 28. See description for bit 0.
27TRP27R0hTransmission Request Pending 27. See description for bit 0.
26TRP26R0hTransmission Request Pending 26. See description for bit 0.
25TRP25R0hTransmission Request Pending 25. See description for bit 0.
24TRP24R0hTransmission Request Pending 24. See description for bit 0.
23TRP23R0hTransmission Request Pending 23. See description for bit 0.
22TRP22R0hTransmission Request Pending 22. See description for bit 0.
21TRP21R0hTransmission Request Pending 21. See description for bit 0.
20TRP20R0hTransmission Request Pending 20. See description for bit 0.
19TRP19R0hTransmission Request Pending 19. See description for bit 0.
18TRP18R0hTransmission Request Pending 18. See description for bit 0.
17TRP17R0hTransmission Request Pending 17. See description for bit 0.
16TRP16R0hTransmission Request Pending 16. See description for bit 0.
15TRP15R0hTransmission Request Pending 15. See description for bit 0.
14TRP14R0hTransmission Request Pending 14. See description for bit 0.
13TRP13R0hTransmission Request Pending 13. See description for bit 0.
12TRP12R0hTransmission Request Pending 12. See description for bit 0.
11TRP11R0hTransmission Request Pending 11. See description for bit 0.
10TRP10R0hTransmission Request Pending 10. See description for bit 0.
9TRP9R0hTransmission Request Pending 9. See description for bit 0.
8TRP8R0hTransmission Request Pending 8. See description for bit 0.
7TRP7R0hTransmission Request Pending 7. See description for bit 0.
6TRP6R0hTransmission Request Pending 6. See description for bit 0.
5TRP5R0hTransmission Request Pending 5. See description for bit 0.
4TRP4R0hTransmission Request Pending 4. See description for bit 0.
3TRP3R0hTransmission Request Pending 3. See description for bit 0.
2TRP2R0hTransmission Request Pending 2. See description for bit 0.
1TRP1R0hTransmission Request Pending 1. See description for bit 0.
0TRP0R0hTransmission Request Pending 0.

Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR.

TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).

A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset.

After a cancellation has been requested, a finished cancellation is signalled via TXBCF
- after successful transmission together with the corresponding TXBTO bit
- when the transmission has not yet been started at the point of cancellation
- when the transmission has been aborted due to lost arbitration
- when an error occurred during frame transmission

In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions.
0 No transmission request pending
1 Transmission request pending

Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset.

26.2.2.46 MCAN_TXBAR Register (Offset = 70D0h) [Reset = 00000000h]

MCAN_TXBAR is shown in Figure 26-72 and described in Table 26-66.

Return to the Summary Table.

MCAN Tx Buffer Add Request

Figure 26-72 MCAN_TXBAR Register
3130292827262524
AR31AR30AR29AR28AR27AR26AR25AR24
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
2322212019181716
AR23AR22AR21AR20AR19AR18AR17AR16
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
15141312111098
AR15AR14AR13AR12AR11AR10AR9AR8
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
76543210
AR7AR6AR5AR4AR3AR2AR1AR0
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
Table 26-66 MCAN_TXBAR Register Field Descriptions
BitFieldTypeResetDescription
31AR31R/WQ0hAdd Request 31. See description for bit 0.
30AR30R/WQ0hAdd Request 30. See description for bit 0.
29AR29R/WQ0hAdd Request 29. See description for bit 0.
28AR28R/WQ0hAdd Request 28. See description for bit 0.
27AR27R/WQ0hAdd Request 27. See description for bit 0.
26AR26R/WQ0hAdd Request 26. See description for bit 0.
25AR25R/WQ0hAdd Request 25. See description for bit 0.
24AR24R/WQ0hAdd Request 24. See description for bit 0.
23AR23R/WQ0hAdd Request 23. See description for bit 0.
22AR22R/WQ0hAdd Request 22. See description for bit 0.
21AR21R/WQ0hAdd Request 21. See description for bit 0.
20AR20R/WQ0hAdd Request 20. See description for bit 0.
19AR19R/WQ0hAdd Request 19. See description for bit 0.
18AR18R/WQ0hAdd Request 18. See description for bit 0.
17AR17R/WQ0hAdd Request 17. See description for bit 0.
16AR16R/WQ0hAdd Request 16. See description for bit 0.
15AR15R/WQ0hAdd Request 15. See description for bit 0.
14AR14R/WQ0hAdd Request 14. See description for bit 0.
13AR13R/WQ0hAdd Request 13. See description for bit 0.
12AR12R/WQ0hAdd Request 12. See description for bit 0.
11AR11R/WQ0hAdd Request 11. See description for bit 0.
10AR10R/WQ0hAdd Request 10. See description for bit 0.
9AR9R/WQ0hAdd Request 9. See description for bit 0.
8AR8R/WQ0hAdd Request 8. See description for bit 0.
7AR7R/WQ0hAdd Request 7. See description for bit 0.
6AR6R/WQ0hAdd Request 6. See description for bit 0.
5AR5R/WQ0hAdd Request 5. See description for bit 0.
4AR4R/WQ0hAdd Request 4. See description for bit 0.
3AR3R/WQ0hAdd Request 3. See description for bit 0.
2AR2R/WQ0hAdd Request 2. See description for bit 0.
1AR1R/WQ0hAdd Request 1. See description for bit 0.
0AR0R/WQ0hAdd Request 0.

Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit
writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.
0 No transmission request added
1 Transmission requested added

Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored.

Qualified Write is possible only with CCCR.CCE='0'

26.2.2.47 MCAN_TXBCR Register (Offset = 70D4h) [Reset = 00000000h]

MCAN_TXBCR is shown in Figure 26-73 and described in Table 26-67.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Request

Figure 26-73 MCAN_TXBCR Register
3130292827262524
CR31CR30CR29CR28CR27CR26CR25CR24
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
2322212019181716
CR23CR22CR21CR20CR19CR18CR17CR16
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
15141312111098
CR15CR14CR13CR12CR11CR10CR9CR8
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
76543210
CR7CR6CR5CR4CR3CR2CR1CR0
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
Table 26-67 MCAN_TXBCR Register Field Descriptions
BitFieldTypeResetDescription
31CR31R/WQ0hCancellation Request 31. See description for bit 0.
30CR30R/WQ0hCancellation Request 30. See description for bit 0.
29CR29R/WQ0hCancellation Request 29. See description for bit 0.
28CR28R/WQ0hCancellation Request 28. See description for bit 0.
27CR27R/WQ0hCancellation Request 27. See description for bit 0.
26CR26R/WQ0hCancellation Request 26. See description for bit 0.
25CR25R/WQ0hCancellation Request 25. See description for bit 0.
24CR24R/WQ0hCancellation Request 24. See description for bit 0.
23CR23R/WQ0hCancellation Request 23. See description for bit 0.
22CR22R/WQ0hCancellation Request 22. See description for bit 0.
21CR21R/WQ0hCancellation Request 21. See description for bit 0.
20CR20R/WQ0hCancellation Request 20. See description for bit 0.
19CR19R/WQ0hCancellation Request 19. See description for bit 0.
18CR18R/WQ0hCancellation Request 18. See description for bit 0.
17CR17R/WQ0hCancellation Request 17. See description for bit 0.
16CR16R/WQ0hCancellation Request 16. See description for bit 0.
15CR15R/WQ0hCancellation Request 15. See description for bit 0.
14CR14R/WQ0hCancellation Request 14. See description for bit 0.
13CR13R/WQ0hCancellation Request 13. See description for bit 0.
12CR12R/WQ0hCancellation Request 12. See description for bit 0.
11CR11R/WQ0hCancellation Request 11. See description for bit 0.
10CR10R/WQ0hCancellation Request 10. See description for bit 0.
9CR9R/WQ0hCancellation Request 9. See description for bit 0.
8CR8R/WQ0hCancellation Request 8. See description for bit 0.
7CR7R/WQ0hCancellation Request 7. See description for bit 0.
6CR6R/WQ0hCancellation Request 6. See description for bit 0.
5CR5R/WQ0hCancellation Request 5. See description for bit 0.
4CR4R/WQ0hCancellation Request 4. See description for bit 0.
3CR3R/WQ0hCancellation Request 3. See description for bit 0.
2CR2R/WQ0hCancellation Request 2. See description for bit 0.
1CR1R/WQ0hCancellation Request 1. See description for bit 0.
0CR0R/WQ0hCancellation Request 0.

Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit
writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset.
0 No cancellation pending
1 Cancellation pending

Qualified Write is possible only with CCCR.CCE='0'

26.2.2.48 MCAN_TXBTO Register (Offset = 70D8h) [Reset = 00000000h]

MCAN_TXBTO is shown in Figure 26-74 and described in Table 26-68.

Return to the Summary Table.

MCAN Tx Buffer Transmission Occurred

Figure 26-74 MCAN_TXBTO Register
3130292827262524
TO31TO30TO29TO28TO27TO26TO25TO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
TO23TO22TO21TO20TO19TO18TO17TO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TO15TO14TO13TO12TO11TO10TO9TO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TO7TO6TO5TO4TO3TO2TO1TO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 26-68 MCAN_TXBTO Register Field Descriptions
BitFieldTypeResetDescription
31TO31R0hTransmission Occurred 31. See description for bit 0.
30TO30R0hTransmission Occurred 30. See description for bit 0.
29TO29R0hTransmission Occurred 29. See description for bit 0.
28TO28R0hTransmission Occurred 28. See description for bit 0.
27TO27R0hTransmission Occurred 27. See description for bit 0.
26TO26R0hTransmission Occurred 26. See description for bit 0.
25TO25R0hTransmission Occurred 25. See description for bit 0.
24TO24R0hTransmission Occurred 24. See description for bit 0.
23TO23R0hTransmission Occurred 23. See description for bit 0.
22TO22R0hTransmission Occurred 22. See description for bit 0.
21TO21R0hTransmission Occurred 21. See description for bit 0.
20TO20R0hTransmission Occurred 20. See description for bit 0.
19TO19R0hTransmission Occurred 19. See description for bit 0.
18TO18R0hTransmission Occurred 18. See description for bit 0.
17TO17R0hTransmission Occurred 17. See description for bit 0.
16TO16R0hTransmission Occurred 16. See description for bit 0.
15TO15R0hTransmission Occurred 15. See description for bit 0.
14TO14R0hTransmission Occurred 14. See description for bit 0.
13TO13R0hTransmission Occurred 13. See description for bit 0.
12TO12R0hTransmission Occurred 12. See description for bit 0.
11TO11R0hTransmission Occurred 11. See description for bit 0.
10TO10R0hTransmission Occurred 10. See description for bit 0.
9TO9R0hTransmission Occurred 9. See description for bit 0.
8TO8R0hTransmission Occurred 8. See description for bit 0.
7TO7R0hTransmission Occurred 7. See description for bit 0.
6TO6R0hTransmission Occurred 6. See description for bit 0.
5TO5R0hTransmission Occurred 5. See description for bit 0.
4TO4R0hTransmission Occurred 4. See description for bit 0.
3TO3R0hTransmission Occurred 3. See description for bit 0.
2TO2R0hTransmission Occurred 2. See description for bit 0.
1TO1R0hTransmission Occurred 1. See description for bit 0.
0TO0R0hTransmission Occurred 0.

Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
0 No transmission occurred
1 Transmission occurred

26.2.2.49 MCAN_TXBCF Register (Offset = 70DCh) [Reset = 00000000h]

MCAN_TXBCF is shown in Figure 26-75 and described in Table 26-69.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Finished

Figure 26-75 MCAN_TXBCF Register
3130292827262524
CF31CF30CF29CF28CF27CF26CF25CF24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
CF23CF22CF21CF20CF19CF18CF17CF16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
CF15CF14CF13CF12CF11CF10CF9CF8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CF7CF6CF5CF4CF3CF2CF1CF0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 26-69 MCAN_TXBCF Register Field Descriptions
BitFieldTypeResetDescription
31CF31R0hCancellation Finished 31. See description for bit 0.
30CF30R0hCancellation Finished 30. See description for bit 0.
29CF29R0hCancellation Finished 29. See description for bit 0.
28CF28R0hCancellation Finished 28. See description for bit 0.
27CF27R0hCancellation Finished 27. See description for bit 0.
26CF26R0hCancellation Finished 26. See description for bit 0.
25CF25R0hCancellation Finished 25. See description for bit 0.
24CF24R0hCancellation Finished 24. See description for bit 0.
23CF23R0hCancellation Finished 23. See description for bit 0.
22CF22R0hCancellation Finished 22. See description for bit 0.
21CF21R0hCancellation Finished 21. See description for bit 0.
20CF20R0hCancellation Finished 20. See description for bit 0.
19CF19R0hCancellation Finished 19. See description for bit 0.
18CF18R0hCancellation Finished 18. See description for bit 0.
17CF17R0hCancellation Finished 17. See description for bit 0.
16CF16R0hCancellation Finished 16. See description for bit 0.
15CF15R0hCancellation Finished 15. See description for bit 0.
14CF14R0hCancellation Finished 14. See description for bit 0.
13CF13R0hCancellation Finished 13. See description for bit 0.
12CF12R0hCancellation Finished 12. See description for bit 0.
11CF11R0hCancellation Finished 11. See description for bit 0.
10CF10R0hCancellation Finished 10. See description for bit 0.
9CF9R0hCancellation Finished 9. See description for bit 0.
8CF8R0hCancellation Finished 8. See description for bit 0.
7CF7R0hCancellation Finished 7. See description for bit 0.
6CF6R0hCancellation Finished 6. See description for bit 0.
5CF5R0hCancellation Finished 5. See description for bit 0.
4CF4R0hCancellation Finished 4. See description for bit 0.
3CF3R0hCancellation Finished 3. See description for bit 0.
2CF2R0hCancellation Finished 2. See description for bit 0.
1CF1R0hCancellation Finished 1. See description for bit 0.
0CF0R0hCancellation Finished 0.

Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
0 No transmit buffer cancellation
1 Transmit buffer cancellation finished

26.2.2.50 MCAN_TXBTIE Register (Offset = 70E0h) [Reset = 00000000h]

MCAN_TXBTIE is shown in Figure 26-76 and described in Table 26-70.

Return to the Summary Table.

MCAN Tx Buffer Transmission Interrupt Enable

Figure 26-76 MCAN_TXBTIE Register
3130292827262524
TIE31TIE30TIE29TIE28TIE27TIE26TIE25TIE24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TIE23TIE22TIE21TIE20TIE19TIE18TIE17TIE16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TIE15TIE14TIE13TIE12TIE11TIE10TIE9TIE8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TIE7TIE6TIE5TIE4TIE3TIE2TIE1TIE0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 26-70 MCAN_TXBTIE Register Field Descriptions
BitFieldTypeResetDescription
31TIE31R/W0hTransmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
30TIE30R/W0hTransmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
29TIE29R/W0hTransmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
28TIE28R/W0hTransmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
27TIE27R/W0hTransmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
26TIE26R/W0hTransmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
25TIE25R/W0hTransmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
24TIE24R/W0hTransmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
23TIE23R/W0hTransmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
22TIE22R/W0hTransmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
21TIE21R/W0hTransmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
20TIE20R/W0hTransmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
19TIE19R/W0hTransmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
18TIE18R/W0hTransmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
17TIE17R/W0hTransmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
16TIE16R/W0hTransmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
15TIE15R/W0hTransmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
14TIE14R/W0hTransmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
13TIE13R/W0hTransmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
12TIE12R/W0hTransmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
11TIE11R/W0hTransmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
10TIE10R/W0hTransmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
9TIE9R/W0hTransmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
8TIE8R/W0hTransmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
7TIE7R/W0hTransmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
6TIE6R/W0hTransmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
5TIE5R/W0hTransmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
4TIE4R/W0hTransmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
3TIE3R/W0hTransmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
2TIE2R/W0hTransmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
1TIE1R/W0hTransmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
0TIE0R/W0hTransmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

26.2.2.51 MCAN_TXBCIE Register (Offset = 70E4h) [Reset = 00000000h]

MCAN_TXBCIE is shown in Figure 26-77 and described in Table 26-71.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Finished Interrupt Enable

Figure 26-77 MCAN_TXBCIE Register
3130292827262524
CFIE31CFIE30CFIE29CFIE28CFIE27CFIE26CFIE25CFIE24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CFIE23CFIE22CFIE21CFIE20CFIE19CFIE18CFIE17CFIE16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CFIE15CFIE14CFIE13CFIE12CFIE11CFIE10CFIE9CFIE8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CFIE7CFIE6CFIE5CFIE4CFIE3CFIE2CFIE1CFIE0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 26-71 MCAN_TXBCIE Register Field Descriptions
BitFieldTypeResetDescription
31CFIE31R/W0hCancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
30CFIE30R/W0hCancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
29CFIE29R/W0hCancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
28CFIE28R/W0hCancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
27CFIE27R/W0hCancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
26CFIE26R/W0hCancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
25CFIE25R/W0hCancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
24CFIE24R/W0hCancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
23CFIE23R/W0hCancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
22CFIE22R/W0hCancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
21CFIE21R/W0hCancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
20CFIE20R/W0hCancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
19CFIE19R/W0hCancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
18CFIE18R/W0hCancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
17CFIE17R/W0hCancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
16CFIE16R/W0hCancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
15CFIE15R/W0hCancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
14CFIE14R/W0hCancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
13CFIE13R/W0hCancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
12CFIE12R/W0hCancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
11CFIE11R/W0hCancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
10CFIE10R/W0hCancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
9CFIE9R/W0hCancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
8CFIE8R/W0hCancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
7CFIE7R/W0hCancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
6CFIE6R/W0hCancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
5CFIE5R/W0hCancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
4CFIE4R/W0hCancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
3CFIE3R/W0hCancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
2CFIE2R/W0hCancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
1CFIE1R/W0hCancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
0CFIE0R/W0hCancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

26.2.2.52 MCAN_TXEFC Register (Offset = 70F0h) [Reset = 00000000h]

MCAN_TXEFC is shown in Figure 26-78 and described in Table 26-72.

Return to the Summary Table.

MCAN Tx Event FIFO Configuration

Figure 26-78 MCAN_TXEFC Register
3130292827262524
RESERVEDEFWM
R/W-0hR/WQ-0h
2322212019181716
RESERVEDEFS
R/W-0hR/WQ-0h
15141312111098
EFSA
R/WQ-0h
76543210
EFSARESERVED
R/WQ-0hR/W-0h
Table 26-72 MCAN_TXEFC Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29-24EFWMR/WQ0hEvent FIFO Watermark
0 Watermark interrupt disabled
1-32 Level for Tx Event FIFO watermark interrupt (IR.TEFW)
>32 Watermark interrupt disabled
23-22RESERVEDR/W0h
21-16EFSR/WQ0hEvent FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1.
0 Tx Event FIFO disabled
1-32 Number of Tx Event FIFO elements
>32 Values greater than 32 are interpreted as 32
15-2EFSAR/WQ0hEvent FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address).
1-0RESERVEDR/W0h

26.2.2.53 MCAN_TXEFS Register (Offset = 70F4h) [Reset = 00000000h]

MCAN_TXEFS is shown in Figure 26-79 and described in Table 26-73.

Return to the Summary Table.

MCAN Tx Event FIFO Status

Figure 26-79 MCAN_TXEFS Register
3130292827262524
RESERVEDTEFLEFF
R-0hR-0hR-0h
2322212019181716
RESERVEDEFPI
R-0hR-0h
15141312111098
RESERVEDEFGI
R-0hR-0h
76543210
RESERVEDEFFL
R-0hR-0h
Table 26-73 MCAN_TXEFS Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25TEFLR0hTx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.
0 No Tx Event FIFO element lost
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
24EFFR0hEvent FIFO Full
0 Tx Event FIFO not full
1 Tx Event FIFO full
23-21RESERVEDR0h
20-16EFPIR0hEvent FIFO Put Index.Tx Event FIFO write index pointer, range 0 to 31.
15-13RESERVEDR0h
12-8EFGIR0hEvent FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31.
7-6RESERVEDR0h
5-0EFFLR0hEvent FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 32.

26.2.2.54 MCAN_TXEFA Register (Offset = 70F8h) [Reset = 00000000h]

MCAN_TXEFA is shown in Figure 26-80 and described in Table 26-74.

Return to the Summary Table.

MCAN Tx Event FIFO Acknowledge

Figure 26-80 MCAN_TXEFA Register
313029282726252423222120191817161514131211109876543210
RESERVEDEFAI
R/W-0hR/W-0h
Table 26-74 MCAN_TXEFA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0h
4-0EFAIR/W0hEvent FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL.

26.2.2.55 MCANSS_PID Register (Offset = 7200h) [Reset = 68E04901h]

MCANSS_PID is shown in Figure 26-81 and described in Table 26-75.

Return to the Summary Table.

MCAN Subsystem Revision Register

Figure 26-81 MCANSS_PID Register
31302928272625242322212019181716
SCHEMERESERVEDMODULE_ID
R-1hR-2hR-8E0h
1514131211109876543210
RESERVEDMAJORRESERVEDMINOR
R-9hR-1hR-0hR-1h
Table 26-75 MCANSS_PID Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMER1hPID Register Scheme
29-28RESERVEDR2hReserved
27-16MODULE_IDR8E0hModule Identification Number
15-11RESERVEDR9hReserved
10-8MAJORR1hMajor Revision of the MCAN Subsystem
7-6RESERVEDR0hReserved
5-0MINORR1hMinor Revision of the MCAN Subsystem

26.2.2.56 MCANSS_CTRL Register (Offset = 7204h) [Reset = 00000008h]

MCANSS_CTRL is shown in Figure 26-82 and described in Table 26-76.

Return to the Summary Table.

MCAN Subsystem Control Register

Figure 26-82 MCANSS_CTRL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEXT_TS_CNTR_ENAUTOWAKEUPWAKEUPREQENDBGSUSP_FREERESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
Table 26-76 MCANSS_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR/W0h
6EXT_TS_CNTR_ENR/W0hExternal Timestamp Counter Enable.
0 External timestamp counter disabled
1 External timestamp counter enabled
5AUTOWAKEUPR/W0hAutomatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up, on an enabled wakeup request.
0 Disable the automatic write to CCCR.INIT
1 Enable the automatic write to CCCR.INIT
4WAKEUPREQENR/W0hWakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity.
0 Disable wakeup request
1 Enables wakeup request
3DBGSUSP_FREER/W1hDebug Suspend Free Bit. Enables debug suspend.
0 Honor debug suspend
1 Disregard debug suspend
2-0RESERVEDR/W0h

26.2.2.57 MCANSS_STAT Register (Offset = 7208h) [Reset = 0000000Xh]

MCANSS_STAT is shown in Figure 26-83 and described in Table 26-77.

Return to the Summary Table.

MCAN Subsystem Status Register

Figure 26-83 MCANSS_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENABLE_FDOEMEM_INIT_DONERESET
R-0hR-XhR-0hR-0h
Table 26-77 MCANSS_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2ENABLE_FDOERXhReflects the value of mcanss_enable_fdoe configuration port
1MEM_INIT_DONER0hMemory Initialization Done.
0 Message RAM initialization is in progress
1 Message RAM is initialized for use
0RESETR0hSoft Reset Status.
0 Not in reset
1 Reset is in progress

26.2.2.58 MCANSS_ICS Register (Offset = 720Ch) [Reset = 00000000h]

MCANSS_ICS is shown in Figure 26-84 and described in Table 26-78.

Return to the Summary Table.

MCAN Subsystem Interrupt Clear Shadow Register

Figure 26-84 MCANSS_ICS Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEXT_TS_CNTR_OVFL
R/W-0hR-0/W1C-0h
Table 26-78 MCANSS_ICS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0EXT_TS_CNTR_OVFLR-0/W1C0hExternal Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0.
0 Write of '0' has no effect
1 Write of '1' clears the MCANSS_IRS.EXT_TS_CNTR_OVFL bit

26.2.2.59 MCANSS_IRS Register (Offset = 7210h) [Reset = 00000000h]

MCANSS_IRS is shown in Figure 26-85 and described in Table 26-79.

Return to the Summary Table.

MCAN Subsystem Interrupt Raw Satus Register

Figure 26-85 MCANSS_IRS Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEXT_TS_CNTR_OVFL
R/W-0hR/W1S-0h
Table 26-79 MCANSS_IRS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0EXT_TS_CNTR_OVFLR/W1S0hExternal Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit.
0 External timestamp counter has not overflowed
1 External timestamp counter has overflowed

When this bit is set to '1' by HW or SW, the MCANSS_EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1.

26.2.2.60 MCANSS_IECS Register (Offset = 7214h) [Reset = 00000000h]

MCANSS_IECS is shown in Figure 26-86 and described in Table 26-80.

Return to the Summary Table.

MCAN Subsystem Interrupt Enable Clear Shadow Register

Figure 26-86 MCANSS_IECS Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEXT_TS_CNTR_OVFL
R/W-0hR-0/W1C-0h
Table 26-80 MCANSS_IECS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0EXT_TS_CNTR_OVFLR-0/W1C0hExternal Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0.
0 Write of '0' has no effect
1 Write of '1' clears the MCANSS_IES.EXT_TS_CNTR_OVFL bit

26.2.2.61 MCANSS_IE Register (Offset = 7218h) [Reset = 00000000h]

MCANSS_IE is shown in Figure 26-87 and described in Table 26-81.

Return to the Summary Table.

MCAN Subsystem Interrupt Enable Register

Figure 26-87 MCANSS_IE Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEXT_TS_CNTR_OVFL
R/W-0hR/W1S-0h
Table 26-81 MCANSS_IE Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0EXT_TS_CNTR_OVFLR/W1S0hExternal Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit.

26.2.2.62 MCANSS_IES Register (Offset = 721Ch) [Reset = 00000000h]

MCANSS_IES is shown in Figure 26-88 and described in Table 26-82.

Return to the Summary Table.

MCAN Subsystem Interrupt Enable Status

Figure 26-88 MCANSS_IES Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEXT_TS_CNTR_OVFL
R-0hR-0h
Table 26-82 MCANSS_IES Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0EXT_TS_CNTR_OVFLR0hExternal Timestamp Counter Overflow Interrupt Enable Status. To set, use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear, use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit.
0 External timestamp counter overflow interrupt is not enabled
1 External timestamp counter overflow interrupt is enabled

26.2.2.63 MCANSS_EOI Register (Offset = 7220h) [Reset = 00000000h]

MCANSS_EOI is shown in Figure 26-89 and described in Table 26-83.

Return to the Summary Table.

MCAN Subsystem End of Interrupt

Figure 26-89 MCANSS_EOI Register
313029282726252423222120191817161514131211109876543210
RESERVEDEOI
R/W-0hR-0/W1S-0h
Table 26-83 MCANSS_EOI Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0EOIR-0/W1S0hEnd of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated.
0x00 External TS Interrupt is cleared
0x01 MCAN(0) interrupt is cleared
0x02 MCAN(1) interrupt is cleared
Other writes are ignored.

26.2.2.64 MCANSS_EXT_TS_PRESCALER Register (Offset = 7224h) [Reset = 00000000h]

MCANSS_EXT_TS_PRESCALER is shown in Figure 26-90 and described in Table 26-84.

Return to the Summary Table.

MCAN Subsystem External Timestamp Prescaler 0

Figure 26-90 MCANSS_EXT_TS_PRESCALER Register
313029282726252423222120191817161514131211109876543210
RESERVEDPRESCALER
R/W-0hR/W-0h
Table 26-84 MCANSS_EXT_TS_PRESCALER Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0h
23-0PRESCALERR/W0hExternal Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001.

26.2.2.65 MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register (Offset = 7228h) [Reset = 00000000h]

MCANSS_EXT_TS_UNSERVICED_INTR_CNTR is shown in Figure 26-91 and described in Table 26-85.

Return to the Summary Table.

MCAN Subsystem External Timestamp Unserviced Interrupts Counter

Figure 26-91 MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEXT_TS_INTR_CNTR
R-0hR-0h
Table 26-85 MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-0EXT_TS_INTR_CNTRR0hExternal Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an MCANSS_EOI write of '1' to bit 0 will issue another interrupt.

The status of this bit field is affected by the MCANSS_IRS.EXT_TS_CNTR_OVFL bit field.

26.2.2.66 MCANERR_REV Register (Offset = 7400h) [Reset = 66A0EA00h]

MCANERR_REV is shown in Figure 26-92 and described in Table 26-86.

Return to the Summary Table.

MCAN Error Aggregator Revision Register

Figure 26-92 MCANERR_REV Register
3130292827262524
SCHEMERESERVEDMODULE_ID
R-1hR-2hR-6A0h
2322212019181716
MODULE_ID
R-6A0h
15141312111098
RESERVEDREVMAJ
R-1DhR-2h
76543210
RESERVEDREVMIN
R-0hR-0h
Table 26-86 MCANERR_REV Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMER1hPID Register Scheme
29-28RESERVEDR2hReserved
27-16MODULE_IDR6A0hModule Identification Number
15-11RESERVEDR1DhReserved
10-8REVMAJR2hMajor Revision of the Error Aggregator
7-6RESERVEDR0hReserved
5-0REVMINR0hMinor Revision of the Error Aggregator

26.2.2.67 MCANERR_VECTOR Register (Offset = 7408h) [Reset = 00000000h]

MCANERR_VECTOR is shown in Figure 26-93 and described in Table 26-87.

Return to the Summary Table.

Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address.

Figure 26-93 MCANERR_VECTOR Register
3130292827262524
RESERVEDRD_SVBUS_DONE
R/W-0hR-0h
2322212019181716
RD_SVBUS_ADDRESS
R/W-0h
15141312111098
RD_SVBUSRESERVEDECC_VECTOR
R-0/W1S-0hR/W-0hR/W-0h
76543210
ECC_VECTOR
R/W-0h
Table 26-87 MCANERR_VECTOR Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/W0h
24RD_SVBUS_DONER0hRead Completion Flag
23-16RD_SVBUS_ADDRESSR/W0hRead Address Offset
15RD_SVBUSR-0/W1S0hRead Trigger
14-11RESERVEDR/W0h
10-0ECC_VECTORR/W0hECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address.
0x000 Message RAM ECC controller is selected
Others Reserved (do not use)

Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing.

26.2.2.68 MCANERR_STAT Register (Offset = 740Ch) [Reset = 00000002h]

MCANERR_STAT is shown in Figure 26-94 and described in Table 26-88.

Return to the Summary Table.

MCAN Error Misc Status

Figure 26-94 MCANERR_STAT Register
313029282726252423222120191817161514131211109876543210
RESERVEDNUM_RAMS
R-0hR-2h
Table 26-88 MCANERR_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0h
10-0NUM_RAMSR2hNumber of RAMs. Number of ECC RAMs serviced by the aggregator.

26.2.2.69 MCANERR_WRAP_REV Register (Offset = 7410h) [Reset = 66A46A02h]

MCANERR_WRAP_REV is shown in Figure 26-95 and described in Table 26-89.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 26-95 MCANERR_WRAP_REV Register
3130292827262524
SCHEMERESERVEDMODULE_ID
R-1hR-2hR-6A4h
2322212019181716
MODULE_ID
R-6A4h
15141312111098
RESERVEDREVMAJ
R-DhR-2h
76543210
RESERVEDREVMIN
R-0hR-2h
Table 26-89 MCANERR_WRAP_REV Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMER1hPID Register Scheme
29-28RESERVEDR2hReserved
27-16MODULE_IDR6A4hModule Identification Number
15-11RESERVEDRDhReserved
10-8REVMAJR2hMajor Revision of the Error Aggregator
7-6RESERVEDR0hReserved
5-0REVMINR2hMinor Revision of the Error Aggregator

26.2.2.70 MCANERR_CTRL Register (Offset = 7414h) [Reset = 00000187h]

MCANERR_CTRL is shown in Figure 26-96 and described in Table 26-90.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 26-96 MCANERR_CTRL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDCHECK_SVBUS_TIMEOUT
R/W-0hR/W-1h
76543210
RESERVEDERROR_ONCEFORCE_N_ROWFORCE_DEDFORCE_SECENABLE_RMWECC_CHECKECC_ENABLE
R/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-1hR/W-1h
Table 26-90 MCANERR_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8CHECK_SVBUS_TIMEOUTR/W1hEnables Serial VBUS timeout mechanism
7RESERVEDR/W1h
6ERROR_ONCER/W0hIf this bit is set, the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled, this error will be cleared the cycle following the read when the data is corrected. For double-bit errors, the FORCE_DED bit will be cleared the cycle following the double-bit error. Any subsequent reads will not force an error.
5FORCE_N_ROWR/W0hEnable single/double-bit error on the next RAM read, regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode, this applies to writes as well as reads.
4FORCE_DEDR/W0hForce double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit.
3FORCE_SECR/W0hForce single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit.
2ENABLE_RMWR/W1hEnable read-modify-write on partial word writes
1ECC_CHECKR/W1hEnable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'.
0ECC_ENABLER/W1hEnable ECC Generation

26.2.2.71 MCANERR_ERR_CTRL1 Register (Offset = 7418h) [Reset = 00000000h]

MCANERR_ERR_CTRL1 is shown in Figure 26-97 and described in Table 26-91.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 26-97 MCANERR_ERR_CTRL1 Register
313029282726252423222120191817161514131211109876543210
ECC_ROW
R/W-0h
Table 26-91 MCANERR_ERR_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ECC_ROWR/W0hRow address where FORCE_SEC or FORCE_DED needs to be applied. This is ignored if FORCE_N_ROW is set.

26.2.2.72 MCANERR_ERR_CTRL2 Register (Offset = 741Ch) [Reset = 00000000h]

MCANERR_ERR_CTRL2 is shown in Figure 26-98 and described in Table 26-92.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 26-98 MCANERR_ERR_CTRL2 Register
313029282726252423222120191817161514131211109876543210
ECC_BIT2ECC_BIT1
R/W-0hR/W-0h
Table 26-92 MCANERR_ERR_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
31-16ECC_BIT2R/W0hSecond column/data bit that needs to be flipped when FORCE_DED is set
15-0ECC_BIT1R/W0hColumn/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set

26.2.2.73 MCANERR_ERR_STAT1 Register (Offset = 7420h) [Reset = 00000000h]

MCANERR_ERR_STAT1 is shown in Figure 26-99 and described in Table 26-93.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 26-99 MCANERR_ERR_STAT1 Register
3130292827262524
ECC_BIT1
R-0h
2322212019181716
ECC_BIT1
R-0h
15141312111098
CLR_CTRL_REG_ERRORRESERVEDCLR_ECC_OTHERCLR_ECC_DEDCLR_ECC_SEC
R/W1S-0hR/W-0hR/W1C-0hR/WD-0hR/WD-0h
76543210
CTRL_REG_ERRORRESERVEDECC_OTHERECC_DEDECC_SEC
R/W1S-0hR/W-0hR/W1S-0hR/WI-0hR/WI-0h
Table 26-93 MCANERR_ERR_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
31-16ECC_BIT1R0hECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error.
0 Bit 0 is in error
1 Bit 1 is in error
2 Bit 2 is in error
3 Bit 3 is in error
...
31 Bit 31 is in error
>32 Invalid
15CLR_CTRL_REG_ERRORR/W1S0hWriting a '1' clears the CTRL_REG_ERROR bit
14-13RESERVEDR/W0h
12CLR_ECC_OTHERR/W1C0hWriting a '1' clears the ECC_OTHER bit.
11-10CLR_ECC_DEDR/WD0hClear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided.
9-8CLR_ECC_SECR/WD0hClear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided.
7CTRL_REG_ERRORR/W1S0hControl Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to re-write these registers to a known state. A write of 1 will set this interrupt flag.
6-5RESERVEDR/W0h
4ECC_OTHERR/W1S0hSEC While Writeback Error Status
0 No SEC error while writeback pending
1 Indicates that successive single-bit errors have occurred while a writeback is still pending
3-2ECC_DEDR/WI0hDouble Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared.

0 No double-bit error detected
1 One double-bit error was detected
2 Two double-bit errors were detected
3 Three double-bit errors were detected

A write of a non-zero value to this bit field increments it by the value provided.
1-0ECC_SECR/WI0hSingle Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared.

0 No single-bit error detected
1 One single-bit error was detected and corrected
2 Two single-bit errors were detected and corrected
3 Three single-bit errors were detected and corrected

A write of a non-zero value to this bit field increments it by the value provided.

26.2.2.74 MCANERR_ERR_STAT2 Register (Offset = 7424h) [Reset = 00000000h]

MCANERR_ERR_STAT2 is shown in Figure 26-100 and described in Table 26-94.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 26-100 MCANERR_ERR_STAT2 Register
313029282726252423222120191817161514131211109876543210
ECC_ROW
R-0h
Table 26-94 MCANERR_ERR_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
31-0ECC_ROWR0hIndicates the row address where the single or double-bit error occurred. This value is address offset/4.

26.2.2.75 MCANERR_ERR_STAT3 Register (Offset = 7428h) [Reset = 00000000h]

MCANERR_ERR_STAT3 is shown in Figure 26-101 and described in Table 26-95.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 26-101 MCANERR_ERR_STAT3 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDCLR_SVBUS_TIMEOUTRESERVED
R/W-0hR-0/W1C-0hR/W-0h
76543210
RESERVEDSVBUS_TIMEOUTWB_PEND
R/W-0hR-0/W1S-0hR-0h
Table 26-95 MCANERR_ERR_STAT3 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9CLR_SVBUS_TIMEOUTR-0/W1C0hWrite 1 to clear the Serial VBUS Timeout Flag
8-2RESERVEDR/W0h
1SVBUS_TIMEOUTR-0/W1S0hSerial VBUS Timeout Flag. Write 1 to set.
0WB_PENDR0hDelayed Write Back Pending Status
0 No write back pending
1 An ECC data correction write back is pending

26.2.2.76 MCANERR_SEC_EOI Register (Offset = 743Ch) [Reset = 00000000h]

MCANERR_SEC_EOI is shown in Figure 26-102 and described in Table 26-96.

Return to the Summary Table.

MCAN Single Error Corrected End of Interrupt Register

Figure 26-102 MCANERR_SEC_EOI Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEOI_WR
R/W-0hR-0/W1S-0h
Table 26-96 MCANERR_SEC_EOI Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0EOI_WRR-0/W1S0hWrite to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host.

Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_SEC goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field.

26.2.2.77 MCANERR_SEC_STATUS Register (Offset = 7440h) [Reset = 00000000h]

MCANERR_SEC_STATUS is shown in Figure 26-103 and described in Table 26-97.

Return to the Summary Table.

MCAN Single Error Corrected Interrupt Status Register

Figure 26-103 MCANERR_SEC_STATUS Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDMSGMEM_PEND
R/W-0hR-0-0h
Table 26-97 MCANERR_SEC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0MSGMEM_PENDR-00hMessage RAM SEC Interrupt Pending
0 No SEC interrupt is pending
1 SEC interrupt is pending

26.2.2.78 MCANERR_SEC_ENABLE_SET Register (Offset = 7480h) [Reset = 00000000h]

MCANERR_SEC_ENABLE_SET is shown in Figure 26-104 and described in Table 26-98.

Return to the Summary Table.

MCAN Single Error Corrected Interrupt Enable Set Register

Figure 26-104 MCANERR_SEC_ENABLE_SET Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDMSGMEM_ENABLE_SET
R/W-0hR/W1S-0h
Table 26-98 MCANERR_SEC_ENABLE_SET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0MSGMEM_ENABLE_SETR/W1S0hMessage RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

26.2.2.79 MCANERR_SEC_ENABLE_CLR Register (Offset = 74C0h) [Reset = 00000000h]

MCANERR_SEC_ENABLE_CLR is shown in Figure 26-105 and described in Table 26-99.

Return to the Summary Table.

MCAN Single Error Corrected Interrupt Enable Clear Register

Figure 26-105 MCANERR_SEC_ENABLE_CLR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDMSGMEM_ENABLE_CLR
R/W-0hR/W1C-0h
Table 26-99 MCANERR_SEC_ENABLE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0MSGMEM_ENABLE_CLRR/W1C0hMessage RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

26.2.2.80 MCANERR_DED_EOI Register (Offset = 753Ch) [Reset = 00000000h]

MCANERR_DED_EOI is shown in Figure 26-106 and described in Table 26-100.

Return to the Summary Table.

MCAN Double Error Detected End of Interrupt Register

Figure 26-106 MCANERR_DED_EOI Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEOI_WR
R/W-0hR-0/W1S-0h
Table 26-100 MCANERR_DED_EOI Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0EOI_WRR-0/W1S0hWrite to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host.

Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_DED goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field.

26.2.2.81 MCANERR_DED_STATUS Register (Offset = 7540h) [Reset = 00000000h]

MCANERR_DED_STATUS is shown in Figure 26-107 and described in Table 26-101.

Return to the Summary Table.

MCAN Double Error Detected Interrupt Status Register

Figure 26-107 MCANERR_DED_STATUS Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDMSGMEM_PEND
R/W-0hR-0-0h
Table 26-101 MCANERR_DED_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0MSGMEM_PENDR-00hMessage RAM DED Interrupt Pending
0 No DED interrupt is pending
1 DED interrupt is pending

26.2.2.82 MCANERR_DED_ENABLE_SET Register (Offset = 7580h) [Reset = 00000000h]

MCANERR_DED_ENABLE_SET is shown in Figure 26-108 and described in Table 26-102.

Return to the Summary Table.

MCAN Double Error Detected Interrupt Enable Set Register

Figure 26-108 MCANERR_DED_ENABLE_SET Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDMSGMEM_ENABLE_SET
R/W-0hR/W1S-0h
Table 26-102 MCANERR_DED_ENABLE_SET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0MSGMEM_ENABLE_SETR/W1S0hMessage RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

26.2.2.83 MCANERR_DED_ENABLE_CLR Register (Offset = 75C0h) [Reset = 00000000h]

MCANERR_DED_ENABLE_CLR is shown in Figure 26-109 and described in Table 26-103.

Return to the Summary Table.

MCAN Double Error Detected Interrupt Enable Clear Register

Figure 26-109 MCANERR_DED_ENABLE_CLR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDMSGMEM_ENABLE_CLR
R/W-0hR/W1C-0h
Table 26-103 MCANERR_DED_ENABLE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0MSGMEM_ENABLE_CLRR/W1C0hMessage RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

26.2.2.84 MCANERR_AGGR_ENABLE_SET Register (Offset = 7600h) [Reset = 00000000h]

MCANERR_AGGR_ENABLE_SET is shown in Figure 26-110 and described in Table 26-104.

Return to the Summary Table.

MCAN Error Aggregator Enable Set Register

Figure 26-110 MCANERR_AGGR_ENABLE_SET Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE_TIMEOUT_SETENABLE_PARITY_SET
R/W-0hR/W1S-0hR/W1S-0h
Table 26-104 MCANERR_AGGR_ENABLE_SET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1ENABLE_TIMEOUT_SETR/W1S0hWrite 1 to enable timeout errors. Reads return the corresponding enable bit's current value.
0ENABLE_PARITY_SETR/W1S0hWrite 1 to enable parity errors. Reads return the corresponding enable bit's current value.

26.2.2.85 MCANERR_AGGR_ENABLE_CLR Register (Offset = 7604h) [Reset = 00000000h]

MCANERR_AGGR_ENABLE_CLR is shown in Figure 26-111 and described in Table 26-105.

Return to the Summary Table.

MCAN Error Aggregator Enable Clear Register

Figure 26-111 MCANERR_AGGR_ENABLE_CLR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE_TIMEOUT_CLRENABLE_PARITY_CLR
R/W-0hR/W1C-0hR/W1C-0h
Table 26-105 MCANERR_AGGR_ENABLE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1ENABLE_TIMEOUT_CLRR/W1C0hWrite 1 to disable timeout errors. Reads return the corresponding enable bit's current value.
0ENABLE_PARITY_CLRR/W1C0hWrite 1 to disable parity errors. Reads return the corresponding enable bit's current value.

26.2.2.86 MCANERR_AGGR_STATUS_SET Register (Offset = 7608h) [Reset = 00000000h]

MCANERR_AGGR_STATUS_SET is shown in Figure 26-112 and described in Table 26-106.

Return to the Summary Table.

MCAN Error Aggregator Status Set Register

Figure 26-112 MCANERR_AGGR_STATUS_SET Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSVBUS_TIMEOUTAGGR_PARITY_ERR
R/W-0hR/WI-0hR/WI-0h
Table 26-106 MCANERR_AGGR_STATUS_SET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-2SVBUS_TIMEOUTR/WI0hAggregator Serial VBUS Timeout Error Status

2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared.
0 No timeout errors have occurred
1 One timeout error has occurred
2 Two timeout errors have occurred
3 Three timeout errors have occurred

A write of a non-zero value to this bit field increments it by the value provided.
1-0AGGR_PARITY_ERRR/WI0hAggregator Parity Error Status

2-bit saturating counter of the number of parity errors that have occurred since last cleared.
0 No parity errors have occurred
1 One parity error has occurred
2 Two parity errors have occurred
3 Three parity errors have occurred

A write of a non-zero value to this bit field increments it by the value provided.

26.2.2.87 MCANERR_AGGR_STATUS_CLR Register (Offset = 760Ch) [Reset = 00000000h]

MCANERR_AGGR_STATUS_CLR is shown in Figure 26-113 and described in Table 26-107.

Return to the Summary Table.

MCAN Error Aggregator Status Clear Register

Figure 26-113 MCANERR_AGGR_STATUS_CLR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSVBUS_TIMEOUTAGGR_PARITY_ERR
R/W-0hR/WD-0hR/WD-0h
Table 26-107 MCANERR_AGGR_STATUS_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-2SVBUS_TIMEOUTR/WD0hAggregator Serial VBUS Timeout Error Status

2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared.
0 No timeout errors have occurred
1 One timeout error has occurred
2 Two timeout errors have occurred
3 Three timeout errors have occurred

A write of a non-zero value to this bit field decrements it by the value provided.
1-0AGGR_PARITY_ERRR/WD0hAggregator Parity Error Status

2-bit saturating counter of the number of parity errors that have occurred since last cleared.
0 No parity errors have occurred
1 One parity error has occurred
2 Two parity errors have occurred
3 Three parity errors have occurred

A write of a non-zero value to this bit field decrements it by the value provided.

26.2.2.88 IIDX Register (Offset = 7820h) [Reset = 00000000h]

IIDX is shown in Figure 26-114 and described in Table 26-108.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, ... IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 26-114 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 26-108 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending.
1h = MCAN Interrupt Line 0 interrupt pending.
2h = MCAN Interrupt Line 1 interrupt pending.
3h = Message RAM SEC (Single Error Correction) interrupt pending.
4h = Message RAM DED (Double Error Detection) interrupt pending.
5h = External Timestamp Counter Overflow interrupt pending.
6h = Clock Stop Wake Up interrupt pending.

26.2.2.89 IMASK Register (Offset = 7828h) [Reset = 00000000h]

IMASK is shown in Figure 26-115 and described in Table 26-109.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 26-115 IMASK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDWAKEUPEXT_TS_CNTR_OVFLDEDSECINTL1INTL0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 26-109 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5WAKEUPR/W0hClock Stop Wake Up interrupt mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
4EXT_TS_CNTR_OVFLR/W0hExternal Timestamp Counter Overflow interrupt mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
3DEDR/W0hMassage RAM DED interrupt mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2SECR/W0hMessage RAM SEC interrupt mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1INTL1R/W0hMCAN Interrupt Line 1 mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0INTL0R/W0hMCAN Interrupt Line 0 mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask

26.2.2.90 RIS Register (Offset = 7830h) [Reset = 00000000h]

RIS is shown in Figure 26-116 and described in Table 26-110.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 26-116 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWAKEUPEXT_TS_CNTR_OVFLDEDSECINTL1INTL0
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 26-110 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5WAKEUPR0hClock Stop Wake Up interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
4EXT_TS_CNTR_OVFLR0hExternal Timestamp Counter Overflow interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
3DEDR0hMessage RAM DED interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
2SECR0hMessage RAM SEC interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
1INTL1R0hMCAN Interrupt Line 1.
0h = Interrupt did not occur
1h = Interrupt occured
0INTL0R0hMCAN Interrupt Line 0.
0h = Interrupt did not occur
1h = Interrupt occured

26.2.2.91 MIS Register (Offset = 7838h) [Reset = 00000000h]

MIS is shown in Figure 26-117 and described in Table 26-111.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 26-117 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWAKEUPEXT_TS_CNTR_OVFLDEDSECINTL1INTL0
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 26-111 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5WAKEUPR0hMasked Clock Stop Wake Up interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
4EXT_TS_CNTR_OVFLR0hMasked External Timestamp Counter Overflow interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
3DEDR0hMasked Message RAM DED interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
2SECR0hMasked Message RAM SEC interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
1INTL1R0hMasked MCAN Interrupt Line 1.
0h = Interrupt did not occur
1h = Interrupt occured
0INTL0R0hMasked MCAN Interrupt Line 0.
0h = Interrupt did not occur
1h = Interrupt occured

26.2.2.92 ISET Register (Offset = 7840h) [Reset = 00000000h]

ISET is shown in Figure 26-118 and described in Table 26-112.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 26-118 ISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDWAKEUPEXT_TS_CNTR_OVFLDEDSECINTL1INTL0
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 26-112 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDW0h
5WAKEUPW0hSet Clock Stop Wake Up interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
4EXT_TS_CNTR_OVFLW0hSet External Timestamp Counter Overflow interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
3DEDW0hSet Message RAM DED interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
2SECW0hSet Message RAM SEC interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
1INTL1W0hSet MCAN Interrupt Line 1.
0h = Writing 0 has no effect
1h = Set Interrupt
0INTL0W0hSet MCAN Interrupt Line 0.
0h = Writing 0 has no effect
1h = Set Interrupt

26.2.2.93 ICLR Register (Offset = 7848h) [Reset = 00000000h]

ICLR is shown in Figure 26-119 and described in Table 26-113.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 26-119 ICLR Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDWAKEUPEXT_TS_CNTR_OVFLDEDSECINTL1INTL0
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 26-113 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDW0h
5WAKEUPW0hClear Clock Stop Wake Up interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
4EXT_TS_CNTR_OVFLW0hClear External Timestamp Counter Overflow interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
3DEDW0hClear Message RAM DED interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
2SECW0hClear Message RAM SEC interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
1INTL1W0hClear MCAN Interrupt Line 1.
0h = Writing 0 has no effect
1h = Clear Interrupt
0INTL0W0hClear MCAN Interrupt Line 0.
0h = Writing 0 has no effect
1h = Clear Interrupt

26.2.2.94 EVT_MODE Register (Offset = 78E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 26-120 and described in Table 26-114.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 26-120 EVT_MODE Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDINT0_CFG
R/W-0hR-0h
Table 26-114 EVT_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1-0INT0_CFGR1hEvent line mode select for event corresponding to [IPSTANDARD.CPU_INT]
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

26.2.2.95 DESC Register (Offset = 78FCh) [Reset = 00000000h]

DESC is shown in Figure 26-121 and described in Table 26-115.

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This register identifies the peripheral and its exact version.

Figure 26-121 DESC Register
31302928272625242322212019181716
MODULEID
R-0h
1514131211109876543210
FEATUREVERRESERVEDMAJREVMINREV
R-0hR-0hR-0hR-0h
Table 26-115 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR940hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERR0hFeature Set for the module *instance*
0h = MCAN module with CAN-FD mode enabled

1h = MCAN module with CAN-FD mode disabled
11-8RESERVEDR0h
7-4MAJREVR0hMajor rev of the IP
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
0h = Smallest value
Fh = Highest possible value

26.2.2.96 MCANSS_CLKEN Register (Offset = 7900h) [Reset = 00000000h]

MCANSS_CLKEN is shown in Figure 26-122 and described in Table 26-116.

Return to the Summary Table.

MCAN module clock (functional clock and Vbusp to access MCAN module MMRs) enable register

Figure 26-122 MCANSS_CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_REQEN
R-0h-0
Table 26-116 MCANSS_CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0CLK_REQEN0hMCAN functional and MCAN/MCANSS MMR clock request enable bit

0h = MCAN module functional clock and Vbusp is not requested.
These clocks are gated to the MCAN module.
1h = Setting this bit requests MCAN module functional clock and Vbusp.
These clocks are not gated to MCAN module.

26.2.2.97 MCANSS_CLKDIV Register (Offset = 7904h) [Reset = 00000000h]

MCANSS_CLKDIV is shown in Figure 26-123 and described in Table 26-117.

Return to the Summary Table.

Needs to go to the Management apperture once available

Figure 26-123 MCANSS_CLKDIV Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDRATIO
R/W-0hR/W-0h
Table 26-117 MCANSS_CLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1-0RATIOR/W0hClock divide ratio specification. Enables configuring clock divide settings for the MCAN functional clock input to the MCAN-SS.
0h (R/W) = Divides input clock by 1
1h (R/W) = Divides input clock by 2
2h (R/W) = Divides input clock by 4
3h (R/W) = Divides input clock by 1

26.2.2.98 MCANSS_CLKCTL Register (Offset = 7908h) [Reset = 00000000h]

MCANSS_CLKCTL is shown in Figure 26-124 and described in Table 26-118.

Return to the Summary Table.

MCANSS clock stop control MMR.
Bus clock for the wrapper MMRs (including this MMR) is not gated by this register settings.

Figure 26-124 MCANSS_CLKCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDWKUP_GLTFLT_EN
R/W-0hR/W-0h
76543210
RESERVEDWAKEUP_INT_ENRESERVEDSTOPREQ
R/W-0hR/W-0hR/W-0hR/W-0h
Table 26-118 MCANSS_CLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8WKUP_GLTFLT_ENR/W0hSetting this bit enables the glitch filter on MCAN RXD input, which wakes up the MCAN controller to exit clock gating.
0h = Disable glitch filter enable on RXD input when MCAN is in clock stop mode (waiting for event on RXD input for clock stop wakeup).
1h = Enable glitch filter enable on RXD input when MCAN is in clock stop mode (waiting for event on RXD input for clock stop wakeup).
7-5RESERVEDR/W0h
4WAKEUP_INT_ENR/W0hThis bit contols enabling or disabling the MCAN IP clock stop wakeup interrupt (when MCANSS_CTRL.WAKEUPREQEN wakeup request is enabled to wakeup MCAN IP upon CAN RXD activity)
0h = Disable MCAN IP clock stop wakeup interrupt
1h = Enable MCAN IP clock stop wakeup interrupt
3-1RESERVEDR/W0h
0STOPREQR/W0hThis bit is used to enable/disable MCAN clock (both host clock and functional clock) gating request.

Note: This bit can be reset by HW by Clock-Stop Wake-up via CAN RX Activity. See spec for more details.

0h = Disable MCAN-SS clock stop request
1h = Enable MCAN-SS clock stop request

26.2.2.99 MCANSS_CLKSTS Register (Offset = 790Ch) [Reset = 00000000h]

MCANSS_CLKSTS is shown in Figure 26-125 and described in Table 26-119.

Return to the Summary Table.

MCANSS clock stop status register to indicate status of clock stop mechanism

Figure 26-125 MCANSS_CLKSTS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCCLKDONE
R-0hR-0h
76543210
RESERVEDSTOPREQ_HW_OVRRESERVEDCLKSTOP_ACKSTS
R-0hR-0hR-0hR-0h
Table 26-119 MCANSS_CLKSTS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8CCLKDONER0hThis bit indicates the status of MCAN contoller clock request from GPRCM.
0h = MCAN controller clock is not available to the MCAN IP.
1h = MCAN controller clock is enabled and available to the MCAN IP.
7-5RESERVEDR0h
4STOPREQ_HW_OVRR0hMCANSS clock stop HW override status bit.

This bit indicates when the MCANSS_CLKCTL.STOPREQ bit has been cleared by HW when a clock-stop wake-up event via CAN RX activity is triggered.
0h = MCANSS_CLKCTL.STOPREQ bit has not been cleared by HW.
1h = MCANSS_CLKCTL.STOPREQ bit has been cleared by HW.
3-1RESERVEDR0h
0CLKSTOP_ACKSTSR0hClock stop acknowledge status from MCAN IP
0h = No clock stop acknowledged.
1h = Clock stop has been acknowledged by MCAN IP
MCAN-SS may be clock gated by stopping both the CAN host and functional clocks.