SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

3.6.2 SYSCTL_REGS Registers

Table 3-24 lists the memory-mapped registers for the SYSCTL_REGS registers. All register offset addresses not listed in Table 3-24 should be considered as reserved locations and the register contents should not be modified.

Table 3-24 SYSCTL_REGS Registers
OffsetAcronymRegister NameSection
800hPWRENIP Enable RegisterGo
804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
814hSTATIP State Register - Read OnlyGo
1020hIIDXSYSCTL interrupt indexGo
1028hIMASKSYSCTL interrupt maskGo
1030hRISSYSCTL raw interrupt statusGo
1038hMISSYSCTL masked interrupt statusGo
1040hISETSYSCTL interrupt setGo
1048hICLRSYSCTL interrupt clearGo
1050hNMIIIDXNMI interrupt indexGo
1060hNMIRISNMI raw interrupt statusGo
1070hNMIISETNMI interrupt setGo
1078hNMIICLRNMI interrupt clearGo
1100hSYSOSCCFGSYSOSC configurationGo
1104hMCLKCFGMain clock (MCLK) configurationGo
1108hHSCLKENHigh-speed clock (HSCLK) source enable/disableGo
110ChHSCLKCFGHigh-speed clock (HSCLK) source selectionGo
1110hHFCLKCLKCFGHigh-frequency clock (HFCLK) configurationGo
1120hSYSPLLCFG0SYSPLL reference and output configurationGo
1124hSYSPLLCFG1SYSPLL reference and feedback dividerGo
1128hSYSPLLPARAM0SYSPLL PARAM0 (load from FACTORY region)Go
112ChSYSPLLPARAM1SYSPLL PARAM1 (load from FACTORY region)Go
1130hSYSPLLPARAM2SYSPLL PARAM2 (load from FACTORY region)Go
1134hSYSPLLLDOCTLSYSPLL LDO CTL (load from FACTORY region)Go
1138hSYSPLLLDOPROGSYSPLL LDO VOUT PROG (load from FACTORY region)Go
113ChGENCLKENGeneral clock enable controlGo
1140hGENCLKCFGGeneral clock configurationGo
1144hPMODECFGPower mode configurationGo
1148hMLDOLPENCFGLDO Configuration ControlGo
1150hFCCFrequency clock counter (FCC) countGo
1154hPMULDOSPARECTLLDO Spare ControlGo
1158hSYSCTL_ECO_REG1Sysctl ECO Reg 1Go
115ChSYSCTL_ECO_REG2Sysctl ECO Reg 2Go
1180hSYSTEMCFGSystem configurationGo
1184hSRAMCFGSystem SRAM configurationGo
1200hWRITELOCKSYSCTL register write lockoutGo
1204hCLKSTATUSClock module (CKM) statusGo
1208hSYSSTATUSSystem status informationGo
1220hRSTCAUSEReset causeGo
1300hRESETLEVELReset level for application-triggered reset commandGo
1304hRESETCMDExecute an application-triggered reset commandGo
1310hSYSOSCFCLCTLSYSOSC frequency correction loop (FCL) ROSC enableGo
131ChSHDNIORELSHUTDOWN IO release controlGo
1320hEXRSTPINDisable the reset function of the NRST pinGo
1324hSYSSTATUSCLRClear sticky bits of SYSSTATUSGo
1328hSWDJCFGDisable the SWD/JTAG function on the SWD/JTAG pinsGo
132ChFCCCMDFrequency clock counter start captureGo
1400hSHUTDNSTORE0Shutdown storage memory (byte 0)Go
1404hSHUTDNSTORE1Shutdown storage memory (byte 1)Go
1408hSHUTDNSTORE2Shutdown storage memory (byte 2)Go
140ChSHUTDNSTORE3Shutdown storage memory (byte 3)Go
1410hADCSEQFRCGBADC Global Sequence ForceGo
1414hADCSEQFRCGBSELADC Global Sequence Force SelectGo
1418hM33SPARESOCLOCK1M33C1 Spare SOC LOCK Reg 1Go
141ChM33SPARESOCLOCK2M33C1 Spare SOC LOCK Reg 2Go
1420hSYSCTL_READ_REGSysctl read only RegGo
1424hPWREN_MCPERIPHRegister to control the power stateGo
1428hRSTCTL_ASSERT_MCPERIPHrstctl assert register to control reset assertion - Write Only Register, Always Read as 0Go
142ChRSTCTL_CLEAR_MCPERIPHrstctl clear register to control reset de-assertion - Write Only Register, Always Read as 0Go
1430hSTAT_MCPERIPHIP State Register - Read OnlyGo
1434hPWREN_SYSPERIPHRegister to control the power stateGo
1438hRSTCTL_ASSERT_SYSPERIPHrstcl assert Register - Write Only Register, Always Read as 0Go
143ChRSTCTL_CLEAR_SYSPERIPHrstctl clear register to control reset de-assertion - Write Only Register, Always Read as 0Go
1440hSTAT_SYSPERIPHIP State Register - Read OnlyGo
1444hCMPHPMXSELBits to select one of the many sources on CompHP inputs. Refer to Pinmux diagram for details.Go
144ChCMPLPMXSELBits to select one of the many sources on CompLP inputs. Refer to Pinmux diagram for details.Go
1450hCMPHNMXSELBits to select one of the many sources on CompHN inputs. Refer to Pinmux diagram for details.Go
1454hCMPLNMXSELBits to select one of the many sources on CompLN inputs. Refer to Pinmux diagram for details.Go
1458hTSNSCFGTemperature Sensor Config RegisterGo
145ChTSNSSCTLTemperature Sensor Control RegisterGo
1460hPGACONFIGPGA Configuration RegisterGo
1464hREFCONFIGAReference Configuration RegsiterGo
1468hINTERNALTESTCTLInternal Test Node Control RegisterGo
146ChI2VCTLI2V Logic ControlGo
1470hADCDACLOOPBACKNot used in AM13Go
1474hXTALCRXTAL Control RegisterGo
1478hXTALCR2XTAL Control Register for pad initGo
147ChX1CNTx1cnt status registerGo
1480hCMPSSCTLCMPSS control registerGo
1484hCMPSSDACBUFCONFIGConfig bits for CMPSS DAC bufferGo
1488hANAREFCTLAnalog Reference SelectGo
148ChPERCLKCRPWM Time Base Clock syncGo
1490hADC_MMR_OVRD_CTLADC MMR Override control register for DFT: Control ADC enable overrideGo
1494hADC_MMR_OVRD_VALADC MMR Override value register for DFT : Value of ADC enable overrideGo
1498hVREGCONFIGDEBUGVREG Configuration Debug RegisterGo
149ChVREGCONFIGDFTVREG Configuration DFT RegisterGo
14A0hAM13SPAREIREFENSOCLOCKAM13 Spare IREFEN SOC LOCK RegGo
14A4hAM13SPARESOCLOCK2AM13 Spare SOC LOCK Reg 2Go
14A8hAM13SPARESOCLOCK3AM13 Spare SOC LOCK Reg 3Go
14AChAM13SPARESOCLOCK4AM13 Spare SOC LOCK Reg 4Go
2800hPWRENIP Enable RegisterGo
2804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
2814hSTATIP State Register - Read OnlyGo
4800hPWRENIP Enable RegisterGo
4804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
4814hSTATIP State Register - Read OnlyGo
000D0800hPWRENIP Enable RegisterGo
000D0804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
000D0814hSTATIP State Register - Read OnlyGo
000E8800hPWRENIP Enable RegisterGo
000E8804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
000E8814hSTATIP State Register - Read OnlyGo
000F0800hPWRENIP Enable RegisterGo
000F0804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
000F0814hSTATIP State Register - Read OnlyGo
000F2800hPWRENIP Enable RegisterGo
000F2804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
000F2814hSTATIP State Register - Read OnlyGo
000F4800hPWRENIP Enable RegisterGo
000F4804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
000F4814hSTATIP State Register - Read OnlyGo
000F6800hPWRENIP Enable RegisterGo
000F6804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
000F6814hSTATIP State Register - Read OnlyGo
00116800hPWRENIP Enable RegisterGo
00116804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00116814hSTATIP State Register - Read OnlyGo
00180800hPWRENIP Enable RegisterGo
00180804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00180814hSTATIP State Register - Read OnlyGo
00188800hPWRENIP Enable RegisterGo
00188804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00188814hSTATIP State Register - Read OnlyGo
001B0800hPWRENIP Enable RegisterGo
001B0804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
001B0814hSTATIP State Register - Read OnlyGo
001B2800hPWRENIP Enable RegisterGo
001B2804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
001B2814hSTATIP State Register - Read OnlyGo
00630800hPWRENIP Enable RegisterGo
00630804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00630814hSTATIP State Register - Read OnlyGo
00632800hPWRENIP Enable RegisterGo
00632804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00632814hSTATIP State Register - Read OnlyGo
00634800hPWRENIP Enable RegisterGo
00634804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00634814hSTATIP State Register - Read OnlyGo
00670800hPWRENIP Enable RegisterGo
00670804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00670814hSTATIP State Register - Read OnlyGo
00672800hPWRENIP Enable RegisterGo
00672804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00672814hSTATIP State Register - Read OnlyGo
00674800hPWRENIP Enable RegisterGo
00674804hRSTCTLPower Control Register - Write Only Register, Always Read as 0Go
00674814hSTATIP State Register - Read OnlyGo

Complex bit access types are encoded to fit into small table cells. Table 3-25 shows the codes that are used for access types in this section.

Table 3-25 SYSCTL_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value

3.6.2.1 PWREN Register (Offset = 800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-11 and described in Table 3-26.

Return to the Summary Table.

IP Enable Register

Figure 3-11 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-26 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.2 RSTCTL Register (Offset = 804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-12 and described in Table 3-27.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-12 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-27 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.3 STAT Register (Offset = 814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-13 and described in Table 3-28.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-13 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-28 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.4 IIDX Register (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 3-14 and described in Table 3-29.

Return to the Summary Table.

SYSCTL interrupt index

Figure 3-14 IIDX Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 3-29 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2-0STATR0hThe SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.
0h = No interrupt pending
1h = LFOSCGOOD interrupt pending
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7

3.6.2.5 IMASK Register (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 3-15 and described in Table 3-30.

Return to the Summary Table.

SYSCTL interrupt mask

Figure 3-15 IMASK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDHSCLKGOODSYSPLLGOODHFCLKGOODFLASHSECLFOSCGOOD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-30 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR/W0h
6HSCLKGOODR/W0hHSCLK GOOD
0h = 0
1h = 1
5SYSPLLGOODR/W0hSYSPLL GOOD
0h = 0
1h = 1
4HFCLKGOODR/W0hHFCLK GOOD
0h = 0
1h = 1
2FLASHSECR/W0hFlash Single Error Correct
0h = 0
1h = 1
0LFOSCGOODR/W0hEnable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.
0h = Interrupt disabled
1h = Interrupt enabled

3.6.2.6 RIS Register (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 3-16 and described in Table 3-31.

Return to the Summary Table.

SYSCTL raw interrupt status

Figure 3-16 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDHSCLKGOODSYSPLLGOODHFCLKGOODFLASHSECLFOSCGOOD
R-0hR-0hR-0hR-0hR-0hR-0h
Table 3-31 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0h
6HSCLKGOODR0hHSCLK GOOD
0h = 0
1h = 1
5SYSPLLGOODR0hSYSPLL GOOD
0h = 0
1h = 1
4HFCLKGOODR0hHFCLK GOOD
0h = 0
1h = 1
2FLASHSECR0hFlash Single Error Correct
0h = 0
1h = 1
0LFOSCGOODR0hRaw status of the LFOSCGOOD interrupt.
0h = No interrupt pending
1h = Interrupt pending

3.6.2.7 MIS Register (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 3-17 and described in Table 3-32.

Return to the Summary Table.

SYSCTL masked interrupt status

Figure 3-17 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDHSCLKGOODSYSPLLGOODHFCLKGOODFLASHSECLFOSCGOOD
R-0hR-0hR-0hR-0hR-0hR-0h
Table 3-32 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0h
6HSCLKGOODR0hHSCLK GOOD
0h = 0
1h = 1
5SYSPLLGOODR0hSYSPLL GOOD
0h = 0
1h = 1
4HFCLKGOODR0hHFCLK GOOD
0h = 0
1h = 1
2FLASHSECR0hFlash Single Error Correct
0h = 0
1h = 1
0LFOSCGOODR0hMasked status of the LFOSCGOOD interrupt.
0h = No interrupt pending
1h = Interrupt pending

3.6.2.8 ISET Register (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 3-18 and described in Table 3-33.

Return to the Summary Table.

SYSCTL interrupt set

Figure 3-18 ISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDHSCLKGOODSYSPLLGOODHFCLKGOODFLASHSECLFOSCGOOD
W-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
Table 3-33 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDW0h
6HSCLKGOODW1S0hHSCLK GOOD
0h = 0
1h = 1
5SYSPLLGOODW1S0hSYSPLL GOOD
0h = 0
1h = 1
4HFCLKGOODW1S0hHFCLK GOOD
0h = 0
1h = 1
2FLASHSECW1S0hFlash Single Error Correct
0h = 0
1h = 1
0LFOSCGOODW1S0hSet the LFOSCGOOD interrupt.
0h = Writing 0h has no effect
1h = Set interrupt

3.6.2.9 ICLR Register (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 3-19 and described in Table 3-34.

Return to the Summary Table.

SYSCTL interrupt clear

Figure 3-19 ICLR Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDHSCLKGOODSYSPLLGOODHFCLKGOODFLASHSECLFOSCGOOD
W-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
Table 3-34 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDW0h
6HSCLKGOODW1C0hHSCLK GOOD
0h = 0
1h = 1
5SYSPLLGOODW1C0hSYSPLL GOOD
0h = 0
1h = 1
4HFCLKGOODW1C0hHFCLK GOOD
0h = 0
1h = 1
2FLASHSECW1C0hFlash Single Error Correct
0h = 0
1h = 1
0LFOSCGOODW1C0hClear the LFOSCGOOD interrupt.
0h = Writing 0h has no effect
1h = Clear interrupt

3.6.2.10 NMIIIDX Register (Offset = 1050h) [Reset = 00000000h]

NMIIIDX is shown in Figure 3-20 and described in Table 3-35.

Return to the Summary Table.

NMI interrupt index

Figure 3-20 NMIIIDX Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 3-35 NMIIIDX Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2-0STATR0hThe NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register.
0h = No NMI pending
1h = Reserved
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7

3.6.2.11 NMIRIS Register (Offset = 1060h) [Reset = 00000000h]

NMIRIS is shown in Figure 3-21 and described in Table 3-36.

Return to the Summary Table.

NMI raw interrupt status

Figure 3-21 NMIRIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSYSMEMACCTMUROMPARSRAMPARFLASHDEDSECURITYWWDT0
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-36 NMIRIS Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0h
6SYSMEMACCR0hSYSMEM Access error
0h = 0
1h = 1
5TMUROMPARR0hTMU ROM Parity error
0h = 0
1h = 1
4SRAMPARR0hSRAM Parity Error Detect
0h = 0
1h = 1
3FLASHDEDR0hFlash Double Error Detect
0h = 0
1h = 1
2SECURITYR0hSecurity Fault
0h = 0
1h = 1
1WWDT0R0hWatch Dog 0 Fault
0h = 0
1h = 1

3.6.2.12 NMIISET Register (Offset = 1070h) [Reset = 00000000h]

NMIISET is shown in Figure 3-22 and described in Table 3-37.

Return to the Summary Table.

NMI interrupt set

Figure 3-22 NMIISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDSYSMEMACCTMUROMPARSRAMPARFLASHDEDSECURITYWWDT0
W-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
Table 3-37 NMIISET Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDW0h
6SYSMEMACCW1S0hSYSMEM Access error
0h = 0
1h = 1
5TMUROMPARW1S0hTMU ROM Parity error
0h = 0
1h = 1
4SRAMPARW1S0hSRAM Parity Error Detect
0h = 0
1h = 1
3FLASHDEDW1S0hFlash Double Error Detect
0h = 0
1h = 1
2SECURITYW1S0hSecurity Fault
0h = 0
1h = 1
1WWDT0W1S0hWatch Dog 0 Fault
0h = 0
1h = 1

3.6.2.13 NMIICLR Register (Offset = 1078h) [Reset = 00000000h]

NMIICLR is shown in Figure 3-23 and described in Table 3-38.

Return to the Summary Table.

NMI interrupt clear

Figure 3-23 NMIICLR Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDSYSMEMACCTMUROMPARSRAMPARFLASHDEDSECURITYWWDT0
W-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
Table 3-38 NMIICLR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDW0h
6SYSMEMACCW1C0hSYSMEM Access error
0h = 0
1h = 1
5TMUROMPARW1C0hTMU ROM Parity error
0h = 0
1h = 1
4SRAMPARW1C0hSRAM Parity Error Detect
0h = 0
1h = 1
3FLASHDEDW1C0hFlash Double Error Detect
0h = 0
1h = 1
2SECURITYW1C0hSecurity Fault
0h = 0
1h = 1
1WWDT0W1C0hWatch Dog 0 Fault
0h = 0
1h = 1

3.6.2.14 SYSOSCCFG Register (Offset = 1100h) [Reset = 0002XXXXh]

SYSOSCCFG is shown in Figure 3-24 and described in Table 3-39.

Return to the Summary Table.

SYSOSC configuration

Figure 3-24 SYSOSCCFG Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDFASTCPUEVENTBLOCKASYNCALL
R/W-0hR/W-1hR/W-0h
15141312111098
RESERVEDDISABLE
R/W-XhR-0h
76543210
RESERVEDFREQ
R/W-XhR/W-0h
Table 3-39 SYSOSCCFG Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0h
17FASTCPUEVENTR/W1hif disabled CPU will not wakeup and continue in STANDBY
0h = An interrupt to the CPU will not assert a fast clock request
1h = An interrupt to the CPU will assert a fast clock request
16BLOCKASYNCALLR/W0hBLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.
0h = Asynchronous fast clock requests are controlled by the requesting peripheral
1h = All asynchronous fast clock requests are blocked
15-11RESERVEDR/WXh
10DISABLER0hDISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.
0h = Do not disable SYSOSC
1h = Disable SYSOSC immediately and source MCLK and ULPCLK from LFCLK
7-2RESERVEDR/WXh
1-0FREQR/W0hTarget operating frequency for the system oscillator (SYSOSC)
0h = Base frequency (32MHz)
1h = Low frequency (4MHz)

3.6.2.15 MCLKCFG Register (Offset = 1104h) [Reset = 07XXX2X0h]

MCLKCFG is shown in Figure 3-25 and described in Table 3-40.

Return to the Summary Table.

Main clock (MCLK) configuration

Figure 3-25 MCLKCFG Register
3130292827262524
RESERVEDMCLKDIVCFG
R/W-0hR/W-7h
2322212019181716
RESERVEDMCLKDEADCHKSTOPCLKSTBYUSELFCLKRESERVEDUSEHSCLK
R/W-XhR/W-0hR/W-0hR-0hR/W-XhR/W-0h
15141312111098
RESERVED
R/W-Xh
76543210
RESERVED
R/W-Xh
Table 3-40 MCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR/W0h
26-24MCLKDIVCFGR/W7hMCLK Divider Configuration bits [1:0] are defined as MCLK4 is Bypass, MCLK2 is Bypass
0h = MCLK: No Divide, MCLK2: No Divide, MCLK4: No Divide
1h = MCLK: No Divide, MCLK2: No Divide, MCLK4: Divide MCLK by 2
3h = MCLK: No Divide, MCLK2: No Divide, MCLK4: Divide MCLK by 4
5h = MCLK: No Divide, MCLK2: Divide MCLK by 2, MCLK4: Divide MCLK by 2
7h = MCLK: No Divide, MCLK2: Divide MCLK by 2, MCLK4: MCLK by 4
23RESERVEDR/WXh
22MCLKDEADCHKR/W0hMCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled.
0h = The MCLK dead check monitor is disabled
1h = The MCLK dead check monitor is enabled
21STOPCLKSTBYR/W0hSTOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1). When set, ULPCLK and LFCLK are disabled to all peripherals in STANDBY mode, with the exception of TIMG0 and TIMG1 which continue to run. Wake-up is only possible via an asynchronous fast clock request.
0h = ULPCLK/LFCLK runs to all PD0 peripherals in STANDBY mode
1h = ULPCLK/LFCLK is disabled to all peripherals in STANDBY mode except TIMG0 and TIMG1
20USELFCLKR0h LFCLK is not an MCLK sourcei in PD1, tied 0.
0h = MCLK will not use the low frequency clock (LFCLK)
1h = MCLK will use the low frequency clock (LFCLK)
19-17RESERVEDR/WXh
16USEHSCLKR/W0hUSEHSCLK, together with USELFCLK, sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes.
0h = MCLK will not use the high speed clock (HSCLK)
1h = MCLK will use the high speed clock (HSCLK) in RUN and SLEEP mode
15-13RESERVEDR/WXh
7-4RESERVEDR/WXh

3.6.2.16 HSCLKEN Register (Offset = 1108h) [Reset = 0000XXXXh]

HSCLKEN is shown in Figure 3-26 and described in Table 3-41.

Return to the Summary Table.

High-speed clock (HSCLK) source enable/disable

Figure 3-26 HSCLKEN Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDUSEEXTHFCLK
R/W-0hR/W-0h
15141312111098
RESERVEDSYSPLLEN
R/W-XhR/W-0h
76543210
RESERVED
R/W-Xh
Table 3-41 HSCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/W0h
16USEEXTHFCLKR/W0hUSEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK.
0h = Use XTAL as the HFCLK source
1h = Use the HFCLK_IN digital clock input as the HFCLK source
15-9RESERVEDR/WXh
8SYSPLLENR/W0hSYSPLLEN enables or disables the system phase-lock loop (SYSPLL).
0h = Disable the SYSPLL
1h = Enable the SYSPLL
7-1RESERVEDR/WXh

3.6.2.17 HSCLKCFG Register (Offset = 110Ch) [Reset = 00000000h]

HSCLKCFG is shown in Figure 3-27 and described in Table 3-42.

Return to the Summary Table.

High-speed clock (HSCLK) source selection

Figure 3-27 HSCLKCFG Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDHSCLKSEL
R/W-0hR/W-0h
Table 3-42 HSCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0HSCLKSELR/W0hHSCLKSEL selects the HSCLK source (SYSPLL or HFCLK).
0h = HSCLK is sourced from the SYSPLL
1h = HSCLK is sourced from the HFCLK

3.6.2.18 HFCLKCLKCFG Register (Offset = 1110h) [Reset = 1XXXXX00h]

HFCLKCLKCFG is shown in Figure 3-28 and described in Table 3-43.

Return to the Summary Table.

High-frequency clock (HFCLK) configuration

Figure 3-28 HFCLKCLKCFG Register
3130292827262524
RESERVEDHFCLKFLTCHKRESERVED
R/W-0hR/W-1hR/W-XXXh
2322212019181716
RESERVED
R/W-XXXh
15141312111098
RESERVEDRESERVED
R/W-XXXhR/W-Xh
76543210
XTALTIME
R/W-0h
Table 3-43 HFCLKCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28HFCLKFLTCHKR/W1hHFCLKFLTCHK enables or disables the HFCLK startup monitor.
0h = HFCLK startup is not checked
1h = HFCLK startup is checked
27-14RESERVEDR/WXXXh
11-8RESERVEDR/WXh
7-0XTALTIMER/W0hXTALTIME specifies the XTAL startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK), XTAL will be checked after this time expires.
0h = Minimum startup time (approximatly zero)
FFh = Maximum startup time (approximatly 16.32ms)

3.6.2.19 SYSPLLCFG0 Register (Offset = 1120h) [Reset = 000000XXh]

SYSPLLCFG0 is shown in Figure 3-29 and described in Table 3-44.

Return to the Summary Table.

SYSPLL reference and output configuration

Figure 3-29 SYSPLLCFG0 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RDIVCLK1RDIVCLK0
R/W-0hR/W-0h
76543210
RESERVEDENABLECLK1ENABLECLK0RESERVEDSYSPLLREF
R/W-XhR/W-1hR/W-1hR/W-XhR/W-0h
Table 3-44 SYSPLLCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
15-12RDIVCLK1R/W0hRDIVCLK1 sets the final divider for the SYSPLLCLK1 output.
0h = SYSPLLCLK1 is divided by 2
1h = SYSPLLCLK1 is divided by 4
2h = SYSPLLCLK1 is divided by 6
3h = SYSPLLCLK1 is divided by 8
4h = SYSPLLCLK1 is divided by 10
5h = SYSPLLCLK1 is divided by 12
6h = SYSPLLCLK1 is divided by 14
7h = SYSPLLCLK1 is divided by 16
8h = SYSPLLCLK1 is divided by 18
9h = SYSPLLCLK1 is divided by 20
Ah = SYSPLLCLK1 is divided by 22
Bh = SYSPLLCLK1 is divided by 24
Ch = SYSPLLCLK1 is divided by 26
Dh = SYSPLLCLK1 is divided by 28
Eh = SYSPLLCLK1 is divided by 30
Fh = SYSPLLCLK1 is divided by 32
11-8RDIVCLK0R/W0hRDIVCLK0 sets the final divider for the SYSPLLCLK0 output.
0h = SYSPLLCLK0 is divided by 2
1h = SYSPLLCLK0 is divided by 4
2h = SYSPLLCLK0 is divided by 6
3h = SYSPLLCLK0 is divided by 8
4h = SYSPLLCLK0 is divided by 10
5h = SYSPLLCLK0 is divided by 12
6h = SYSPLLCLK0 is divided by 14
7h = SYSPLLCLK0 is divided by 16
8h = SYSPLLCLK0 is divided by 18
9h = SYSPLLCLK0 is divided by 20
Ah = SYSPLLCLK0 is divided by 22
Bh = SYSPLLCLK0 is divided by 24
Ch = SYSPLLCLK0 is divided by 26
Dh = SYSPLLCLK0 is divided by 28
Eh = SYSPLLCLK0 is divided by 30
Fh = SYSPLLCLK0 is divided by 32
7RESERVEDR/WXh
5ENABLECLK1R/W1hENABLECLK1 enables or disables the SYSPLLCLK1 output.
0h = SYSPLLCLK1 is disabled
1h = SYSPLLCLK1 is enabled
4ENABLECLK0R/W1hENABLECLK0 enables or disables the SYSPLLCLK0 output.
0h = SYSPLLCLK0 is disabled
1h = SYSPLLCLK0 is enabled
3-2RESERVEDR/WXh
0SYSPLLREFR/W0hSYSPLLREF selects the system PLL (SYSPLL) reference clock source.
0h = SYSPLL reference is SYSOSC
1h = SYSPLL reference is HFCLK

3.6.2.20 SYSPLLCFG1 Register (Offset = 1124h) [Reset = 000023XXh]

SYSPLLCFG1 is shown in Figure 3-30 and described in Table 3-45.

Return to the Summary Table.

SYSPLL reference and feedback divider

Figure 3-30 SYSPLLCFG1 Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDQDIVRESERVEDPDIV
R/W-0hR/W-23hR/W-XhR/W-0h
Table 3-45 SYSPLLCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W0h
14-8QDIVR/W23hQDIV selects the SYSPLL feedback path divider.
0h = Divide-by-one is not a valid QDIV option
1h = Feedback path is divided by 2
7Eh = Feedback path is divided by 127 (0x7E)
7-2RESERVEDR/WXh
1-0PDIVR/W0hPDIV selects the SYSPLL reference clock prescale divider.
0h = SYSPLLREF is not divided
1h = SYSPLLREF is divided by 2
2h = SYSPLLREF is divided by 4
3h = SYSPLLREF is divided by 8

3.6.2.21 SYSPLLPARAM0 Register (Offset = 1128h) [Reset = X1XAX0X0h]

SYSPLLPARAM0 is shown in Figure 3-31 and described in Table 3-46.

Return to the Summary Table.

SYSPLL PARAM0 (load from FACTORY region)

Figure 3-31 SYSPLLPARAM0 Register
3130292827262524
CAPBOVERRIDERESERVEDCAPBVAL
R/W-1hR/W-XhR/W-1h
2322212019181716
RESERVEDCPCURRENT
R/W-XhR/W-Ah
15141312111098
RESERVEDSTARTTIMELP
R/W-XhR/W-0h
76543210
RESERVEDSTARTTIME
R/W-XhR/W-0h
Table 3-46 SYSPLLPARAM0 Register Field Descriptions
BitFieldTypeResetDescription
31CAPBOVERRIDER/W1hCAPBOVERRIDE controls the override for Cap B
0h = Cap B override disabled
1h = Cap B override enabled
30-29RESERVEDR/WXh
28-24CAPBVALR/W1hOverride value for Cap B
23-22RESERVEDR/WXh
21-16CPCURRENTR/WAhCharge pump current
15RESERVEDR/WXh
14-8STARTTIMELPR/W0hStartup time from low power mode exit to locked clock, in 1us resolution
7RESERVEDR/WXh
6-0STARTTIMER/W0hStartup time from enable to locked clock, in 1us resolution

3.6.2.22 SYSPLLPARAM1 Register (Offset = 112Ch) [Reset = 0FXX01XFh]

SYSPLLPARAM1 is shown in Figure 3-32 and described in Table 3-47.

Return to the Summary Table.

SYSPLL PARAM1 (load from FACTORY region)

Figure 3-32 SYSPLLPARAM1 Register
31302928272625242322212019181716
LPFRESCRESERVEDLPFRESA
R/W-FhR/W-XhR/W-1h
1514131211109876543210
LPFRESARESERVEDLPFCAPA
R/W-1hR/W-XhR/W-Fh
Table 3-47 SYSPLLPARAM1 Register Field Descriptions
BitFieldTypeResetDescription
31-24LPFRESCR/WFhLoop filter Res C
23-18RESERVEDR/WXh
17-8LPFRESAR/W1hLoop filter Res A
7-5RESERVEDR/WXh
4-0LPFCAPAR/WFhLoop filter Cap A

3.6.2.23 SYSPLLPARAM2 Register (Offset = 1130h) [Reset = 0000000Xh]

SYSPLLPARAM2 is shown in Figure 3-33 and described in Table 3-48.

Return to the Summary Table.

SYSPLL PARAM2 (load from FACTORY region)

Figure 3-33 SYSPLLPARAM2 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRNGFIXVCOIBIASCFGRESERVEDLPFCAPC
R/W-0hR/W-1hR/W-XhR/W-0h
Table 3-48 SYSPLLPARAM2 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3RNGFIXVCOIBIASCFGR/W1h0 value for Temperature Compensation R addition
2RESERVEDR/WXh
1-0LPFCAPCR/W0hLoop filter Cap C

3.6.2.24 SYSPLLLDOCTL Register (Offset = 1134h) [Reset = 00000000h]

SYSPLLLDOCTL is shown in Figure 3-34 and described in Table 3-49.

Return to the Summary Table.

SYSPLL LDO CTL (load from FACTORY region)

Figure 3-34 SYSPLLLDOCTL Register
313029282726252423222120191817161514131211109876543210
RESERVEDLDOCTLLOWV
R/W-0hR/W-0h
Table 3-49 SYSPLLLDOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0LDOCTLLOWVR/W0hLDO Configurability

3.6.2.25 SYSPLLLDOPROG Register (Offset = 1138h) [Reset = 00000004h]

SYSPLLLDOPROG is shown in Figure 3-35 and described in Table 3-50.

Return to the Summary Table.

SYSPLL LDO VOUT PROG (load from FACTORY region)

Figure 3-35 SYSPLLLDOPROG Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDLDOVOUTPROGLOWV
R/W-0hR/W-4h
Table 3-50 SYSPLLLDOPROG Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0LDOVOUTPROGLOWVR/W4hHPLL LDO Vout Prog

3.6.2.26 GENCLKEN Register (Offset = 113Ch) [Reset = 000000XXh]

GENCLKEN is shown in Figure 3-36 and described in Table 3-51.

Return to the Summary Table.

General clock enable control

Figure 3-36 GENCLKEN Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
CANEXTDIVENEXTDIVCANMCLKEXTDIVENEXTDIVMCLK
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDEXCLKEN
R/W-XhR/W-XhR/W-0h
Table 3-51 GENCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR/W0h
15CANEXTDIVENR/W0hCANEXTDIVEN enables or disables the divider function of the PLL Source to CAN.
0h = CLock divider is disabled (passthrough, EXTDIVCAN is not applied)
1h = Clock divider is enabled (EXTDIVCAN is applied)
14-12EXTDIVCANR/W0hEXTDIVCAN selects the divider value for the divider for the PLL Source to CAN.
0h = CLK_OUT source is divided by 2
1h = CLK_OUT source is divided by 4
2h = CLK_OUT source is divided by 6
3h = CLK_OUT source is divided by 8
4h = CLK_OUT source is divided by 10
5h = CLK_OUT source is divided by 12
6h = CLK_OUT source is divided by 14
7h = CLK_OUT source is divided by 16
11MCLKEXTDIVENR/W0hMCLKEXTDIVEN enables or disables the divider function of the PLL Source to MCLK.
0h = CLock divider is disabled (passthrough, EXTDIVMCLK is not applied)
1h = Clock divider is enabled (EXTDIVMCLK is applied)
10-8EXTDIVMCLKR/W0hEXTDIVMCLK selects the divider value for the divider for the PLL Source MCLK.
0h = CLK_OUT source is divided by 2
1h = CLK_OUT source is divided by 4
2h = CLK_OUT source is divided by 6
3h = CLK_OUT source is divided by 8
4h = CLK_OUT source is divided by 10
5h = CLK_OUT source is divided by 12
6h = CLK_OUT source is divided by 14
7h = CLK_OUT source is divided by 16
7-5RESERVEDR/WXh
3-1RESERVEDR/WXh
0EXCLKENR/W0hEXCLKEN enables the CLK_OUT external clock output block.
0h = CLK_OUT block is disabled
1h = CLK_OUT block is enabled

3.6.2.27 GENCLKCFG Register (Offset = 1140h) [Reset = 00000X0Xh]

GENCLKCFG is shown in Figure 3-37 and described in Table 3-52.

Return to the Summary Table.

General clock configuration

Figure 3-37 GENCLKCFG Register
3130292827262524
RESERVEDFCCTRIGCNT
R/W-0hR/W-0h
2322212019181716
FCCLVLTRIGFCCTRIGSRCFCCSELCLK
R/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDCANCLKSRC
R/W-XhR/W-0h
76543210
EXCLKDIVENEXCLKDIVVALRESERVEDEXCLKSRC
R/W-0hR/W-0hR/W-XhR/W-0h
Table 3-52 GENCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
28-24FCCTRIGCNTR/W0hFCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified.
21FCCLVLTRIGR/W0hFCCLVLTRIG selects the frequency clock counter (FCC) trigger mode.
0h = Rising edge to rising edge triggered
1h = Level triggered
20FCCTRIGSRCR/W0hFCCTRIGSRC selects the frequency clock counter (FCC) trigger source.
0h = FCC trigger is the external pin
1h = FCC trigger is the LFCLK
19-16FCCSELCLKR/W0hFCCSELCLK selectes the frequency clock counter (FCC) clock source.
0h = FCC clock is MCLK/4
1h = FCC clock is SYSOSC
2h = FCC clock is HFCLK
3h = FCC clock is the CLK_OUT selection
4h = FCC clock is SYSPLLCLK0
5h = FCC clock is SYSPLLCLK1
6h = Reserved
7h = FCC clock is the FCCIN external input
11-10RESERVEDR/WXh
8CANCLKSRCR/W0hCANCLKSRC selects the CANCLK source.
0h = CANCLK source is HFCLK
1h = CANCLK source is SYSPLLCLK
7EXCLKDIVENR/W0hEXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block.
0h = CLock divider is disabled (passthrough, EXCLKDIVVAL is not applied)
1h = Clock divider is enabled (EXCLKDIVVAL is applied)
6-4EXCLKDIVVALR/W0hEXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block.
0h = CLK_OUT source is divided by 2
1h = CLK_OUT source is divided by 4
2h = CLK_OUT source is divided by 6
3h = CLK_OUT source is divided by 8
4h = CLK_OUT source is divided by 10
5h = CLK_OUT source is divided by 12
6h = CLK_OUT source is divided by 14
7h = CLK_OUT source is divided by 16
3RESERVEDR/WXh
2-0EXCLKSRCR/W0hEXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled
0h = CLK_OUT is SYSOSC
1h = CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled)
2h = CLK_OUT is LFCLK
3h = CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled)
4h = CLK_OUT is HFCLK
5h = CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be <=48MHz)

3.6.2.28 PMODECFG Register (Offset = 1144h) [Reset = 00000000h]

PMODECFG is shown in Figure 3-38 and described in Table 3-53.

Return to the Summary Table.

Power mode configuration

Figure 3-38 PMODECFG Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDDSLEEP
R/W-0hR/W-0h
Table 3-53 PMODECFG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1-0DSLEEPR/W0hDSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU.
0h = STOP mode is entered
1h = STANDBY mode is entered
2h = SHUTDOWN mode is entered
3h = Reserved

3.6.2.29 MLDOLPENCFG Register (Offset = 1148h) [Reset = 000000XXh]

MLDOLPENCFG is shown in Figure 3-39 and described in Table 3-54.

Return to the Summary Table.

LDO Configuration Control

Figure 3-39 MLDOLPENCFG Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCVLODIS
R/W-XhR/W-0h
Table 3-54 MLDOLPENCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
7-1RESERVEDR/WXh
0CVLODISR/W0hControl to disable lowering the core voltage for STOP and STANDBY
0h = Lower Core Voltage for STOP and STANDBY mode
1h = Do Not Lower Core Voltage for STOP and STANDBY mode to provide faster wakeup

3.6.2.30 FCC Register (Offset = 1150h) [Reset = 00000000h]

FCC is shown in Figure 3-40 and described in Table 3-55.

Return to the Summary Table.

Frequency clock counter (FCC) count

Figure 3-40 FCC Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR-0h
Table 3-55 FCC Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21-0DATAR0hFrequency clock counter (FCC) count value.

3.6.2.31 PMULDOSPARECTL Register (Offset = 1154h) [Reset = 00000000h]

PMULDOSPARECTL is shown in Figure 3-41 and described in Table 3-56.

Return to the Summary Table.

LDO Spare Control

Figure 3-41 PMULDOSPARECTL Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVED
R/W-0h
Table 3-56 PMULDOSPARECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h

3.6.2.32 SYSCTL_ECO_REG1 Register (Offset = 1158h) [Reset = 00000000h]

SYSCTL_ECO_REG1 is shown in Figure 3-42 and described in Table 3-57.

Return to the Summary Table.

Sysctl ECO Reg 1

Figure 3-42 SYSCTL_ECO_REG1 Register
313029282726252423222120191817161514131211109876543210
ecoreg
R/W-0h
Table 3-57 SYSCTL_ECO_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ecoregR/W0hECO Reg 1 for M33

3.6.2.33 SYSCTL_ECO_REG2 Register (Offset = 115Ch) [Reset = 00000000h]

SYSCTL_ECO_REG2 is shown in Figure 3-43 and described in Table 3-58.

Return to the Summary Table.

Sysctl ECO Reg 2

Figure 3-43 SYSCTL_ECO_REG2 Register
313029282726252423222120191817161514131211109876543210
ecoreg
R/W-0h
Table 3-58 SYSCTL_ECO_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31-0ecoregR/W0hECO Reg 2 for M33

3.6.2.34 SYSTEMCFG Register (Offset = 1180h) [Reset = 00XXXXXXh]

SYSTEMCFG is shown in Figure 3-44 and described in Table 3-59.

Return to the Summary Table.

System configuration

Figure 3-44 SYSTEMCFG Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDFLASHECCRSTDISRESERVEDWWDTLP0RSTDIS
R/W-XXXXhR/W-1hR/W-XhR/W-0h
Table 3-59 SYSTEMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0
1Bh = Issue write
23-3RESERVEDR/WXXXXh
2FLASHECCRSTDISR/W1hFLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI.
0h = Flash ECC DED will trigger a SYSRST
1h = Flash ECC DED will trigger a NMI
1RESERVEDR/WXh
0WWDTLP0RSTDISR/W0hWWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI.
0h = WWDTLP0 Error Event will trigger a BOOTRST
1h = WWDTLP0 Error Event will trigger an NMI

3.6.2.35 SRAMCFG Register (Offset = 1184h) [Reset = 00X0XXX0h]

SRAMCFG is shown in Figure 3-45 and described in Table 3-60.

Return to the Summary Table.

System SRAM configuration

Figure 3-45 SRAMCFG Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVEDBANKINITDIS3BANKINITDIS2BANKINITDIS1BANKINITDIS0
R/W-XhR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R/W-XXXh
76543210
RESERVED
R/W-XXXh
Table 3-60 SRAMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of B5h (181) must be written to KEY together with contents to be updated. Reads as 0
B5h = Issue write
23-20RESERVEDR/WXh
19BANKINITDIS3R/W0hSRAM BANK3 Initialization
0h = SRAM BANK3 will Initialize when transitioning from OFF to ON
1h = SRAM BANK3 will NOT Initialize when transitioning from OFF to ON
18BANKINITDIS2R/W0hSRAM BANK2 Initialization
0h = SRAM BANK2 will Initialize when transitioning from OFF to ON
1h = SRAM BANK2 will NOT Initialize when transitioning from OFF to ON
17BANKINITDIS1R/W0hSRAM BANK1 Initialization
0h = SRAM BANK1 will Initialize when transitioning from OFF to ON
1h = SRAM BANK1 will NOT Initialize when transitioning from OFF to ON
16BANKINITDIS0R/W0hSRAM BANK0 Initialization
0h = SRAM BANK0 will Initialize when transitioning from OFF to ON
1h = SRAM BANK0 will NOT Initialize when transitioning from OFF to ON
15-4RESERVEDR/WXXXh

3.6.2.36 WRITELOCK Register (Offset = 1200h) [Reset = 00000000h]

WRITELOCK is shown in Figure 3-46 and described in Table 3-61.

Return to the Summary Table.

SYSCTL register write lockout

Figure 3-46 WRITELOCK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDACTIVE
R/W-0hR/W-0h
Table 3-61 WRITELOCK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0ACTIVER/W0hACTIVE controls whether critical SYSCTL registers are write protected or not.
0h = Allow writes to lockable registers
1h = Disallow writes to lockable registers

3.6.2.37 CLKSTATUS Register (Offset = 1204h) [Reset = XXXXXXXXh]

CLKSTATUS is shown in Figure 3-47 and described in Table 3-62.

Return to the Summary Table.

Clock module (CKM) status

Figure 3-47 CLKSTATUS Register
3130292827262524
RESERVEDSYSPLLBLKUPDHFCLKBLKUPDRESERVEDFCCDONEFCLMODE
R-XhR-0hR-0hR-XhR-0hR-0h
2322212019181716
RESERVEDHSCLKGOODHSCLKDEADRESERVEDCURHSCLKSEL
R-XhR-0hR-0hR-XhR-0h
15141312111098
RESERVEDSYSPLLOFFHFCLKOFFHSCLKSOFFLFOSCGOODRESERVEDSYSPLLGOODHFCLKGOOD
R-XhR-1hR-1hR-1hR-0hR-XhR-0hR-0h
76543210
RESERVEDHSCLKMUXRESERVEDSYSOSCFREQ
R-XhR-0hR-XhR-0h
Table 3-62 CLKSTATUS Register Field Descriptions
BitFieldTypeResetDescription
30RESERVEDRXh
29SYSPLLBLKUPDR0hSYSPLLBLKUPD indicates when writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are blocked.
0h = writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are allowed
1h = writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are blocked
28HFCLKBLKUPDR0hHFCLKBLKUPD indicates when writes to the HFCLKCLKCFG register are blocked.
0h = Writes to HFCLKCLKCFG are allowed
1h = Writes to HFCLKCLKCFG are blocked
27-26RESERVEDRXh
25FCCDONER0hFCCDONE indicates when a frequency clock counter capture is complete.
0h = FCC capture is not done
1h = FCC capture is done
24FCLMODER0hFCLMODE indicates if the SYSOSC frequency correction loop (FCL) is enabled.
0h = SYSOSC FCL is disabled
1h = SYSOSC FCL is enabled
23-22RESERVEDRXh
21HSCLKGOODR0hHSCLKGOOD is set by hardware if the selected clock source for HSCLK started successfully.
0h = The HSCLK source did not start correctly
1h = The HSCLK source started correctly
20HSCLKDEADR0hHSCLKDEAD is set by hardware if the selected source for HSCLK was started but did not start successfully.
0h = The HSCLK source was not started or started correctly
1h = The HSCLK source did not start correctly
19-18RESERVEDRXh
16CURHSCLKSELR0hCURHSCLKSEL indicates the current clock source for HSCLK.
0h = HSCLK is currently sourced from the SYSPLL
1h = HSCLK is currently sourced from the HFCLK
15RESERVEDRXh
14SYSPLLOFFR1hSYSPLLOFF indicates if the SYSPLL is disabled or was dead at startup. When the SYSPLL is started, SYSPLLOFF is cleared by hardware. Following startup of the SYSPLL, if the SYSPLL startup monitor determines that the SYSPLL was not started correctly, SYSPLLOFF is set.
0h = SYSPLL started correctly and is enabled
1h = SYSPLL is disabled or was dead startup
13HFCLKOFFR1hHFCLKOFF indicates if the HFCLK is disabled or was dead at startup. When the HFCLK is started, HFCLKOFF is cleared by hardware. Following startup of the HFCLK, if the HFCLK startup monitor determines that the HFCLK was not started correctly, HFCLKOFF is set.
0h = HFCLK started correctly and is enabled
1h = HFCLK is disabled or was dead at startup
12HSCLKSOFFR1hHSCLKSOFF is set when the high speed clock sources (SYSPLL, HFCLK) are disabled or dead. It is the logical AND of HFCLKOFF and SYSPLLOFF.
0h = SYSPLL, HFCLK, or both were started correctly and remain enabled
1h = SYSPLL and HFCLK are both either off or dead
11LFOSCGOODR0hLFOSCGOOD indicates when the LFOSC startup has completed and the LFOSC is ready for use.
0h = LFOSC is not ready
1h = LFOSC is ready
10RESERVEDRXh
9SYSPLLGOODR0hSYSPLLGOOD indicates if the SYSPLL started correctly. When the SYSPLL is started, SYSPLLGOOD is cleared by hardware. After the startup settling time has expired, the SYSPLL status is tested. If the SYSPLL started successfully the SYSPLLGOOD bit is set, else it is left cleared.
0h = SYSPLL did not start correctly
1h = SYSPLL started correctly
8HFCLKGOODR0hHFCLKGOOD indicates that the HFCLK started correctly. When the XTAL is started or HFCLK_IN is selected as the HFCLK source, this bit will be set by hardware if a valid HFCLK is detected, and cleared if HFCLK is not operating within the expected range.
0h = HFCLK did not start correctly
1h = HFCLK started correctly
5RESERVEDRXh
4HSCLKMUXR0hHSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK).
0h = MCLK is not sourced from HSCLK
1h = MCLK is sourced from HSCLK
3-2RESERVEDRXh
1-0SYSOSCFREQR0hSYSOSCFREQ indicates the current SYSOSC operating frequency.
0h = SYSOSC is at base frequency (32MHz)
1h = SYSOSC is at low frequency (4MHz)

3.6.2.38 SYSSTATUS Register (Offset = 1208h) [Reset = XXX00XX0h]

SYSSTATUS is shown in Figure 3-48 and described in Table 3-63.

Return to the Summary Table.

System status information

Figure 3-48 SYSSTATUS Register
3130292827262524
REBOOTATTEMPTSRESERVED
R-0hR-XXh
2322212019181716
RESERVEDSRAMBANK3READYSRAMBANK2READYSRAMBANK1READYSRAMBANK0READY
R-XXhR-0hR-0hR-0hR-0h
15141312111098
SHDNIOLOCKSWDJCFGDISEXTRSTPINDISRESERVEDMCAN0READY
R-0hR-0hR-0hR-XhR-0h
76543210
RESERVEDPMUIREFGOODFLASHSECFLASHDED
R-XhR-0hR-0hR-0h
Table 3-63 SYSSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-30REBOOTATTEMPTSR0hREBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts.
29-20RESERVEDRXXh
19SRAMBANK3READYR0hSRAM BANK3 READY STATE
0h = SRAM BANK3 is NOT READY for access
1h = SRAM BANK3 is READY for access
18SRAMBANK2READYR0hSRAM BANK2 READY STATE
0h = SRAM BANK2 is NOT READY for access
1h = SRAM BANK2 is READY for access
17SRAMBANK1READYR0hSRAM BANK1 READY STATE
0h = SRAM BANK1 is NOT READY for access
1h = SRAM BANK1 is READY for access
16SRAMBANK0READYR0hSRAM BANK0 READY STATE
0h = SRAM BANK0 is NOT READY for access
1h = SRAM BANK0 is READY for access
14SHDNIOLOCKR0hSHDNIOLOCK indicates when IO is locked due to SHUTDOWN
0h = IO IS NOT Locked due to SHUTDOWN
1h = IO IS Locked due to SHUTDOWN
13SWDJCFGDISR0hSWDJCFGDIS indicates when user has disabled the use of SWD/JTAG Port
0h = SWD/JTAG Port Enabled
1h = SWD/JTAG Port Disabled
12EXTRSTPINDISR0hEXTRSTPINDIS indicates when user has disabled the use of external reset pin
0h = External Reset Pin Enabled
1h = External Reset Pin Disabled
11-9RESERVEDRXh
8MCAN0READYR0hMCAN0READY indicates when the MCAN0 peripheral is ready.
0h = MCAN0 is not ready
1h = MCAN0 is ready
7RESERVEDRXh
6PMUIREFGOODR0hPMUIREFGOOD is set by hardware when the PMU current reference is ready.
0h = IREF is not ready
1h = IREF is ready
1FLASHSECR0hFLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC).
0h = No flash ECC single bit error detected
1h = Flash ECC single bit error was detected and corrected
0FLASHDEDR0hFLASHDED indicates if a flash ECC double bit error was detected (DED).
0h = No flash ECC double bit error detected
1h = Flash ECC double bit error detected

3.6.2.39 RSTCAUSE Register (Offset = 1220h) [Reset = 00000000h]

RSTCAUSE is shown in Figure 3-49 and described in Table 3-64.

Return to the Summary Table.

Reset cause

Figure 3-49 RSTCAUSE Register
313029282726252423222120191817161514131211109876543210
RESERVEDID
R-0hRC-0h
Table 3-64 RSTCAUSE Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-0IDRC0hID is a read-to-clear field which indicates the lowest level reset cause since the last read.
0h = No reset since last read
1h = POR- violation, SHUTDNSTOREx or PMU trim parity fault
2h = NRST triggered POR (>1s hold)
3h = Software triggered POR
4h = BOR0- violation
5h = SHUTDOWN mode exit
8h = Non-PMU trim parity fault
9h = Fatal clock failure
Ch = NRST triggered BOOTRST (<1s hold)
Dh = Software triggered BOOTRST
Eh = WWDT0 violation
10h = BSL exit
11h = BSL entry
14h = Flash uncorrectable ECC error
15h = CPULOCK violation
1Ah = Debug triggered SYSRST
1Bh = Software triggered SYSRST
1Ch = Debug triggered CPURST
1Dh = Software triggered CPURST

3.6.2.40 RESETLEVEL Register (Offset = 1300h) [Reset = 00000000h]

RESETLEVEL is shown in Figure 3-50 and described in Table 3-65.

Return to the Summary Table.

Reset level for application-triggered reset command

Figure 3-50 RESETLEVEL Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDLEVEL
R/W-0hR/W-0h
Table 3-65 RESETLEVEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0LEVELR/W0hLEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset.
0h = Issue a SYSRST (CPU plus peripherals only)
1h = Issue a BOOTRST (CPU, peripherals, and boot configuration routine)
2h = Issue a SYSRST and enter the boot strap loader (BSL)
3h = Issue a power-on reset (POR)
4h = Issue a SYSRST and exit the boot strap loader (BSL)

3.6.2.41 RESETCMD Register (Offset = 1304h) [Reset = 00XXXXXXh]

RESETCMD is shown in Figure 3-51 and described in Table 3-66.

Return to the Summary Table.

Execute an application-triggered reset command

Figure 3-51 RESETCMD Register
31302928272625242322212019181716
KEYRESERVED
W-0hW-XXXXh
1514131211109876543210
RESERVEDGO
W-XXXXhW-0h
Table 3-66 RESETCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of E4h (228) must be written to KEY together with GO to trigger the reset.
E4h = Issue reset
23-1RESERVEDWXXXXh
0GOW0hExecute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY.
1h = Issue reset

3.6.2.42 SYSOSCFCLCTL Register (Offset = 1310h) [Reset = 00XXXXXXh]

SYSOSCFCLCTL is shown in Figure 3-52 and described in Table 3-67.

Return to the Summary Table.

SYSOSC frequency correction loop (FCL) ROSC enable

Figure 3-52 SYSOSCFCLCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDSETUSEFCL
W-XXXXhW-0h
Table 3-67 SYSOSCFCLCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL.
2Ah = Issue Command
23-2RESERVEDWXXXXh
0SETUSEFCLW0hSet SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST.
1h = Enable the SYSOSC FCL

3.6.2.43 SHDNIOREL Register (Offset = 131Ch) [Reset = 00XXXXXXh]

SHDNIOREL is shown in Figure 3-53 and described in Table 3-68.

Return to the Summary Table.

SHUTDOWN IO release control

Figure 3-53 SHDNIOREL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRELEASE
W-XXXXhW-0h
Table 3-68 SHDNIOREL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 91h must be written to KEY together with RELEASE to set RELEASE.
91h = Issue command
23-1RESERVEDWXXXXh
0RELEASEW0hSet RELEASE to release the IO after a SHUTDOWN mode exit.
1h = Release IO

3.6.2.44 EXRSTPIN Register (Offset = 1320h) [Reset = 00XXXXXXh]

EXRSTPIN is shown in Figure 3-54 and described in Table 3-69.

Return to the Summary Table.

Disable the reset function of the NRST pin

Figure 3-54 EXRSTPIN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDDISABLE
W-XXXXhW-0h
Table 3-69 EXRSTPIN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 1Eh must be written together with DISABLE to disable the reset function.
1Eh = Issue command
23-1RESERVEDWXXXXh
0DISABLEW0hSet DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR.
0h = Reset function of NRST pin is enabled
1h = Reset function of NRST pin is disabled

3.6.2.45 SYSSTATUSCLR Register (Offset = 1324h) [Reset = 00XXXXXXh]

SYSSTATUSCLR is shown in Figure 3-55 and described in Table 3-70.

Return to the Summary Table.

Clear sticky bits of SYSSTATUS

Figure 3-55 SYSSTATUSCLR Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDALLECC
W-XXXXhW-0h
Table 3-70 SYSSTATUSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value CEh (206) must be written to KEY together with ALLECC to clear the ECC state.
CEh = Issue command
23-1RESERVEDWXXXXh
0ALLECCW0hSet ALLECC to clear all ECC related SYSSTATUS indicators.
1h = Clear ECC error state

3.6.2.46 SWDJCFG Register (Offset = 1328h) [Reset = 00XXXXXXh]

SWDJCFG is shown in Figure 3-56 and described in Table 3-71.

Return to the Summary Table.

Disable the SWD/JTAG function on the SWD/JTAG pins

Figure 3-56 SWDJCFG Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDDISABLE
W-XXXXhW-0h
Table 3-71 SWDJCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 62h (98) must be written to KEY together with DISBALE to disable the SWD/JTAG functions.
62h = Issue command
23-1RESERVEDWXXXXh
0DISABLEW0hSet DISABLE to disable the SWD/JTAG function on SWD/JTAG pins, allowing the SWD/JTAG pins to be used as GPIO.
1h = Disable SWD/JTAG function on SWD/JTAG pins

3.6.2.47 FCCCMD Register (Offset = 132Ch) [Reset = 00XXXXXXh]

FCCCMD is shown in Figure 3-57 and described in Table 3-72.

Return to the Summary Table.

Frequency clock counter start capture

Figure 3-57 FCCCMD Register
31302928272625242322212019181716
KEYRESERVED
W-0hW-XXXXh
1514131211109876543210
RESERVEDGO
W-XXXXhW-0h
Table 3-72 FCCCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 0Eh (14) must be written with GO to start a capture.
0Eh = Issue command
23-1RESERVEDWXXXXh
0GOW0hSet GO to start a capture with the frequency clock counter (FCC).
1h = 1

3.6.2.48 SHUTDNSTORE0 Register (Offset = 1400h) [Reset = 00000000h]

SHUTDNSTORE0 is shown in Figure 3-58 and described in Table 3-73.

Return to the Summary Table.

Shutdown storage memory (byte 0)

Figure 3-58 SHUTDNSTORE0 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0hR-0hR/W-0h
76543210
DATA
R/W-0h
Table 3-73 SHUTDNSTORE0 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9RESERVEDR0hReserved
8RESERVEDR/W0hReserved
7-0DATAR/W0hShutdown storage byte 0

3.6.2.49 SHUTDNSTORE1 Register (Offset = 1404h) [Reset = 00000000h]

SHUTDNSTORE1 is shown in Figure 3-59 and described in Table 3-74.

Return to the Summary Table.

Shutdown storage memory (byte 1)

Figure 3-59 SHUTDNSTORE1 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0hR-0hR/W-0h
76543210
DATA
R/W-0h
Table 3-74 SHUTDNSTORE1 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9RESERVEDR0hReserved
8RESERVEDR/W0hReserved
7-0DATAR/W0hShutdown storage byte 1

3.6.2.50 SHUTDNSTORE2 Register (Offset = 1408h) [Reset = 00000000h]

SHUTDNSTORE2 is shown in Figure 3-60 and described in Table 3-75.

Return to the Summary Table.

Shutdown storage memory (byte 2)

Figure 3-60 SHUTDNSTORE2 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0hR-0hR/W-0h
76543210
DATA
R/W-0h
Table 3-75 SHUTDNSTORE2 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9RESERVEDR0hReserved
8RESERVEDR/W0hReserved
7-0DATAR/W0hShutdown storage byte 2

3.6.2.51 SHUTDNSTORE3 Register (Offset = 140Ch) [Reset = 00000000h]

SHUTDNSTORE3 is shown in Figure 3-61 and described in Table 3-76.

Return to the Summary Table.

Shutdown storage memory (byte 3)

Figure 3-61 SHUTDNSTORE3 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0hR-0hR/W-0h
76543210
DATA
R/W-0h
Table 3-76 SHUTDNSTORE3 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9RESERVEDR0hReserved
8RESERVEDR/W0hReserved
7-0DATAR/W0hShutdown storage byte 3

3.6.2.52 ADCSEQFRCGB Register (Offset = 1410h) [Reset = 00000000h]

ADCSEQFRCGB is shown in Figure 3-62 and described in Table 3-77.

Return to the Summary Table.

ADC Global Sequence Force

Figure 3-62 ADCSEQFRCGB Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSEQ3SEQ2SEQ1SEQ0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-77 ADCSEQFRCGB Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3SEQ3R/W0hGenerate synchronous SW trigger for SEQ3
2SEQ2R/W0hGenerate synchronous SW trigger for SEQ2
1SEQ1R/W0hGenerate synchronous SW trigger for SEQ1
0SEQ0R/W0hGenerate synchronous SW trigger for SEQ0

3.6.2.53 ADCSEQFRCGBSEL Register (Offset = 1414h) [Reset = 00000000h]

ADCSEQFRCGBSEL is shown in Figure 3-63 and described in Table 3-78.

Return to the Summary Table.

ADC Global Sequence Force Select

Figure 3-63 ADCSEQFRCGBSEL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDADCCADCBADCA
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-78 ADCSEQFRCGBSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2ADCCR/W0hGenerate synchronous SW trigger for ADCC
1ADCBR/W0hGenerate synchronous SW trigger for ADCB
0ADCAR/W0hGenerate synchronous SW trigger for ADCA

3.6.2.54 M33SPARESOCLOCK1 Register (Offset = 1418h) [Reset = 00000000h]

M33SPARESOCLOCK1 is shown in Figure 3-64 and described in Table 3-79.

Return to the Summary Table.

M33C1 Spare SOC LOCK Reg 1

Figure 3-64 M33SPARESOCLOCK1 Register
313029282726252423222120191817161514131211109876543210
SPARE
R/W-0h
Table 3-79 M33SPARESOCLOCK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPARER/W0hSpare SOC LOCK Register 1

3.6.2.55 M33SPARESOCLOCK2 Register (Offset = 141Ch) [Reset = 00000000h]

M33SPARESOCLOCK2 is shown in Figure 3-65 and described in Table 3-80.

Return to the Summary Table.

M33C1 Spare SOC LOCK Reg 2

Figure 3-65 M33SPARESOCLOCK2 Register
313029282726252423222120191817161514131211109876543210
SPARE
R/W-0h
Table 3-80 M33SPARESOCLOCK2 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPARER/W0hSpare SOC LOCK Register 2

3.6.2.56 SYSCTL_READ_REG Register (Offset = 1420h) [Reset = 00000000h]

SYSCTL_READ_REG is shown in Figure 3-66 and described in Table 3-81.

Return to the Summary Table.

Sysctl read only Reg

Figure 3-66 SYSCTL_READ_REG Register
313029282726252423222120191817161514131211109876543210
ecoreg
R/W-0h
Table 3-81 SYSCTL_READ_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0ecoregR/W0hRead only register

3.6.2.57 PWREN_MCPERIPH Register (Offset = 1424h) [Reset = 00XXX000h]

PWREN_MCPERIPH is shown in Figure 3-67 and described in Table 3-82.

Return to the Summary Table.

Register to control the power state

Figure 3-67 PWREN_MCPERIPH Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXh
15141312111098
RESERVEDxbarcmpss3cmpss2cmpss1cmpss0pwm4pwm3
R/W-XXhR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
pwm2pwm1pwm0ecap1ecap0eqep2eqep1eqep0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-82 PWREN_MCPERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-15RESERVEDR/WXXh
14xbarR/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
13cmpss3R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
12cmpss2R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
11cmpss1R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
10cmpss0R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
9pwm4R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
8pwm3R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
7pwm2R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
6pwm1R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
5pwm0R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
4ecap1R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
3ecap0R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
2eqep2R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
1eqep1R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
0eqep0R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power

3.6.2.58 RSTCTL_ASSERT_MCPERIPH Register (Offset = 1428h) [Reset = 00XXX000h]

RSTCTL_ASSERT_MCPERIPH is shown in Figure 3-68 and described in Table 3-83.

Return to the Summary Table.

rstctl assert register to control reset assertion - Write Only Register, Always Read as 0

Figure 3-68 RSTCTL_ASSERT_MCPERIPH Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXh
15141312111098
RESERVEDRESETASSERT_xbarRESETASSERT_cmpss3RESETASSERT_cmpss2RESETASSERT_cmpss1RESETASSERT_cmpss0RESETASSERT_pwm4RESETASSERT_pwm3
W-XXhW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESETASSERT_pwm2RESETASSERT_pwm1RESETASSERT_pwm0RESETASSERT_ecap1RESETASSERT_ecap0RESETASSERT_eqep2RESETASSERT_eqep1RESETASSERT_eqep0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 3-83 RSTCTL_ASSERT_MCPERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0xb1
B1h = 0xb1
23-15RESERVEDWXXh
14RESETASSERT_xbarW0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
13RESETASSERT_cmpss3W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
12RESETASSERT_cmpss2W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
11RESETASSERT_cmpss1W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
10RESETASSERT_cmpss0W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
9RESETASSERT_pwm4W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
8RESETASSERT_pwm3W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
7RESETASSERT_pwm2W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
6RESETASSERT_pwm1W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
5RESETASSERT_pwm0W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
4RESETASSERT_ecap1W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
3RESETASSERT_ecap0W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
2RESETASSERT_eqep2W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
1RESETASSERT_eqep1W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
0RESETASSERT_eqep0W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset

3.6.2.59 RSTCTL_CLEAR_MCPERIPH Register (Offset = 142Ch) [Reset = 00XXX000h]

RSTCTL_CLEAR_MCPERIPH is shown in Figure 3-69 and described in Table 3-84.

Return to the Summary Table.

rstctl clear register to control reset de-assertion - Write Only Register, Always Read as 0

Figure 3-69 RSTCTL_CLEAR_MCPERIPH Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXh
15141312111098
RESERVEDRESETSTKYCLR_xbarRESETSTKYCLR_cmpss3RESETSTKYCLR_cmpss2RESETSTKYCLR_cmpss1RESETSTKYCLR_cmpss0RESETSTKYCLR_pwm4RESETSTKYCLR_pwm3
W-XXhW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESETSTKYCLR_pwm2RESETSTKYCLR_pwm1RESETSTKYCLR_pwm0RESETSTKYCLR_ecap1RESETSTKYCLR_ecap0RESETSTKYCLR_eqep2RESETSTKYCLR_eqep1RESETSTKYCLR_eqep0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 3-84 RSTCTL_CLEAR_MCPERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0xb1
B1h = 0xb1
23-15RESERVEDWXXh
14RESETSTKYCLR_xbarW0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
13RESETSTKYCLR_cmpss3W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
12RESETSTKYCLR_cmpss2W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
11RESETSTKYCLR_cmpss1W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
10RESETSTKYCLR_cmpss0W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
9RESETSTKYCLR_pwm4W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
8RESETSTKYCLR_pwm3W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
7RESETSTKYCLR_pwm2W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
6RESETSTKYCLR_pwm1W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
5RESETSTKYCLR_pwm0W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
4RESETSTKYCLR_ecap1W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
3RESETSTKYCLR_ecap0W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
2RESETSTKYCLR_eqep2W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
1RESETSTKYCLR_eqep1W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
0RESETSTKYCLR_eqep0W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect

3.6.2.60 STAT_MCPERIPH Register (Offset = 1430h) [Reset = 00000000h]

STAT_MCPERIPH is shown in Figure 3-70 and described in Table 3-85.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-70 STAT_MCPERIPH Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDxbarcmpss3cmpss2cmpss1cmpss0pwm4pwm3
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
pwm2pwm1pwm0ecap1ecap0eqep2eqep1eqep0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-85 STAT_MCPERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14xbarR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
13cmpss3R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
12cmpss2R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
11cmpss1R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
10cmpss0R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
9pwm4R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
8pwm3R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
7pwm2R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
6pwm1R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
5pwm0R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
4ecap1R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
3ecap0R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
2eqep2R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
1eqep1R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
0eqep0R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear

3.6.2.61 PWREN_SYSPERIPH Register (Offset = 1434h) [Reset = 00XXXXX0h]

PWREN_SYSPERIPH is shown in Figure 3-71 and described in Table 3-86.

Return to the Summary Table.

Register to control the power state

Figure 3-71 PWREN_SYSPERIPH Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDepipga2pga1pga0tinie
R/W-XXXXhR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-86 PWREN_SYSPERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-5RESERVEDR/WXXXXh
4epiR/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
3pga2R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
2pga1R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
1pga0R/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power
0tinieR/W0hEnable the power to IP, KEY must be set to 26h to write to this bit
0h = Disable Power
1h = Enable Power

3.6.2.62 RSTCTL_ASSERT_SYSPERIPH Register (Offset = 1438h) [Reset = 00XXXXX0h]

RSTCTL_ASSERT_SYSPERIPH is shown in Figure 3-72 and described in Table 3-87.

Return to the Summary Table.

rstcl assert Register - Write Only Register, Always Read as 0

Figure 3-72 RSTCTL_ASSERT_SYSPERIPH Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETASSERT_epiRESETASSERT_pga2RESETASSERT_pga1RESETASSERT_pga0RESETASSERT_tinie
W-XXXXhW-0hW-0hW-0hW-0hW-0h
Table 3-87 RSTCTL_ASSERT_SYSPERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0xb1
B1h = 0xb1
23-5RESERVEDWXXXXh
4RESETASSERT_epiW0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
3RESETASSERT_pga2W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
2RESETASSERT_pga1W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
1RESETASSERT_pga0W0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset
0RESETASSERT_tinieW0hassert reset to the peripheral, KEY must be set to B1h to write to this bit
0h = Writing 0 has no effect
1h = Assert reset

3.6.2.63 RSTCTL_CLEAR_SYSPERIPH Register (Offset = 143Ch) [Reset = 00XXXXX0h]

RSTCTL_CLEAR_SYSPERIPH is shown in Figure 3-73 and described in Table 3-88.

Return to the Summary Table.

rstctl clear register to control reset de-assertion - Write Only Register, Always Read as 0

Figure 3-73 RSTCTL_CLEAR_SYSPERIPH Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLR_epiRESETSTKYCLR_pga2RESETSTKYCLR_pga1RESETSTKYCLR_pga0RESETSTKYCLR_tinie
W-XXXXhW-0hW-0hW-0hW-0hW-0h
Table 3-88 RSTCTL_CLEAR_SYSPERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0xb1
B1h = 0xb1
23-5RESERVEDWXXXXh
4RESETSTKYCLR_epiW0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
3RESETSTKYCLR_pga2W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
2RESETSTKYCLR_pga1W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
1RESETSTKYCLR_pga0W0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect
0RESETSTKYCLR_tinieW0hClear the RESETSTKY bit in the STAT register, KEY must be set to B1h to write to this bit
1h = Writing 0 has no effect

3.6.2.64 STAT_SYSPERIPH Register (Offset = 1440h) [Reset = 00000000h]

STAT_SYSPERIPH is shown in Figure 3-74 and described in Table 3-89.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-74 STAT_SYSPERIPH Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDepipga2pga1pga0tinie
R-0hR-0hR-0hR-0hR-0hR-0h
Table 3-89 STAT_SYSPERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4epiR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
3pga2R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
2pga1R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
1pga0R0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
0tinieR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear

3.6.2.65 CMPHPMXSEL Register (Offset = 1444h) [Reset = 00000000h]

CMPHPMXSEL is shown in Figure 3-75 and described in Table 3-90.

Return to the Summary Table.

Bits to select one of the many sources on CompHP inputs. Refer to Pinmux diagram for details.

Figure 3-75 CMPHPMXSEL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDCMP3HPMXSELCMP2HPMXSEL
R/W-0hR/W-0hR/W-0h
76543210
CMP2HPMXSELCMP1HPMXSELCMP0HPMXSEL
R/W-0hR/W-0hR/W-0h
Table 3-90 CMPHPMXSEL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR/W0h
11-9CMP3HPMXSELR/W0hCMP3HPMXSEL bits
8-6CMP2HPMXSELR/W0hCMP2HPMXSEL bits
5-3CMP1HPMXSELR/W0hCMP1HPMXSEL bits
2-0CMP0HPMXSELR/W0hCMP0HPMXSEL bits

3.6.2.66 CMPLPMXSEL Register (Offset = 144Ch) [Reset = 00000000h]

CMPLPMXSEL is shown in Figure 3-76 and described in Table 3-91.

Return to the Summary Table.

Bits to select one of the many sources on CompLP inputs. Refer to Pinmux diagram for details.

Figure 3-76 CMPLPMXSEL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDCMP3LPMXSELCMP2LPMXSEL
R/W-0hR/W-0hR/W-0h
76543210
CMP2LPMXSELCMP1LPMXSELCMP0LPMXSEL
R/W-0hR/W-0hR/W-0h
Table 3-91 CMPLPMXSEL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR/W0h
11-9CMP3LPMXSELR/W0hCMP3LPMXSEL bits
8-6CMP2LPMXSELR/W0hCMP2LPMXSEL bits
5-3CMP1LPMXSELR/W0hCMP1LPMXSEL bits
2-0CMP0LPMXSELR/W0hCMP0LPMXSEL bits

3.6.2.67 CMPHNMXSEL Register (Offset = 1450h) [Reset = 00000000h]

CMPHNMXSEL is shown in Figure 3-77 and described in Table 3-92.

Return to the Summary Table.

Bits to select one of the many sources on CompHN inputs. Refer to Pinmux diagram for details.

Figure 3-77 CMPHNMXSEL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCMP3HNMXSELCMP2HNMXSELCMP1HNMXSELCMP0HNMXSEL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-92 CMPHNMXSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3CMP3HNMXSELR/W0hCMP3HNMXSEL bits
2CMP2HNMXSELR/W0hCMP2HNMXSEL bits
1CMP1HNMXSELR/W0hCMP1HNMXSEL bits
0CMP0HNMXSELR/W0hCMP0HNMXSEL bits

3.6.2.68 CMPLNMXSEL Register (Offset = 1454h) [Reset = 00000000h]

CMPLNMXSEL is shown in Figure 3-78 and described in Table 3-93.

Return to the Summary Table.

Bits to select one of the many sources on CompLN inputs. Refer to Pinmux diagram for details.

Figure 3-78 CMPLNMXSEL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCMP3LNMXSELCMP2LNMXSELCMP1LNMXSELCMP0LNMXSEL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-93 CMPLNMXSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3CMP3LNMXSELR/W0hCMP3LNMXSEL bits
2CMP2LNMXSELR/W0hCMP2LNMXSEL bits
1CMP1LNMXSELR/W0hCMP1LNMXSEL bits
0CMP0LNMXSELR/W0hCMP0LNMXSEL bits

3.6.2.69 TSNSCFG Register (Offset = 1458h) [Reset = 00000000h]

TSNSCFG is shown in Figure 3-79 and described in Table 3-94.

Return to the Summary Table.

Temperature Sensor Config Register

Figure 3-79 TSNSCFG Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-94 TSNSCFG Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR/W0h
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.6.2.70 TSNSSCTL Register (Offset = 145Ch) [Reset = 00000000h]

TSNSSCTL is shown in Figure 3-80 and described in Table 3-95.

Return to the Summary Table.

Temperature Sensor Control Register

Figure 3-80 TSNSSCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE
R/W-0hR/W-0h
Table 3-95 TSNSSCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0ENABLER/W0hTemperature Sensor Enable

3.6.2.71 PGACONFIG Register (Offset = 1460h) [Reset = 00000000h]

PGACONFIG is shown in Figure 3-81 and described in Table 3-96.

Return to the Summary Table.

PGA Configuration Register

Figure 3-81 PGACONFIG Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-96 PGACONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
19-18RESERVEDR/W0hReserved
17-14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12-7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.6.2.72 REFCONFIGA Register (Offset = 1464h) [Reset = 00000000h]

REFCONFIGA is shown in Figure 3-82 and described in Table 3-97.

Return to the Summary Table.

Reference Configuration Regsiter

Figure 3-82 REFCONFIGA Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-97 REFCONFIGA Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26-21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18-15RESERVEDR/W0hReserved
14-12RESERVEDR/W0hReserved
11-5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.6.2.73 INTERNALTESTCTL Register (Offset = 1468h) [Reset = 00000000h]

INTERNALTESTCTL is shown in Figure 3-83 and described in Table 3-98.

Return to the Summary Table.

Internal Test Node Control Register

Figure 3-83 INTERNALTESTCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVED
R/W-0hR/W-0h
76543210
RESERVEDTESTSEL
R/W-0hR/W-0h
Table 3-98 INTERNALTESTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8-6RESERVEDR/W0hReserved
5-0TESTSELR/W0hTest Select
1h = VDDCORE
2h = VDDA
3h = VSSA
4h = VREFLOAC
5h = CDAC1H
6h = CDAC1L
7h = CDAC2H
8h = CDAC2H
9h = CDAC2H
Ah = CDAC2H
Bh = CDAC2H
Ch = CDAC2H
1Dh = ENZ_CALIB_GAIN_3P3V will be made low. ADCA and ADCC will be in gain calibration mode, and 0.9xVREFHIAB pin voltage will be sampled by both ADCs through internal test-mux output
1Eh = CMPSS1 VDDA sense on TESTANA0,VSSA sense on TESTANA1
1Fh = ADCA VDDA sense on TESTANA0,VSSA sense on TESTANA1
20h = COMP DAC BUFFER VDDA sense on TESTANA0,VSSA sense on TESTANA1
21h = PGA1 VDDA sense on TESTANA0,VSSA sense on TESTANA1
22h = ADCCIO_TESTANA0_INT
23h = PMM/HPLL/INTOSC TESTANA0_INT
24h = ADCCIO_TESTANA1_INT
25h = PMM/HPLL/INTOSC TESTANA1_INT
26h = Enable resistor for I2V conversion. The same control enables the sampling of voltage across a resistor by ADC. R=2.5k, 38: R=10k, 39: R=35k
29h = USB_TESTANA0_INT
2Ah = USB_TESTANA1_INT
2Bh = USB_TESTANA0_INT & USB_TESTANA1_INT
2Ch = VSS
2Dh = Bring FLT3 & TESTPAD3 of flash on TESTANA1
2Eh = Enable resistor for I2V conversion. The same control enables the sampling of voltage across a resistor by ADC. R=2.5k, 47: R=10k, 48: R=35k
31h = VREFLOAC

3.6.2.74 I2VCTL Register (Offset = 146Ch) [Reset = 00000000h]

I2VCTL is shown in Figure 3-84 and described in Table 3-99.

Return to the Summary Table.

I2V Logic Control

Figure 3-84 I2VCTL Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDRESERVED
R/W-0hR/W-0h
Table 3-99 I2VCTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0RESERVEDR/W0hReserved

3.6.2.75 ADCDACLOOPBACK Register (Offset = 1470h) [Reset = 00000000h]

ADCDACLOOPBACK is shown in Figure 3-85 and described in Table 3-100.

Return to the Summary Table.

Not used in AM13

Figure 3-85 ADCDACLOOPBACK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-100 ADCDACLOOPBACK Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.6.2.76 XTALCR Register (Offset = 1474h) [Reset = 00000001h]

XTALCR is shown in Figure 3-86 and described in Table 3-101.

Return to the Summary Table.

XTAL Control Register

Figure 3-86 XTALCR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSEOSCOFF
R/W-0hR/W-0hR/W-1h
Table 3-101 XTALCR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1SER/W0hXTAL Oscilator in Single-Ended
0h = XTAL oscillator in Crystal mode
1h = XTAL oscilator in single-ended mode (through X1)
0OSCOFFR/W1hThis bit if 1, powers-down the XTAL oscillator macro and hence doesnt let X2 to be driven by the XTAL oscillator. If a crystal is connected to X1/X2, user needs to first clear this bit, wait for the oscillator to power up (using X1CNT) and then only switch the clock source to X1/X2
0h = XTAL Oscillator powered-up using X1/X2
1h = XTAL Oscillator powered-down

3.6.2.77 XTALCR2 Register (Offset = 1478h) [Reset = 0000XXXXh]

XTALCR2 is shown in Figure 3-87 and described in Table 3-102.

Return to the Summary Table.

XTAL Control Register for pad init

Figure 3-87 XTALCR2 Register
31302928272625242322212019181716
FKEEPXI
R/W-0h
1514131211109876543210
RESERVEDFENXOFXIF
R/W-XXXhR/W-0hR/W-1hR/W-1h
Table 3-102 XTALCR2 Register Field Descriptions
BitFieldTypeResetDescription
31-16FKEEPXIR/W0hThis field when written 0xface allows to hold the force value on XI as programmed on XIF. 0xface: Force on XI is continued as per XIF value regardless of XOSC ON/OFF state only in XTAL mode. In Single ended mode this field has no impact. Any other value: Force on XI is removed with enabling of XOSC as per FEN function.
15-3RESERVEDR/WXXXh
2FENR/W0hXOSC pads initialisation enable. Configures XTAL oscillator pad initilisation. This register has effect only when XOSC is OFF (no SE , no XTAL mode). If this register is set during XOSC off state (XOSCOFF=1 & SE=0)
then upon change of these controls this bit gets reset and rearmed
0h = XOSC pads are not driven through GPIO connection.
1h = XOSC pads are driven through connected GPIO as per XIF & XOF values.
1XOFR/W1hXO Initial value deposited before XOSC start. Polarity selection to initialise XO/X2 pad of the XOSC before start-up. This value shall be deposited on the pad before XOSC started (XOSCOFF=1). If FEN=0 or XOSC is in XTAL or SE mode
then this value will not be applied to the pad.
0XIFR/W1hXI Initial value deposited before XOSC start. Polarity selection to initialise XI/X1 pad of the XOSC before start-up. This value shall be deposited on the pad before XOSC started (XOSCOFF=1). If FEN=0 or XOSC is in XTAL or SE mode
then this value will not be applied to the pad.

3.6.2.78 X1CNT Register (Offset = 147Ch) [Reset = 0000XX00h]

X1CNT is shown in Figure 3-88 and described in Table 3-103.

Return to the Summary Table.

x1cnt status register

Figure 3-88 X1CNT Register
31302928272625242322212019181716
RESERVEDCLR
R/W-0hW-0h
1514131211109876543210
RESERVEDX1CNT
R/W-XhR-0h
Table 3-103 X1CNT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/W0h
16CLRW0hX1 Counter clear: A write of 1 to this bit field clears the X1CNT and makes it count from 0x0 again (provided X1 clock is ticking). Writes of 0 are ignore to this bit field
15-11RESERVEDR/WXh
10-0X1CNTR0hThis counter increments on every X1 CLOCKs positive-edge. Once it reaches the values of 0x7ff, it freezes. Before switching from SYSOSC/PLL clock to X1, application must check this counter and make sure that it has saturated. This will ensure that the Crystal connected to X1/X2 is oscillating

3.6.2.79 CMPSSCTL Register (Offset = 1480h) [Reset = XXXXXXXXh]

CMPSSCTL is shown in Figure 3-89 and described in Table 3-104.

Return to the Summary Table.

CMPSS control register

Figure 3-89 CMPSSCTL Register
3130292827262524
CMPSSCTLENRESERVED
R/W-0hR/W-000XXXXXh
2322212019181716
RESERVED
R/W-000XXXXXh
15141312111098
RESERVED
R/W-000XXXXXh
76543210
RESERVEDCMP3LDACOUTENCMP2LDACOUTEN
R/W-000XXXXXhR/W-0hR/W-0h
Table 3-104 CMPSSCTL Register Field Descriptions
BitFieldTypeResetDescription
31CMPSSCTLENR/W0hEnable the CMPSSCTL Register
30-2RESERVEDR/WXXXXh
1CMP3LDACOUTENR/W0hEnable general purpose DAC functionality for CMPSS3 COMPDACL
0CMP2LDACOUTENR/W0hEnable general purpose DAC functionality for CMPSS2 COMPDACL

3.6.2.80 CMPSSDACBUFCONFIG Register (Offset = 1484h) [Reset = 00000000h]

CMPSSDACBUFCONFIG is shown in Figure 3-90 and described in Table 3-105.

Return to the Summary Table.

Config bits for CMPSS DAC buffer

Figure 3-90 CMPSSDACBUFCONFIG Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDRESERVED
R/W-0hR/W-0h
Table 3-105 CMPSSDACBUFCONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-8RESERVEDR/W0hReserved
7-0RESERVEDR/W0hReserved

3.6.2.81 ANAREFCTL Register (Offset = 1488h) [Reset = 000000XXh]

ANAREFCTL is shown in Figure 3-91 and described in Table 3-106.

Return to the Summary Table.

Analog Reference Select

Figure 3-91 ANAREFCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDANAREF2P5SEL
R/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDANAREFSEL
R/W-XhR/W-0hR/W-0hR/W-1h
Table 3-106 ANAREFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8ANAREF2P5SELR/W0hAnalog reference 2.5V source select. In internal reference mode, this bit selects which voltage the internal reference buffer drives onto the VREFHI pin. The buffer can drive either 1.65V onto the pin, resulting in a reference range of 0 to 3.3V, or the buffer can drive 2.5V onto the pin, resulting in a reference range of 0 to 2.5V. If switching between these two modes, the user must allow adequate time for the external capacitor to charge to the new voltage before using the ADC or buffered DAC. 0 - Internal 1.65V reference mode (3.3V reference range) 1 - Internal 2.5V reference mode (2.5V reference range)
7-3RESERVEDR/WXh
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0ANAREFSELR/W1hAnalog reference mode select. This bit selects whether the VREFHI pin uses internal reference mode (the device drives a voltage onto the VREFHI pin) or external reference mode (the system is expected to drive a voltage into the VREFHI pin). 0 - Internal reference mode 1 - External reference mode

3.6.2.82 PERCLKCR Register (Offset = 148Ch) [Reset = 00000000h]

PERCLKCR is shown in Figure 3-92 and described in Table 3-107.

Return to the Summary Table.

PWM Time Base Clock sync

Figure 3-92 PERCLKCR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDTBCLKSYNC
R/W-0hR/W-0h
Table 3-107 PERCLKCR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0TBCLKSYNCR/W0hPWM Time Base Clock sync: When set PWM time bases of all the PWM modules belonging to the same CPU-Subsystem (as partitioned using their CPUSEL bits) start counting

3.6.2.83 ADC_MMR_OVRD_CTL Register (Offset = 1490h) [Reset = 00000000h]

ADC_MMR_OVRD_CTL is shown in Figure 3-93 and described in Table 3-108.

Return to the Summary Table.

ADC MMR Override control register for DFT: Control ADC enable override

Figure 3-93 ADC_MMR_OVRD_CTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-108 ADC_MMR_OVRD_CTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.6.2.84 ADC_MMR_OVRD_VAL Register (Offset = 1494h) [Reset = 00000000h]

ADC_MMR_OVRD_VAL is shown in Figure 3-94 and described in Table 3-109.

Return to the Summary Table.

ADC MMR Override value register for DFT : Value of ADC enable override

Figure 3-94 ADC_MMR_OVRD_VAL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-109 ADC_MMR_OVRD_VAL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.6.2.85 VREGCONFIGDEBUG Register (Offset = 1498h) [Reset = 00X0X0X0h]

VREGCONFIGDEBUG is shown in Figure 3-95 and described in Table 3-110.

Return to the Summary Table.

VREG Configuration Debug Register

Figure 3-95 VREGCONFIGDEBUG Register
3130292827262524
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-XhR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVED
R/W-XhR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-XhR/W-0hR/W-0h
Table 3-110 VREGCONFIGDEBUG Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0h
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/WXh
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/WXh
14-7RESERVEDR/W0hReserved
6-5RESERVEDR/W0hReserved
4RESERVEDR/WXh
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

3.6.2.86 VREGCONFIGDFT Register (Offset = 149Ch) [Reset = 00000000h]

VREGCONFIGDFT is shown in Figure 3-96 and described in Table 3-111.

Return to the Summary Table.

VREG Configuration DFT Register

Figure 3-96 VREGCONFIGDFT Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVED
R/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-111 VREGCONFIGDFT Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR/W0h
11-4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.6.2.87 AM13SPAREIREFENSOCLOCK Register (Offset = 14A0h) [Reset = 00000000h]

AM13SPAREIREFENSOCLOCK is shown in Figure 3-97 and described in Table 3-112.

Return to the Summary Table.

AM13 Spare IREFEN SOC LOCK Reg

Figure 3-97 AM13SPAREIREFENSOCLOCK Register
313029282726252423222120191817161514131211109876543210
RESERVEDSPARE
R/W-0hR/W-0h
Table 3-112 AM13SPAREIREFENSOCLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-0SPARER/W0hSpare IREFEN SOC LOCK Register

3.6.2.88 AM13SPARESOCLOCK2 Register (Offset = 14A4h) [Reset = 00000001h]

AM13SPARESOCLOCK2 is shown in Figure 3-98 and described in Table 3-113.

Return to the Summary Table.

AM13 Spare SOC LOCK Reg 2

Figure 3-98 AM13SPARESOCLOCK2 Register
3130292827262524
SPARE
R/W-0h
2322212019181716
SPARE
R/W-0h
15141312111098
SPARE
R/W-0h
76543210
SPARESRAM3_STATIC_MUX_SEL
R/W-0hR/W-1h
Table 3-113 AM13SPARESOCLOCK2 Register Field Descriptions
BitFieldTypeResetDescription
31-1SPARER/W0hSpare SOC LOCK Register 2
0SRAM3_STATIC_MUX_SELR/W1hSRAM3 static mux select between CBUS and SBUS
0h = SBUS path is selected
1h = CBUS path is selected

3.6.2.89 AM13SPARESOCLOCK3 Register (Offset = 14A8h) [Reset = 00000000h]

AM13SPARESOCLOCK3 is shown in Figure 3-99 and described in Table 3-114.

Return to the Summary Table.

AM13 Spare SOC LOCK Reg 3

Figure 3-99 AM13SPARESOCLOCK3 Register
313029282726252423222120191817161514131211109876543210
SPARE
R/W-0h
Table 3-114 AM13SPARESOCLOCK3 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPARER/W0hSpare SOC LOCK Register 3

3.6.2.90 AM13SPARESOCLOCK4 Register (Offset = 14ACh) [Reset = 00000000h]

AM13SPARESOCLOCK4 is shown in Figure 3-100 and described in Table 3-115.

Return to the Summary Table.

AM13 Spare SOC LOCK Reg 4

Figure 3-100 AM13SPARESOCLOCK4 Register
313029282726252423222120191817161514131211109876543210
SPARE
R/W-0h
Table 3-115 AM13SPARESOCLOCK4 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPARER/W0hSpare SOC LOCK Register 4

3.6.2.91 PWREN Register (Offset = 2800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-101 and described in Table 3-116.

Return to the Summary Table.

IP Enable Register

Figure 3-101 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-116 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.92 RSTCTL Register (Offset = 2804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-102 and described in Table 3-117.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-102 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-117 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.93 STAT Register (Offset = 2814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-103 and described in Table 3-118.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-103 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-118 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.94 PWREN Register (Offset = 4800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-104 and described in Table 3-119.

Return to the Summary Table.

IP Enable Register

Figure 3-104 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-119 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.95 RSTCTL Register (Offset = 4804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-105 and described in Table 3-120.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-105 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-120 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.96 STAT Register (Offset = 4814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-106 and described in Table 3-121.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-106 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-121 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.97 PWREN Register (Offset = 000D0800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-107 and described in Table 3-122.

Return to the Summary Table.

IP Enable Register

Figure 3-107 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-122 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.98 RSTCTL Register (Offset = 000D0804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-108 and described in Table 3-123.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-108 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-123 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.99 STAT Register (Offset = 000D0814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-109 and described in Table 3-124.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-109 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-124 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.100 PWREN Register (Offset = 000E8800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-110 and described in Table 3-125.

Return to the Summary Table.

IP Enable Register

Figure 3-110 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-125 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.101 RSTCTL Register (Offset = 000E8804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-111 and described in Table 3-126.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-111 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-126 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.102 STAT Register (Offset = 000E8814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-112 and described in Table 3-127.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-112 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-127 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.103 PWREN Register (Offset = 000F0800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-113 and described in Table 3-128.

Return to the Summary Table.

IP Enable Register

Figure 3-113 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-128 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.104 RSTCTL Register (Offset = 000F0804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-114 and described in Table 3-129.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-114 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-129 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.105 STAT Register (Offset = 000F0814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-115 and described in Table 3-130.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-115 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-130 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.106 PWREN Register (Offset = 000F2800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-116 and described in Table 3-131.

Return to the Summary Table.

IP Enable Register

Figure 3-116 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-131 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.107 RSTCTL Register (Offset = 000F2804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-117 and described in Table 3-132.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-117 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-132 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.108 STAT Register (Offset = 000F2814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-118 and described in Table 3-133.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-118 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-133 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.109 PWREN Register (Offset = 000F4800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-119 and described in Table 3-134.

Return to the Summary Table.

IP Enable Register

Figure 3-119 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-134 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.110 RSTCTL Register (Offset = 000F4804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-120 and described in Table 3-135.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-120 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-135 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.111 STAT Register (Offset = 000F4814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-121 and described in Table 3-136.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-121 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-136 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.112 PWREN Register (Offset = 000F6800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-122 and described in Table 3-137.

Return to the Summary Table.

IP Enable Register

Figure 3-122 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-137 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.113 RSTCTL Register (Offset = 000F6804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-123 and described in Table 3-138.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-123 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-138 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.114 STAT Register (Offset = 000F6814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-124 and described in Table 3-139.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-124 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-139 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.115 PWREN Register (Offset = 00116800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-125 and described in Table 3-140.

Return to the Summary Table.

IP Enable Register

Figure 3-125 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-140 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.116 RSTCTL Register (Offset = 00116804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-126 and described in Table 3-141.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-126 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-141 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.117 STAT Register (Offset = 00116814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-127 and described in Table 3-142.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-127 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-142 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.118 PWREN Register (Offset = 00180800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-128 and described in Table 3-143.

Return to the Summary Table.

IP Enable Register

Figure 3-128 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-143 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.119 RSTCTL Register (Offset = 00180804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-129 and described in Table 3-144.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-129 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-144 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.120 STAT Register (Offset = 00180814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-130 and described in Table 3-145.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-130 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-145 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.121 PWREN Register (Offset = 00188800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-131 and described in Table 3-146.

Return to the Summary Table.

IP Enable Register

Figure 3-131 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-146 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.122 RSTCTL Register (Offset = 00188804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-132 and described in Table 3-147.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-132 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-147 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.123 STAT Register (Offset = 00188814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-133 and described in Table 3-148.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-133 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-148 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.124 PWREN Register (Offset = 001B0800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-134 and described in Table 3-149.

Return to the Summary Table.

IP Enable Register

Figure 3-134 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-149 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.125 RSTCTL Register (Offset = 001B0804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-135 and described in Table 3-150.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-135 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-150 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.126 STAT Register (Offset = 001B0814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-136 and described in Table 3-151.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-136 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-151 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.127 PWREN Register (Offset = 001B2800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-137 and described in Table 3-152.

Return to the Summary Table.

IP Enable Register

Figure 3-137 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-1h
Table 3-152 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W1hIP Enable
0h = 0
1h = 1

3.6.2.128 RSTCTL Register (Offset = 001B2804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-138 and described in Table 3-153.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-138 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-153 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.129 STAT Register (Offset = 001B2814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-139 and described in Table 3-154.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-139 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-154 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.130 PWREN Register (Offset = 00630800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-140 and described in Table 3-155.

Return to the Summary Table.

IP Enable Register

Figure 3-140 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-155 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.131 RSTCTL Register (Offset = 00630804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-141 and described in Table 3-156.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-141 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-156 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.132 STAT Register (Offset = 00630814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-142 and described in Table 3-157.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-142 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-157 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.133 PWREN Register (Offset = 00632800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-143 and described in Table 3-158.

Return to the Summary Table.

IP Enable Register

Figure 3-143 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-158 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.134 RSTCTL Register (Offset = 00632804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-144 and described in Table 3-159.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-144 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-159 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.135 STAT Register (Offset = 00632814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-145 and described in Table 3-160.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-145 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-160 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.136 PWREN Register (Offset = 00634800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-146 and described in Table 3-161.

Return to the Summary Table.

IP Enable Register

Figure 3-146 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-161 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.137 RSTCTL Register (Offset = 00634804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-147 and described in Table 3-162.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-147 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-162 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.138 STAT Register (Offset = 00634814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-148 and described in Table 3-163.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-148 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-163 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.139 PWREN Register (Offset = 00670800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-149 and described in Table 3-164.

Return to the Summary Table.

IP Enable Register

Figure 3-149 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-164 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.140 RSTCTL Register (Offset = 00670804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-150 and described in Table 3-165.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-150 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-165 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.141 STAT Register (Offset = 00670814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-151 and described in Table 3-166.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-151 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-166 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.142 PWREN Register (Offset = 00672800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-152 and described in Table 3-167.

Return to the Summary Table.

IP Enable Register

Figure 3-152 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-167 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.143 RSTCTL Register (Offset = 00672804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-153 and described in Table 3-168.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-153 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-168 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.144 STAT Register (Offset = 00672814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-154 and described in Table 3-169.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-154 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-169 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh

3.6.2.145 PWREN Register (Offset = 00674800h) [Reset = 00XXXXXXh]

PWREN is shown in Figure 3-155 and described in Table 3-170.

Return to the Summary Table.

IP Enable Register

Figure 3-155 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-XXXXh
15141312111098
RESERVED
R/W-XXXXh
76543210
RESERVEDENABLE
R/W-XXXXhR/W-0h
Table 3-170 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Enable State Change -- 0x26
26h = 0x26
23-1RESERVEDR/WXXXXh
0ENABLER/W0hIP Enable
0h = 0
1h = 1

3.6.2.146 RSTCTL Register (Offset = 00674804h) [Reset = 00XXXXXXh]

RSTCTL is shown in Figure 3-156 and described in Table 3-171.

Return to the Summary Table.

Power Control Register - Write Only Register, Always Read as 0

Figure 3-156 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-XXXXh
15141312111098
RESERVED
W-XXXXh
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-XXXXhW-0hW-0h
Table 3-171 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to Allow Reset -- 0xb1
B1h = 0xb1
23-2RESERVEDWXXXXh
1RESETSTKYCLRW0hClear the RESET STICKY Bit
1h = 1
0RESETASSERTW0hAssert Reset to IP Domain.
1h = 1

3.6.2.147 STAT Register (Offset = 00674814h) [Reset = 0000XXXXh]

STAT is shown in Figure 3-157 and described in Table 3-172.

Return to the Summary Table.

IP State Register - Read Only

Figure 3-157 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-XXXXh
76543210
RESERVED
R-XXXXh
Table 3-172 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hIP has been Reset
0h = 0
1h = 1
15-0RESERVEDRXXXXh