SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

24.3.2 UNICOMMI2CC_REGS Registers

Table 24-20 lists the memory-mapped registers for the UNICOMMI2CC_REGS registers. All register offset addresses not listed in Table 24-20 should be considered as reserved locations and the register contents should not be modified.

Table 24-20 UNICOMMI2CC_REGS Registers
OffsetAcronymRegister NameSection
0hCLKDIVClock DividerGo
8hCLKSELClock Source Selection/Enable.Go
18hPDBGCTLPeripheral Debug ControlGo
20hIIDXInterrupt indexGo
28hIMASKInterrupt maskGo
30hRISRaw interrupt statusGo
38hMISMasked interrupt statusGo
40hISETInterrupt setGo
48hICLRInterrupt clearGo
58hIMASKInterrupt maskGo
60hRISRaw interrupt statusGo
68hMISMasked interrupt statusGo
70hISETInterrupt setGo
88hIMASKInterrupt maskGo
90hRISRaw interrupt statusGo
98hMISMasked interrupt statusGo
A0hISETInterrupt setGo
E4hINTCTLInterrupt control registerGo
100hCTRControl RegisterGo
104hCRConfigurationGo
108hSRStatus RegisterGo
10ChIFLSInterrupt FIFO Level Select RegisterGo
110hTPRTimer PeriodGo
118hGFCTLI2C Glitch Filter ControlGo
11ChBMONBus MonitorGo
120hTXDATATXDataGo
124hRXDATARXDataGo
128hPECSRPEC status registerGo
14ChTATarget Address RegisterGo
150hTIMEOUT_CNTI2C Timeout Count RegisterGo
154hTIMEOUT_CTLI2C Timeout Count Control RegisterGo
158hPECCTLI2C PEC control registerGo

Complex bit access types are encoded to fit into small table cells. Table 24-21 shows the codes that are used for access types in this section.

Table 24-21 UNICOMMI2CC_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

24.3.2.1 CLKDIV Register (Offset = 0h) [Reset = 00000000h]

CLKDIV is shown in Figure 24-21 and described in Table 24-22.

Return to the Summary Table.

This register is used to specify the module-specific divide ratio of the I2CC functional clock (I2Cclk).

Figure 24-21 CLKDIV Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDRATIO
R/W-0hR/W-0h
Table 24-22 CLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0RATIOR/W0hSelects divide ratio of module clock Division factor 0 : DIV_BY_1 1 : DIV_BY_2 .... 63: DIV_BY_64
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 3
3h = Divide clock source by 4
4h = Divide clock source by 5
5h = Divide clock source by 6
6h = Divide clock source by 7
7h = Divide clock source by 8

24.3.2.2 CLKSEL Register (Offset = 8h) [Reset = 00000000h]

CLKSEL is shown in Figure 24-22 and described in Table 24-23.

Return to the Summary Table.

I2CC Clock Source Selection.

Figure 24-22 CLKSEL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDMCLKDIV2RESERVED
R/W-0hR/W-0hR/W-0h
Table 24-23 CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3MCLKDIV2R/W0hEnables MCLKDIV2 as the UNICOMM I2CC clock source.
0h = Does not select this clock as a source
1h = Select this clock as a source
2-0RESERVEDR/W0h

24.3.2.3 PDBGCTL Register (Offset = 18h) [Reset = 00000000h]

PDBGCTL is shown in Figure 24-23 and described in Table 24-24.

Return to the Summary Table.

I2CC Debug Control. This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input.

Figure 24-23 PDBGCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSOFTFREE
R/W-0hR/W-0hR/W-0h
Table 24-24 PDBGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1SOFTR/W1hSoft Halt Boundary Control. This function is only available, if [FREE] is set to 'STOP'
0h = Not supported
1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0FREER/W1hFree Run Control.
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

24.3.2.4 IIDX Register (Offset = 20h) [Reset = 00000000h]

IIDX is shown in Figure 24-24 and described in Table 24-25.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index.

Figure 24-24 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 24-25 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hI2CC Interrupt Vector Value. This field provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS. 15h-1Fh = Reserved.
00h = No Interrupt Pending.
01h = Receive Done Flag.
02h = Transmit Done Flag.
03h = Receive FIFO Event.
04h = Transmit FIFO Event.
5h = RX FIFO Full Event/Interrupt Pending.
6h = TX FIFO Empty Event/Interrupt Pending.
08h = Address/Data NACK.
09h = START Event.
0Ah = STOP Event.
0Bh = Arbitration Lost.
Ch = PEC Receive Error Event. This event is only available on Advanced I2CC instances.
Dh = Timeout Counter A Event.
Eh = Timeout Counter B Event.
10h = DMA DONE on Channel RX.
11h = DMA DONE on Channel TX.

24.3.2.5 IMASK Register (Offset = 28h) [Reset = 00000000h]

IMASK is shown in Figure 24-25 and described in Table 24-26.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 24-25 IMASK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDDMA_DONE_TX
R/W-0hR/W-0h
15141312111098
DMA_DONE_RXRESERVEDTIMEOUTBTIMEOUTAPEC_RX_ERRARBLOSTSTOPSTART
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
NACKRESERVEDTXEMPTYRXFULLTXTRGRXTRGTXDONERXDONE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 24-26 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/W0h
16DMA_DONE_TXR/W0hI2CC DMA Done on TX Event Channel Interrupt Mask. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA, indicating all the transactions have completed.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
15DMA_DONE_RXR/W0hI2CC DMA Done on RX Event Channel Interrupt Mask. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA indicating all the transactions have completed.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
14RESERVEDR/W0h
13TIMEOUTBR/W0hI2CC Timeout Counter B Interrupt Mask. This interrupt is raised when the SCL line is continously high for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLB register.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12TIMEOUTAR/W0hI2CC Timeout Counter A Interrupt Mask. This interrupt is raised when the SCL line is continously low for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLA register.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11PEC_RX_ERRR/W0hI2CC Receive PEC Error Interrupt Mask. This interrupt is raised when the PEC calculated by the I2CC does not match received PEC. This interrupt is only available on Advanced I2CC instances.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10ARBLOSTR/W0hI2CC Arbitration Lost Interrupt Mask. This flag indicates that the I2CC has lost an arbitration contest with another Controller in a multi-controller system.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9STOPR/W0hI2CC STOP Detection Interrupt Mask. This interrupt is raised when a STOP condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8STARTR/W0hI2CC START Detection Interrupt Mask. This interrupt is raised when a START condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7NACKR/W0hI2CC Address/Data NACK Interrupt Mask. This interrupt is raised when an address or data NACK is received by the I2CC.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6RESERVEDR/W0h
5TXEMPTYR/W0hI2CC TX FIFO Empty Interrupt Mask. This interrupt is raised when all data has been shifted out of the TX FIFO and the I2CC transmitter goes idle.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4RXFULLR/W0hI2CC RX FIFO Full Interrupt Mask. This interrupt is raised when the RX FIFO is full.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3TXTRGR/W0hI2CC Transmit Trigger Interrupt Mask. This interrupt is raised when the TX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2RXTRGR/W0hI2CC Receive Trigger Interrupt Mask. This interrupt is raised when the RX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1TXDONER/W0hI2CC Transmit Done Interrupt Mask. This interrupt is raised when a burst length of CTR.BLEN bytes is transmitted. For variants where the BLEN register is not available, it is raised after each byte is transmitted. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '0'.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0RXDONER/W0hI2CC Receive Done Interrupt Mask. This interrupt is raised when a burst length of CTR.BLEN bytes is received. For variants where the BLEN register is not available, it is raised after each byte is received. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '1'.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

24.3.2.6 RIS Register (Offset = 30h) [Reset = 00000000h]

RIS is shown in Figure 24-26 and described in Table 24-27.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 24-26 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMA_DONE_TX
R-0hR-0h
15141312111098
DMA_DONE_RXRESERVEDTIMEOUTBTIMEOUTAPEC_RX_ERRARBLOSTSTOPSTART
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
NACKRESERVEDTXEMPTYRXFULLTXTRGRXTRGTXDONERXDONE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 24-27 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DMA_DONE_TXR0hI2CC DMA Done on TX Event Channel Interrupt Raw Status. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA, indicating all the transactions have completed.
0h = Interrupt did not occur
1h = Interrupt occurred
15DMA_DONE_RXR0hI2CC DMA Done on RX Event Channel Interrupt Raw Status. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA indicating all the transactions have completed.
0h = Interrupt did not occur
1h = Interrupt occurred
14RESERVEDR0h
13TIMEOUTBR0hI2CC Timeout Counter B Interrupt Raw Status. This interrupt is raised when the SCL line is continously high for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLB register.
0h = Interrupt did not occur
1h = Interrupt occurred
12TIMEOUTAR0hI2CC Timeout Counter A Interrupt Raw Status. This interrupt is raised when the SCL line is continously low for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLA register.
0h = Interrupt did not occur
1h = Interrupt occurred
11PEC_RX_ERRR0hI2CC Receive PEC Error Interrupt Raw Status. This interrupt is raised when the PEC calculated by the I2CC does not match received PEC. This interrupt is only available on Advanced I2CC instances.
0h = Interrupt did not occur
1h = Interrupt Occured
10ARBLOSTR0hI2CC Arbitration Lost Interrupt Raw Status. This flag indicates that the I2CC has lost an arbitration contest with another Controller in a multi-controller system.
0h = Interrupt did not occur
1h = Interrupt occurred
9STOPR0hI2CC STOP Detection Interrupt Raw Status. This interrupt is raised when a STOP condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Interrupt did not occur
1h = Interrupt occurred
8STARTR0hI2CC START Detection Interrupt Raw Status. This interrupt is raised when a START condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Interrupt did not occur
1h = Interrupt occurred
7NACKR0hI2CC Address/Data NACK Interrupt Raw Status. This interrupt is raised when an address or data NACK is received by the I2CC.
0h = Interrupt did not occur
1h = Interrupt occurred
6RESERVEDR0h
5TXEMPTYR0hI2CC TX FIFO Empty Interrupt Raw Status. This interrupt is raised when all data has been shifted out of the TX FIFO and the I2CC transmitter goes idle.
0h = Interrupt did not occur
1h = Interrupt occurred
4RXFULLR0hI2CC RX FIFO Full Interrupt Raw Status. This interrupt is raised when the RX FIFO is full.
0h = Interrupt did not occur
1h = Interrupt occurred
3TXTRGR0hI2CC Transmit Trigger Interrupt Raw Status. This interrupt is raised when the TX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Interrupt occurred
2RXTRGR0hI2CC Receive Trigger Interrupt Raw Status. This interrupt is raised when the RX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Interrupt occurred
1TXDONER0hI2CC Transmit Done Interrupt Raw Status. This interrupt is raised when a burst length of CTR.BLEN bytes is transmitted. For variants where the BLEN register is not available, it is raised after each byte is transmitted. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '0'.
0h = Interrupt did not occur
1h = Interrupt occurred
0RXDONER0hI2CC Receive Done Interrupt Raw Status. This interrupt is raised when a burst length of CTR.BLEN bytes is received. For variants where the BLEN register is not available, it is raised after each byte is received. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '1'.
0h = Interrupt did not occur
1h = Interrupt occurred

24.3.2.7 MIS Register (Offset = 38h) [Reset = 00000000h]

MIS is shown in Figure 24-27 and described in Table 24-28.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 24-27 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMA_DONE_TX
R-0hR-0h
15141312111098
DMA_DONE_RXRESERVEDTIMEOUTBTIMEOUTAPEC_RX_ERRARBLOSTSTOPSTART
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
NACKRESERVEDTXEMPTYRXFULLTXTRGRXTRGTXDONERXDONE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 24-28 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DMA_DONE_TXR0hI2CC DMA Done on TX Event Channel Interrupt Masked Status. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA, indicating all the transactions have completed.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
15DMA_DONE_RXR0hI2CC DMA Done on RX Event Channel Interrupt Masked Status. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA indicating all the transactions have completed.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
14RESERVEDR0h
13TIMEOUTBR0hI2CC Timeout Counter B Interrupt Masked Status. This interrupt is raised when the SCL line is continously high for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLB register.
0h = Clear interrupt mask
1h = Set interrupt mask
12TIMEOUTAR0hI2CC Timeout Counter A Interrupt Masked Status. This interrupt is raised when the SCL line is continously low for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLA register.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
11PEC_RX_ERRR0hI2CC Receive PEC Error Interrupt Masked Status. This interrupt is raised when the PEC calculated by the I2CC does not match received PEC. This interrupt is only available on Advanced I2CC instances.
0h = Clear interrupt mask
1h = Set interrupt mask
10ARBLOSTR0hI2CC Arbitration Lost Interrupt Masked Status. This flag indicates that the I2CC has lost an arbitration contest with another Controller in a multi-controller system.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
9STOPR0hI2CC STOP Detection Interrupt Masked Status. This interrupt is raised when a STOP condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
8STARTR0hI2CC START Detection Interrupt Masked Status. This interrupt is raised when a START condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
7NACKR0hI2CC Address/Data NACK Interrupt Masked Status. This interrupt is raised when an address or data NACK is received by the I2CC.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
6RESERVEDR0h
5TXEMPTYR0hI2CC TX FIFO Empty Interrupt Masked Status. This interrupt is raised when all data has been shifted out of the TX FIFO and the I2CC transmitter goes idle.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
4RXFULLR0hI2CC RX FIFO Full Interrupt Masked Status. This interrupt is raised when the RX FIFO is full.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
3TXTRGR0hI2CC Transmit Trigger Interrupt Masked Status. This interrupt is raised when the TX FIFO condition programmed by the IFLS register is met.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
2RXTRGR0hI2CC Receive Trigger Interrupt Masked Status. This interrupt is raised when the RX FIFO condition programmed by the IFLS register is met.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
1TXDONER0hI2CC Transmit Done Interrupt Masked Status. This interrupt is raised when a burst length of CTR.BLEN bytes is transmitted. For variants where the BLEN register is not available, it is raised after each byte is transmitted. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '0'.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
0RXDONER0hI2CC Receive Done Interrupt Masked Status. This interrupt is raised when a burst length of CTR.BLEN bytes is received. For variants where the BLEN register is not available, it is raised after each byte is received. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '1'.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred

24.3.2.8 ISET Register (Offset = 40h) [Reset = 00000000h]

ISET is shown in Figure 24-28 and described in Table 24-29.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 24-28 ISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVEDDMA_DONE_TX
W-0hW-0h
15141312111098
DMA_DONE_RXRESERVEDTIMEOUTBTIMEOUTAPEC_RX_ERRARBLOSTSTOPSTART
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
NACKRESERVEDTXEMPTYRXFULLTXTRGRXTRGTXDONERXDONE
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 24-29 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDW0h
16DMA_DONE_TXW0hSet I2CC DMA Done on TX Event Channel Interrupt. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA, indicating all the transactions have completed.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
15DMA_DONE_RXW0hSet I2CC DMA Done on RX Event Channel Interrupt. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA indicating all the transactions have completed.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
14RESERVEDW0h
13TIMEOUTBW0hSet I2CC Timeout Counter B Interrupt. This interrupt is raised when the SCL line is continously high for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLB register.
0h = Writing 0 has no effect
1h = Set interrupt
12TIMEOUTAW0hSet I2CC Timeout Counter A Interrupt. This interrupt is raised when the SCL line is continously low for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLA register.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
11PEC_RX_ERRW0hSet I2CC Receive PEC Error Interrupt. This interrupt is raised when the PEC calculated by the I2CC does not match received PEC. This interrupt is only available on Advanced I2CC instances.
0h = Writing 0 has no effect
1h = Set interrupt
10ARBLOSTW0hSet I2CC Arbitration Lost Interrupt. This flag indicates that the I2CC has lost an arbitration contest with another Controller in a multi-controller system.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
9STOPW0hSet I2CC STOP Detection Interrupt. This interrupt is raised when a STOP condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
8STARTW0hSet I2CC START Detection Interrupt. This interrupt is raised when a START condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
7NACKW0hSet I2CC Address/Data NACK Interrupt. This interrupt is raised when an address or data NACK is received by the I2CC.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
6RESERVEDW0h
5TXEMPTYW0hSet I2CC TX FIFO Empty Interrupt. This interrupt is raised when all data has been shifted out of the TX FIFO and the I2CC transmitter goes idle.
0h = Writing 0 has no effect
1h = Set Interrupt
4RXFULLW0hSet I2CC RX FIFO Full Interrupt. This interrupt is raised when the RX FIFO is full.
0h = Writing 0 has no effect
1h = Set Interrupt
3TXTRGW0hSet I2CC Transmit Trigger Interrupt. This interrupt is raised when the TX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2RXTRGW0hSet I2CC Receive Trigger Interrupt. This interrupt is raised when the RX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1TXDONEW0hSet I2CC Transmit Done Interrupt. This interrupt is raised when a burst length of CTR.BLEN bytes is transmitted. For variants where the BLEN register is not available, it is raised after each byte is transmitted. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '0'.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
0RXDONEW0hSet I2CC Receive Done Interrupt. This interrupt is raised when a burst length of CTR.BLEN bytes is received. For variants where the BLEN register is not available, it is raised after each byte is received. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '1'.
0h = Writing 0 has no effect
1h = Set Interrupt Mask

24.3.2.9 ICLR Register (Offset = 48h) [Reset = 00000000h]

ICLR is shown in Figure 24-29 and described in Table 24-30.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 24-29 ICLR Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVEDDMA_DONE_TX
W-0hW-0h
15141312111098
DMA_DONE_RXRESERVEDTIMEOUTBTIMEOUTAPEC_RX_ERRARBLOSTSTOPSTART
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
NACKRESERVEDTXEMPTYRXFULLTXTRGRXTRGTXDONERXDONE
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 24-30 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDW0h
16DMA_DONE_TXW0hClear I2CC DMA Done on TX Event Channel Interrupt. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA, indicating all the transactions have completed.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
15DMA_DONE_RXW0hClear I2CC DMA Done on RX Event Channel Interrupt. This interrupt is raised when the DONE signal is sent to the I2CC from a DMA indicating all the transactions have completed.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
14RESERVEDW0h
13TIMEOUTBW0hClear I2CC Timeout Counter B Interrupt. This interrupt is raised when the SCL line is continously high for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLB register.
0h = Writing 0 has no effect
1h = Clear Interrupt
12TIMEOUTAW0hClear I2CC Timeout Counter A Interrupt. This interrupt is raised when the SCL line is continously low for longer than the clock timeout period programmed by the TIMEOUT_CTL.TCNTLA register.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
11PEC_RX_ERRW0hClear I2CC Receive PEC Error Interrupt. This interrupt is raised when the PEC calculated by the I2CC does not match received PEC. This interrupt is only available on Advanced I2CC instances.
0h = Writing 0 has no effect
1h = Clear Interrupt
10ARBLOSTW0hClear I2CC Arbitration Lost Interrupt. This flag indicates that the I2CC has lost an arbitration contest with another Controller in a multi-controller system.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
9STOPW0hClear I2CC STOP Detection Interrupt. This interrupt is raised when a STOP condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
8STARTW0hClear I2CC START Detection Interrupt. This interrupt is raised when a START condition is detected on the bus, either generated by the current I2CC or another I2C Controller when in multi-master mode.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
7NACKW0hClear I2CC Address/Data NACK Interrupt. This interrupt is raised when an address or data NACK is received by the I2CC.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
6RESERVEDW0h
5TXEMPTYW0hClear I2CC TX FIFO Empty Interrupt. This interrupt is raised when all data has been shifted out of the TX FIFO and the I2CC transmitter goes idle.
0h = Writing 0 has no effect
1h = Clear Interrupt
4RXFULLW0hClear I2CC RX FIFO Full Interrupt. This interrupt is raised when the RX FIFO is full.
0h = Writing 0 has no effect
1h = Clear Interrupt
3TXTRGW0hClear I2CC Transmit Trigger Interrupt Mask. This interrupt is raised when the TX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2RXTRGW0hClear I2CC Receive Trigger Interrupt Mask. This interrupt is raised when the RX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1TXDONEW0hClear I2CC Transmit Done Interrupt. This interrupt is raised when a burst length of CTR.BLEN bytes is transmitted. For variants where the BLEN register is not available, it is raised after each byte is transmitted. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '0'.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
0RXDONEW0hClear I2CC Receive Done Interrupt. This interrupt is raised when a burst length of CTR.BLEN bytes is received. For variants where the BLEN register is not available, it is raised after each byte is received. In the case of a quick command, the interrupt is raised when a quick command with R/Wn bit set to '1'.
0h = Writing 0 has no effect
1h = Set Interrupt Mask

24.3.2.10 IMASK Register (Offset = 58h) [Reset = 00000000h]

IMASK is shown in Figure 24-30 and described in Table 24-31.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 24-30 IMASK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRXTRGRESERVED
R/W-0hR/W-0hR/W-0h
Table 24-31 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2RXTRGR/W0hI2CC Receive DMA Trigger Mask. The DMA is triggered when the RX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1-0RESERVEDR/W0h

24.3.2.11 RIS Register (Offset = 60h) [Reset = 00000000h]

RIS is shown in Figure 24-31 and described in Table 24-32.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 24-31 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRXTRGRESERVED
R-0hR-0hR-0h
Table 24-32 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2RXTRGR0hI2CC Receive DMA Trigger Raw Status. The DMA is triggered when the RX FIFO condition programmed by the IFLS register is met.
0h = Interrupt did not occur
1h = Interrupt occurred
1-0RESERVEDR0h

24.3.2.12 MIS Register (Offset = 68h) [Reset = 00000000h]

MIS is shown in Figure 24-32 and described in Table 24-33.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the ICLR register bit.

Figure 24-32 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRXTRGRESERVED
R-0hR-0hR-0h
Table 24-33 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2RXTRGR0hI2CC Receive DMA Trigger Masked Status. The DMA is triggered when the RX FIFO condition programmed by the IFLS register is met.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
1-0RESERVEDR0h

24.3.2.13 ISET Register (Offset = 70h) [Reset = 00000000h]

ISET is shown in Figure 24-33 and described in Table 24-34.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 24-33 ISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDRXTRGRESERVED
W-0hW-0hW-0h
Table 24-34 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDW0h
2RXTRGW0hSet I2CC Receive DMA Trigger. The DMA is triggered when the RX FIFO condition programmed by the IFLS register is met.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
1-0RESERVEDW0h

24.3.2.14 IMASK Register (Offset = 88h) [Reset = 00000000h]

IMASK is shown in Figure 24-34 and described in Table 24-35.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 24-34 IMASK Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDTXTRGRESERVED
R/W-0hR/W-0hR/W-0h
Table 24-35 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3TXTRGR/W0hI2CC Transmit DMA Trigger Mask. The DMA is triggered when the TX FIFO condition programmed by the IFLS register is met.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2-0RESERVEDR/W0h

24.3.2.15 RIS Register (Offset = 90h) [Reset = 00000000h]

RIS is shown in Figure 24-35 and described in Table 24-36.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 24-35 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTXTRGRESERVED
R-0hR-0hR-0h
Table 24-36 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3TXTRGR0hI2CC Transmit DMA Trigger Raw Status. The DMA is triggered when the TX FIFO condition programmed by the IFLS register is met.
0h = Interrupt did not occur
1h = Interrupt occurred
2-0RESERVEDR0h

24.3.2.16 MIS Register (Offset = 98h) [Reset = 00000000h]

MIS is shown in Figure 24-36 and described in Table 24-37.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 24-36 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTXTRGRESERVED
R-0hR-0hR-0h
Table 24-37 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3TXTRGR0hI2CC Transmit DMA Trigger Masked Status. The DMA is triggered when the TX FIFO condition programmed by the IFLS register is met.
0h = Interrupt did not occur or mask was not enabled
1h = Interrupt occurred
2-0RESERVEDR0h

24.3.2.17 ISET Register (Offset = A0h) [Reset = 00000000h]

ISET is shown in Figure 24-37 and described in Table 24-38.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 24-37 ISET Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDTXTRGRESERVED
W-0hW-0hW-0h
Table 24-38 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3TXTRGW0hSet I2CC Transmit DMA Trigger. The DMA is triggered when the TX FIFO condition programmed by the IFLS register is met.
0h = Writing 0 has no effect
1h = Set Interrupt
2-0RESERVEDW0h

24.3.2.18 INTCTL Register (Offset = E4h) [Reset = 00000000h]

INTCTL is shown in Figure 24-38 and described in Table 24-39.

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Interrupt Control Register.

Figure 24-38 INTCTL Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDINTEVAL
W-0hW-0h
Table 24-39 INTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0INTEVALW0hWriting a 1 to this field re-evaluates the interrupt sources.
0h = Writing 0 has no effect
1h = Interrupt Eval

24.3.2.19 CTR Register (Offset = 100h) [Reset = 00000000h]

CTR is shown in Figure 24-39 and described in Table 24-40.

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I2CC Control Register. Configures the I2CC operation.

Figure 24-39 CTR Register
3130292827262524
RESERVEDBLEN
R/W-0hR/W-0h
2322212019181716
BLEN
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSUSPENDRD_ON_TXEMPTYACKOENACKSTOPSTARTFRM_START
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 24-40 CTR Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0h
27-16BLENR/W0hI2CC Transaction Length. This field contains the programmed length of bytes of the next transaction. For variants that don't have the BLEN register, the BLEN is hardcoded to a value of 1.
0h = Smallest value
FFFh = Highest possible value
15-7RESERVEDR/W0h
6SUSPENDR/W0hSuspend External Communication. When this bit is set, I2CC communication on the external bus is suspended after the I2CC FSM goes idle (SR.BUSY reads '0').
0h = Normal communication
1h = External communication suspended
5RD_ON_TXEMPTYR/W0hRead on TX EMPTY Enable/Disable. This feature initiates an I2CC write followed by a I2CC read without needing application intervention.
0h = No special behavior
1h = The I2CC will transmit all the bytes from TX FIFO, issue a RESTART and receive data as per programmed burst length (BLEN). This bit is ignored if DIR bit is not set to READ.
4ACKOENR/W0hACK Override Enable When ACKOEN is enabled: 1. I2CC receives data according to the configured burst length (BLEN). 2. Upon receiving the complete data burst, I2CC generates a RXDONE interrupt. 3. The I2CC then holds SCL line low (clock stretching) during the acknowledge phase. 4. This pause gives the application time to update the ACKOVAL register. At this point, application has two options: Option 1: Terminate transaction 1. Set ACKOVAL to send a NACK. 2. The I2CC will automatically generate a STOP condition after the NACK. Option 2: Continue transaction 1. Clear ACKOVAL to send an ACK. 2. Update any other settings as needed. 3. The transaction will proceed based on the new configuration. This mechanism allows the application to control the transaction flow after each data burst is received. Note: In some variants, when BLEN register is not available, the design implements a hardcoded BLEN value of '1'. Consult your device datasheet.
0h = No special behavior
1h = Acknowledge Override Feature Enabled
3ACKR/W0hFinal Data Acknowledge Value. Determines whether a ACK or NACK is automatically sent by the I2CC after the last byte, of length 'N', are received from the target. This setting is used when CTR.ACKOEN=0.
0h = The last received data byte of a transaction is not acknowledged automatically.
1h = The last received data byte of a transaction is acknowledged automatically.
2STOPR/W0hEnable STOP Condition Generation. I2CC is enabled to send the STOP condition on the bus at the end of the current transaction, per the I2C protocol.
0h = The controller does not generate the STOP condition.
1h = The controller generates the STOP condition.
1STARTR/W0hEnable START Condition Generation. I2CC is enabled to send the START condition on the bus per the I2C protocol, when CTR.FRM_START is also set.
0h = The controller does not generate the START condition.
1h = The controller generates the START or repeated START condition.
0FRM_STARTR/W0hFrame Start. Start the transaction on the I2C bus according to the programmed settings.
0h = Write of '0' has no effect. Reads back '0' when there is no ongoing transaction
1h = When written to '1', a new transaction is started. Has no effect if there is an ongoing transaction. Reads back as '1' if the transaction is ongoing

24.3.2.20 CR Register (Offset = 104h) [Reset = 00000000h]

CR is shown in Figure 24-40 and described in Table 24-41.

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I2CC Configuration Register. Configures and enables the I2CC.

Figure 24-40 CR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCLKSTRETCHMCTLENABLE
R/W-0hR/W-0hR/W-0hR/W-0h
Table 24-41 CR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2CLKSTRETCHR/W0hClock Stretching Enable. This bit enables/disables clock stretching detection of the I2CC.
0h = Disables the clock stretching detection. This can be disabled if no Target on the bus does support clock stretching, so that the maximum speed on the bus can be reached.
1h = Enables the clock stretching detection. Enabling the clock stretching ensures compliance to the I2C standard but could limit the speed due the clock stretching.
1MCTLR/W0hMulti-Controller Mode Enable/Disable. In Multi-Controller mode, the SCL high time begins counting once the SCL line has been detected high. If this bit is not set, the SCL high time begins counting as soon as the SCL line has been set high by the I2CC.
0h = Disable MultiController mode.
1h = Enable MultiController mode.
0ENABLER/W0hEnable I2CC module. After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.
0h = Disables operation.
1h = Enables operation.

24.3.2.21 SR Register (Offset = 108h) [Reset = 00000000h]

SR is shown in Figure 24-41 and described in Table 24-42.

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I2CC Status Register. This status register indicates the current state of the I2CC.

Figure 24-41 SR Register
3130292827262524
RESERVEDBCNT
R-0hR-0h
2322212019181716
BCNT
R-0h
15141312111098
RESERVEDTXFFTXFERXFFRXFETXCLRRXCLRRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDBUSBSYIDLEARBLSTDATACKADRACKERRBUSY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 24-42 SR Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0h
27-16BCNTR0hBurst Transaction Count Status. This field contains the current count-down value of the transaction. This field is only available on Advanced I2CC instances.
0h = Smallest value
FFFh = Highest possible value
15RESERVEDR0h
14TXFFR0hTX FIFO Full Status.
0h = TX FIFO is not full
1h = TX FIFO is full
13TXFER1hTX FIFO Empty Status.
0h = TX FIFO is not empty
1h = TX FIFO is empty
12RXFFR0hRX FIFO Full Status.
0h = RX FIFO is not full
1h = RX FIFO is full
11RXFER1hRX FIFO Empty Status.
0h = RX FIFO is not empty
1h = RX FIFO is empty
10TXCLRR0hTX FIFO Clear Status.
0h = TX FIFO is not cleared
1h = TX FIFO clear is complete
9RXCLRR0hRX FIFO Clear Status.
0h = RX FIFO is not cleared
1h = RX FIFO clear is complete
8-7RESERVEDR0h
6BUSBSYR0hI2C Bus Busy Status. Indicates when the external line is busy 1. It is set when there is an ongoing transaction on the bus (i.e. if there is a START condition observed) or if SCL toggles. 2. It is cleared upon a STOP condition or when HIGH TIMEOUT occurs & SCL/SDA are both at their IDLE state. This bit reads back '0' when ACTIVE is cleared. The I2CC will wait until this bit is cleared before starting an I2C transaction. When enabling the controller initially, the application should wait for one I2C clock period, poll BUSBSY and start a transaction.
0h = The I2C bus is idle.
1h = SET
5IDLER1hI2CC FSM Idle Status. This bit is set when the internal I2CC state machine, rather than when the external bus, is not busy with an ongoing transaction i.e. there is no transmit/receive of data bytes, START, RESTART, Address or STOP signal generation occuring.
0h = The I2C controller is not idle.
1h = The I2C controller is idle.
4ARBLSTR0hArbitration Lost Status. This status bit indicates whether or not the I2CC won arbitration on the bus.
0h = The I2C controller won arbitration.
1h = The I2C controller lost arbitration.
3DATACKR0hData Acknowledge Status. This status bit indicates the acknowledgement status of the previously transmitted data byte.
0h = The transmitted data was acknowledged
1h = The transmitted data was not acknowledged.
2ADRACKR0hAcknowledge Address
0h = The transmitted address was acknowledged
1h = The transmitted address was not acknowledged.
1ERRR0hNACK Error Status. This status bit indicates the acknowledgement status of the previously transmitted target address or data byte.
0h = No error was detected on the last operation.
1h = An error occurred on the last operation.
0BUSYR0hI2CC FSM Busy Status. This bit is set when the internal I2CC state machine, rather than when the external bus, is busy with an ongoing transaction i.e. during transmit/receive of data bytes configured as per BLEN including START, RESTART, Address and STOP signal generation. In variants where the BLEN register is not available, the design implements a hardcoded BLEN value of '1'.
0h = The controller is idle.
1h = The controller is busy.

24.3.2.22 IFLS Register (Offset = 10Ch) [Reset = 00000022h]

IFLS is shown in Figure 24-42 and described in Table 24-43.

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I2CC Interrupt FIFO Level Select Register. The IFLS register is the interrupt FIFO level select register. Use this register to define the levels at which the TX, RX, and Receive timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level itself. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the receive FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Figure 24-42 IFLS Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RXCLRRXIFLSELTXCLRTXIFLSEL
R/W-0hR/W-2hR/W-0hR/W-2h
Table 24-43 IFLS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7RXCLRR/W0hRX FIFO Clear. Setting this bit will clear the RX FIFO contents.
0h = Disable FIFO clear
1h = Enable FIFO Clear
6-4RXIFLSELR/W2hRX FIFO Level Select for generating events (interrupt/DMA). Note: for undefined settings the default configuration is used.
1h = RX FIFO >= 1/4 full
2h = RX FIFO >= 1/2 full (default)
3h = RX FIFO >= 3/4 full
4h = Opposite of empty
5h = RX FIFO is full
6h = RX_FIFO >= (MAX_FIFO_LEN -1)
7h = RX_FIFO <= 1
3TXCLRR/W0hTX FIFO Clear. Setting this bit will clear the TX FIFO contents.
0h = Disable FIFO clear
1h = Enable FIFO Clear
2-0TXIFLSELR/W2hTX FIFO Level Select for generating events (interrupt/DMA). Note: for undefined settings the default configuration is used.
1h = TX FIFO <= 3/4 empty
2h = TX FIFO <= 1/2 empty (default)
3h = TX FIFO <= 1/4 empty
4h = Opposite of full
5h = TX FIFO is empty
6h = TX FIFO <= 1
7h = TX_FIFO >= (MAX_FIFO_LEN -1)

24.3.2.23 TPR Register (Offset = 110h) [Reset = 00000001h]

TPR is shown in Figure 24-43 and described in Table 24-44.

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I2CC Timer Period Register. This register programs the clock period of the SCL line. Transmission speeds of Standard mode (100kbps), Fast mode (400 kbps), or Fast mode plus (1Mbps) are supported.

Figure 24-43 TPR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTPR
R/W-0hR/W-1h
Table 24-44 TPR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR/W0h
6-0TPRR/W1hTimer Period. This field is used in the equation to configure SCL_PERIOD SCL_PERIOD = (1 + TPR ) x (SCL_LP + SCL_HP ) x INT_CLK_PRD Where: - SCL_PRD is the SCL line period (I2C clock). - TPR is the Timer Period register value (range of 1 to 127). - SCL_LP is the SCL Low period (fixed at 6). - SCL_HP is the SCL High period (fixed at 4). - CLK_PRD is the functional clock period in ns.
0h = Smallest value
7Fh = Highest possible value

24.3.2.24 GFCTL Register (Offset = 118h) [Reset = 00000000h]

GFCTL is shown in Figure 24-44 and described in Table 24-45.

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I2CC Glitch Filter Control Register. This register configures the glitch filter on the SCL and SDA lines.

Figure 24-44 GFCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDAGFEN
R/W-0hR/W-0h
76543210
RESERVEDDGFSEL
R/W-0hR/W-0h
Table 24-45 GFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8AGFENR/W0hAnalog Glitch Suppression Enable.
0h = Analog Glitch Filter disable
1h = Analog Glitch Filter enable
7-3RESERVEDR/W0h
2-0DGFSELR/W0hDigital Glitch Suppression Pulse Width. The digital glitch filter is only available on Basic I2CC instances. This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following glitch suppression values are in terms of I2Cclk cycles.
0h = Bypass
1h = 1 clock
2h = 2 clocks
3h = 3 clocks
4h = 4 clocks
5h = 8 clocks
6h = 16 clocks
7h = 31 clocks

24.3.2.25 BMON Register (Offset = 11Ch) [Reset = 00000003h]

BMON is shown in Figure 24-45 and described in Table 24-46.

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I2CC Bus Monitor Register. This register is used to read the current SCL and SDA signal logic levels.

Figure 24-45 BMON Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSDASCL
R-0hR-1hR-1h
Table 24-46 BMON Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1SDAR1hI2C SDA Status.
0h = The I2CSDA signal is low.
1h = The I2CSDA signal is high. Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations.
0SCLR1hI2C SCL Status.
0h = The I2CSCL signal is low.
1h = The I2CSCL signal is high. Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations.

24.3.2.26 TXDATA Register (Offset = 120h) [Reset = 00000000h]

TXDATA is shown in Figure 24-46 and described in Table 24-47.

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I2CC Transmit Data Register. This register is the transmit data register (the interface to the TX FIFO). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the TX FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the TX FIFO).

Figure 24-46 TXDATA Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
W-0hW-0h
Table 24-47 TXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDW0h
7-0DATAW0hTransmit Data. This byte contains the data to be transferred during the next transaction.
0h = Smallest value
FFh = Highest possible value

24.3.2.27 RXDATA Register (Offset = 124h) [Reset = 00000000h]

RXDATA is shown in Figure 24-47 and described in Table 24-48.

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I2CC Receive Data Register. This field contains the current byte being read in the RX FIFO If the FIFO is not present, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.

Figure 24-47 RXDATA Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR-0h
Table 24-48 RXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0DATAR0hReceived Data. This field contains the last received data.
0h = Smallest value
FFh = Highest possible value

24.3.2.28 PECSR Register (Offset = 128h) [Reset = 00000000h]

PECSR is shown in Figure 24-48 and described in Table 24-49.

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I2CC PEC Status Register. This status register can be used to read the current status of the packet error checking mechanism.

Figure 24-48 PECSR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDPECSTS_ERRORPECSTS_CHECK
R-0hR-0hR-0h
15141312111098
RESERVEDPECBYTECNT
R-0hR-0h
76543210
PECBYTECNT
R-0h
Table 24-49 PECSR Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17PECSTS_ERRORR0hPEC Status Error. This status bit indicates if a PEC check error occurred in the transaction that occurred before the last STOP. This bit is cleared automatically when the next STOP condition is observed on the bus.
0h = Indicates PEC check error did not occur in the transaction that occurred before the last STOP
1h = Indicates if a PEC check error occurred in the transaction that occurred before the last STOP
16PECSTS_CHECKR0hPEC Status Check. This status bit indicates if the PEC was checked in the transaction that occurred before the last STOP. This bit is cleared automatically when the next STOP condition is observed on the bus.
0h = Indicates PEC was not checked in the transaction that occurred before the last STOP
1h = Indicates if the PEC was checked in the transaction that occurred before the last STOP
15-9RESERVEDR0h
8-0PECBYTECNTR0hPEC Byte Count. This is the current PEC Byte Count of the Controller State Machine.
0h = Minimum Value
1FFh = Maximum Value

24.3.2.29 TA Register (Offset = 14Ch) [Reset = 00000000h]

TA is shown in Figure 24-49 and described in Table 24-50.

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I2CC Target Address Register. This register configures the target address, addressing mode, and direction (controller-transmit or controller-receive) of the next transaction.

Figure 24-49 TA Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
MODERESERVEDADDR
R/W-0hR/W-0hR/W-0h
76543210
ADDRDIR
R/W-0hR/W-0h
Table 24-50 TA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15MODER/W0hAddress Mode Select. This bit selects the addressing mode to be used. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.
0h = 7-bit addressing mode
1h = 10-bit addressing mode
14-11RESERVEDR/W0h
10-1ADDRR/W0hI2C Target Address. This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode, as selected by TA.MODE bit, the top 3 bits are don't care.
0h = Smallest value
3FFh = Highest possible value
0DIRR/W0hReceive/Transmit Direction. The DIR bit specifies if the next operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive
0h = in transmit mode.
1h = is in receive mode.

24.3.2.30 TIMEOUT_CNT Register (Offset = 150h) [Reset = 00020002h]

TIMEOUT_CNT is shown in Figure 24-50 and described in Table 24-51.

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I2CC Timeout Count Register. This register contains the upper 8 bits of a 12-bit current counter values for Timeout Counter A and Timeout Counter B. The lower four bits of the counter are not user visible and are always 0h.

Figure 24-50 TIMEOUT_CNT Register
313029282726252423222120191817161514131211109876543210
RESERVEDTCNTBRESERVEDTCNTA
R-0hR-2hR-0hR-2h
Table 24-51 TIMEOUT_CNT Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23-16TCNTBR2hTimeout Count B Current Count. This field contains the upper 8 bits of a 12-bit current counter for Timeout Counter B. This field is only available on Advanced I2CC instances.
0h = Smallest Value
FFh = Highest possible value
15-8RESERVEDR0h
7-0TCNTAR2hTimeout Count A Current Count. This field contains the upper 8 bits of a 12-bit current counter for Timeout Counter A.
0h = Smallest Value
FFh = Highest possible value

24.3.2.31 TIMEOUT_CTL Register (Offset = 154h) [Reset = 00020002h]

TIMEOUT_CTL is shown in Figure 24-51 and described in Table 24-52.

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I2CC Timeout Control Register. This register configures Timeout Counter A and Timeout Counter B.

Figure 24-51 TIMEOUT_CTL Register
3130292827262524
TCNTBENRESERVED
R/W-0hR/W-0h
2322212019181716
TCNTLB
R/W-2h
15141312111098
TCNTAENRESERVED
R/W-0hR/W-0h
76543210
TCNTLA
R/W-2h
Table 24-52 TIMEOUT_CTL Register Field Descriptions
BitFieldTypeResetDescription
31TCNTBENR/W0hTimeout Counter B Enable. This field is only available on Advanced I2CC instances.
0h = Disable Timeout Counter B
1h = Enable Timeout Counter B
30-24RESERVEDR/W0h
23-16TCNTLBR/W2hTimeout Count B Load. Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout Counter B. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns.
0h = Smallest possible value
FFh = Highest possible value
15TCNTAENR/W0hTimeout Counter A Enable.
0h = Disable Timeout Counter A
1h = Enable Timeout Counter A
14-8RESERVEDR/W0h
7-0TCNTLAR/W2hTimeout Counter A Load Value. Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout Counter A. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us.
0h = Smallest Value
FFh = Highest possible value

24.3.2.32 PECCTL Register (Offset = 158h) [Reset = 00000000h]

PECCTL is shown in Figure 24-52 and described in Table 24-53.

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I2CC PEC Control Register. This register configures the packet error checking (PEC) feature. This register is only available on Advanced I2CC instances.

Figure 24-52 PECCTL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDPECENRESERVEDPECCNT
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
PECCNT
R/W-0h
Table 24-53 PECCTL Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR/W0h
12PECENR/W0hPEC Enable. This bit enables the SMB Packet Error Checking (PEC). When enabled, the PEC is calculated on all bits except the START, STOP, and ACK/NACK. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a STOP or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.
0h = PEC is disabled
1h = PEC is enabled
11-9RESERVEDR/W0h
8-0PECCNTR/W0hPEC Count. When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the I2CC is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the TX FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode, the FIFO must be loaded with a dummy PEC byte. In receive mode, the PEC byte will be passed to the RX FIFO. In the a typical controller use case, the application would set PECEN=1 and PECCNT=SMB packet length (not including the Target Address byte, but including the PEC byte). The I2CC application would then configure the DMA to allow the packet to complete unassisted and write CTR to initiate the transaction. Note that when the byte count = PECCNT, the byte count is reset to 0 and multiple PEC calculations can automatically occur within a single I2C transaction. Note that any write to the PECCTL register will clear the current PEC byte count in the I2CC state machine.
0h = Minimum Value
1FFh = Maximum Value