SPRUJF2A March   2026  â€“ March 2026 AM13E23019

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 AM13E230x Architecture Overview
      1. 1.2.1 Bus, Power, Clock Organization
      2. 1.2.2 Device Block Diagram
      3. 1.2.3 Module Allocation and Instances
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 External Memory Region
      6. 1.3.6 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 FLNONMAINECC Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FLASH Registers
    6. 1.6 Memory Configuration
      1. 1.6.1 MEMCFG Registers
        1. 1.6.1.1 MEMCFG Base Address Table
        2. 1.6.1.2 MEM_CFG_REGS Registers
  4. 2 Peripheral Registers Memory Map
  5. 3  Power Management and Clock Unit (PMCU)
    1. 3.1 PMCU Overview
      1. 3.1.1 Power Domains
      2. 3.1.2 Operating Modes
        1. 3.1.2.1 RUN Mode
        2. 3.1.2.2 SLEEP Mode
        3. 3.1.2.3 STOP Mode
        4. 3.1.2.4 STANDBY Mode
        5. 3.1.2.5 SHUTDOWN Mode
        6. 3.1.2.6 Supported Functionality by Operating Mode
    2. 3.2 Quick Start Reference
      1. 3.2.1 Increasing MCLK Precision
      2. 3.2.2 Configuring MCLK for Maximum Speed
      3. 3.2.3 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
    3. 3.3 Power Management (PMU)
      1. 3.3.1 Power Supply
        1. 3.3.1.1 Main LDO
        2. 3.3.1.2 STOP LDO
        3. 3.3.1.3 VOSC LDO
        4. 3.3.1.4 HPLL LDO
      2. 3.3.2 Supply Supervisors
        1. 3.3.2.1 Power-on Reset (POR)
        2. 3.3.2.2 Brownout Reset (BOR)
        3. 3.3.2.3 POR and BOR Behavior During Supply Changes
      3. 3.3.3 Bandgap Reference
      4. 3.3.4 Analog Supplies
        1. 3.3.4.1 Analog Reference Circuits
      5. 3.3.5 Internal Temperature Sensor
      6. 3.3.6 Peripheral Enable
        1. 3.3.6.1 Automatic Peripheral Disable in Low Power Modes
    4. 3.4 Clock Module (CKM)
      1. 3.4.1 Clock Tree
      2. 3.4.2 Oscillators
        1. 3.4.2.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 3.4.2.2 Internal System Oscillator (SYSOSC)
          1. 3.4.2.2.1 SYSOSC Frequency
          2. 3.4.2.2.2 SYSOSC Frequency Correction Loop
            1. 3.4.2.2.2.1 SYSOSC FCL in Internal Resistor Mode
          3. 3.4.2.2.3 Disabling SYSOSC
        3. 3.4.2.3 System Phase-Locked Loop (SYSPLL)
          1. 3.4.2.3.1 Configuring SYSPLL Output Frequencies
          2. 3.4.2.3.2 Loading SYSPLL Lookup Parameters
          3. 3.4.2.3.3 SYSPLL Startup Time
        4. 3.4.2.4 External Crystal Oscillator (XTAL)
        5. 3.4.2.5 HFCLK_IN (Digital clock)
      3. 3.4.3 Clocks
        1. 3.4.3.1 MCLK (Main Clock) Tree
        2. 3.4.3.2 CPUCLK (Processor Clock)
        3. 3.4.3.3 ULPCLK (Low-Power Clock)
        4. 3.4.3.4 LFCLK (Low-Frequency Clock)
        5. 3.4.3.5 HFCLK (High-Frequency External Clock)
        6. 3.4.3.6 HSCLK (High Speed Clock)
        7. 3.4.3.7 CANCLK (CAN-FD Functional Clock)
        8. 3.4.3.8 External Clock Output (CLK_OUT)
      4. 3.4.4 Clock Monitors
        1. 3.4.4.1 MCLK Monitor
        2. 3.4.4.2 Startup Monitors
          1. 3.4.4.2.1 LFOSC Startup Monitor
          2. 3.4.4.2.2 HFCLK Startup Monitor
          3. 3.4.4.2.3 SYSPLL Startup Monitor
          4. 3.4.4.2.4 HSCLK Status
      5. 3.4.5 Frequency Clock Counter (FCC)
        1. 3.4.5.1 Using the FCC
        2. 3.4.5.2 FCC Frequency Computation and Accuracy
    5. 3.5 System Controller (SYSCTL)
      1. 3.5.1  Resets and Device Initialization
        1. 3.5.1.1 Reset Levels
          1. 3.5.1.1.1 Power-on Reset (POR) Reset Level
          2. 3.5.1.1.2 Brownout Reset (BOR) Reset Level
          3. 3.5.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 3.5.1.1.4 System Reset (SYSRST) Reset Level
          5. 3.5.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 3.5.1.2 Initial Conditions After Power-Up
        3. 3.5.1.3 NRST Pin
        4. 3.5.1.4 SWD/JTAG Pins
        5. 3.5.1.5 Generating Resets in Software
        6. 3.5.1.6 Reset Cause
        7. 3.5.1.7 Peripheral Reset Control
        8. 3.5.1.8 Boot Fail Handling
      2. 3.5.2  Operating Mode Selection
      3. 3.5.3  Asynchronous Fast Clock Requests
      4. 3.5.4  SRAM Write Protection
      5. 3.5.5  Flash Wait States
      6. 3.5.6  Flash Bank Address Swap
      7. 3.5.7  Shutdown Mode Handling
      8. 3.5.8  Configuration Lockout
      9. 3.5.9  System Status
      10. 3.5.10 Error Handling
      11. 3.5.11 SYSCTL Events
        1. 3.5.11.1 CPU Interrupt Events (CPU_INT)
        2. 3.5.11.2 CPU Nonmaskable Interrupt (NMI) Events
    6. 3.6 SYSCTL Registers
      1. 3.6.1 SYSCTL Base Address Table
      2. 3.6.2 SYSCTL_REGS Registers
  6. 4  Central Processing Unit (CPU)
    1. 4.1 Overview
    2. 4.2 CPU
      1. 4.2.1 Arm Cortex-M33 CPU
      2. 4.2.2 CPU Register File
      3. 4.2.3 Stack Behavior
      4. 4.2.4 Execution Modes and Privilege Levels
      5. 4.2.5 Address Space and Supported Data Sizes
    3. 4.3 Interrupts and Exceptions
      1. 4.3.1 Peripheral Interrupts (IRQs)
        1. 4.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 4.3.1.2 Wake Up Controller (WUC)
      2. 4.3.2 Interrupt and Exception Table
      3. 4.3.3 Processor Lockup Scenario
    4. 4.4 CPU Peripherals
      1. 4.4.1 System Control Block (SCB)
      2. 4.4.2 System Tick Timer (SysTick)
      3. 4.4.3 Memory Protection Unit (MPU)
      4. 4.4.4 Floating Point Unit (FPU)
      5. 4.4.5 Digital Signal Processing Extension
      6. 4.4.6 Custom Datapath Extension TMU
    5. 4.5 Read-Only Memory (ROM)
  7. 5 Trigonometric Math Unit (TMU)
    1. 5.1 Introduction
    2. 5.2 Features
    3. 5.3 Functional Operation
      1. 5.3.1 Supported TMU Instructions
  8. 6  TinyEngineâ„¢ NPU
    1. 6.1 Introduction
      1. 6.1.1 TinyEngineâ„¢ NPU Related Collateral
  9. 7 Secure ROM
    1. 7.1 ROM Overview
    2. 7.2 Memory Map
    3. 7.3 Boot Configuration Routine (BCR)
      1. 7.3.1 SWD Mass Erase and Factory Reset Commands
      2. 7.3.2 Fast Boot
    4. 7.4 Bootstrap Loader (BSL)
      1. 7.4.1 Application Version
      2. 7.4.2 GPIO Invoke
      3. 7.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 7.5 Lifecycle Management
      1. 7.5.1 Device Sub-Type
      2. 7.5.2 Lifecycle Transitions
    6. 7.6 Boot and Startup Sequence
      1. 7.6.1 Secure Boot
      2. 7.6.2 Customer Secure Code (CSC)
  10. 8 Global Security Controller (GSC)
    1. 8.1 GSC Introduction
      1. 8.1.1 GSC Features
    2. 8.2 GSC Operation
      1. 8.2.1 Functional Block Diagram
      2. 8.2.2 Peripheral Protection Controller
        1. 8.2.2.1 DMA Security
        2. 8.2.2.2 TinyEngine NPU Security
      3. 8.2.3 SRAM Protection Controller
        1. 8.2.3.1 SRAM Page Use Model
      4. 8.2.4 Flash Protection Controller
        1. 8.2.4.1 Flash Bank Security Implementation
        2. 8.2.4.2 Flash Hide Protection
      5. 8.2.5 Strict Privilege Context Protection
      6. 8.2.6 GSC Configuration Lock
    3. 8.3 GSC Registers
      1. 8.3.1 GSC Base Address Table
      2. 8.3.2 GSC_LITE_REGS Registers
  11. 9 Direct Memory Access (DMA)
    1. 9.1 DMA Overview
    2. 9.2 DMA Operation
      1. 9.2.1  Channel Types
      2. 9.2.2  Channel Priorities
      3. 9.2.3  Initiating DMA Transfers
        1. 9.2.3.1 DMA - DMA Trigger Source Options
        2. 9.2.3.2 Cascading DMA Channels
      4. 9.2.4  Transfer Modes
        1. 9.2.4.1 Single Transfer
        2. 9.2.4.2 Block Transfer
        3. 9.2.4.3 Repeated Single Transfer
        4. 9.2.4.4 Repeated Block Transfer
        5. 9.2.4.5 Burst Block Mode
      5. 9.2.5  Pausing DMA Transfers
      6. 9.2.6  DMA Auto-enable
      7. 9.2.7  Addressing Modes
        1. 9.2.7.1 Basic Addressing Modes
        2. 9.2.7.2 Stride Mode
        3. 9.2.7.3 Extended Modes
          1. 9.2.7.3.1 Fill Mode
          2. 9.2.7.3.2 Table Mode
          3. 9.2.7.3.3 Gather Mode
      8. 9.2.8  DMA Controller Interrupts
        1. 9.2.8.1 Using DMA with System Interrupts
      9. 9.2.9  DMA Trigger Event Status
      10. 9.2.10 DMA Operating Mode Support
        1. 9.2.10.1 Transfer in RUN Mode
        2. 9.2.10.2 Transfer in SLEEP Mode
        3. 9.2.10.3 Transfer in STOP Mode
        4. 9.2.10.4 Transfers in STANDBY Mode
      11. 9.2.11 DMA Address and Data Errors
    3. 9.3 DMA Registers
      1. 9.3.1 DMA Base Address Table
      2. 9.3.2 DMA_REGS Registers
  12. 10Flash Module
    1. 10.1 Flash (NVM)
      1. 10.1.1 Introduction to Flash and OTP Memory
        1. 10.1.1.1 Flash Features
        2. 10.1.1.2 System Components
        3. 10.1.1.3 Terminology
      2. 10.1.2 Flash Memory Bank Organization
        1. 10.1.2.1 Banks
        2. 10.1.2.2 Flash Memory Regions
        3. 10.1.2.3 Addressing
          1. 10.1.2.3.1 Flash Memory Map
        4. 10.1.2.4 Memory Organization Examples
      3. 10.1.3 Flash Controller
        1. 10.1.3.1 Overview of Flash Controller Commands
        2. 10.1.3.2 Command Diagnostics
          1. 10.1.3.2.1 Command Status
          2. 10.1.3.2.2 Address Translation
          3. 10.1.3.2.3 Pulse Counts
        3. 10.1.3.3 NOOP Command
        4. 10.1.3.4 PROGRAM Command
          1. 10.1.3.4.1 Program Bit Masking Behavior
          2. 10.1.3.4.2 Target Data Alignment
          3. 10.1.3.4.3 Executing a PROGRAM Operation
        5. 10.1.3.5 ERASE Command
          1. 10.1.3.5.1 Erase Sector Masking Behavior
          2. 10.1.3.5.2 Executing an ERASE Operation
        6. 10.1.3.6 READVERIFY Command
          1. 10.1.3.6.1 Executing a READVERIFY Operation
        7. 10.1.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
        8. 10.1.3.8 FLASHCTL Events
      4. 10.1.4 Write Protection
        1. 10.1.4.1 Write Protection Resolution
        2. 10.1.4.2 Static Write Protection
        3. 10.1.4.3 Dynamic Write Protection
          1. 10.1.4.3.1 Configuring Protection for the MAIN Region
          2. 10.1.4.3.2 Configuring Protection for the NONMAIN Region
      5. 10.1.5 Flash Read Interface
        1. 10.1.5.1 Bank Modes and Swapping
        2. 10.1.5.2 Flash Wait States
        3. 10.1.5.3 Buffer and Cache Mechanisms
        4. 10.1.5.4 Flash Read Arbitration
        5. 10.1.5.5 Error Correction Code (ECC) Protection
        6. 10.1.5.6 Procedure to Change Flash Read Interface Registers
      6. 10.1.6 Read Interface
        1. 10.1.6.1 Bank Address Swapping
        2. 10.1.6.2 ECC Error Handling
          1. 10.1.6.2.1 Single bit (correctable) errors
          2. 10.1.6.2.2 Dual bit (uncorrectable) errors
    2. 10.2 FLASH Registers
      1. 10.2.1 FLASH Base Address Table
      2. 10.2.2 FLASH_CTRL_REGS Registers
      3. 10.2.3 NVMNW_REGS Registers
  13. 11Error Aggregator Module (EAM)
    1. 11.1 EAM
      1. 11.1.1 EAM Introduction
      2. 11.1.2 EAM Operation
        1. 11.1.2.1 Security Error Aggregator
        2. 11.1.2.2 Safety Error Aggregator
        3. 11.1.2.3 SYSMEM Access Error
    2. 11.2 EAM Registers
      1. 11.2.1 EAM Base Address Table
      2. 11.2.2 EAM_REGS Registers
  14. 12Events
    1. 12.1 Events Overview
      1. 12.1.1 Event Publisher
        1. 12.1.1.1 Standard Event Registers
      2. 12.1.2 Event Subscriber
      3. 12.1.3 Event Routing Map
      4. 12.1.4 Event Fabric Routing
        1. 12.1.4.1 CPU Interrupt Event Route (CPU_INT)
        2. 12.1.4.2 DMA Trigger Event Route (DMA_TRIG)
        3. 12.1.4.3 ADC Start Of Conversion Event Route (ADC_SOC)
      5. 12.1.5 Event Propagation Latency
  15. 13IOMUX
    1. 13.1 IOMUX
      1. 13.1.1 IOMUX Overview
        1. 13.1.1.1 IO Types and Analog Sharing
      2. 13.1.2 IOMUX Operation
        1. 13.1.2.1 Peripheral Function (PF) Assignment
        2. 13.1.2.2 Logic High to Hi-Z Conversion
        3. 13.1.2.3 Logic Inversion
        4. 13.1.2.4 SHUTDOWN Mode Wakeup Logic
        5. 13.1.2.5 Pullup/Pulldown Resistors
        6. 13.1.2.6 Drive Strength Control
    2. 13.2 IOMUX Registers
      1. 13.2.1 IOMUX Base Address Table
      2. 13.2.2 IOMUX_REGS Registers
  16. 14General Purpose Input/Output (GPIO)
    1. 14.1 General-Purpose Input/Output (GPIO)
      1. 14.1.1 GPIO Overview
      2. 14.1.2 GPIO Operation
        1. 14.1.2.1 GPIO Ports
        2. 14.1.2.2 GPIO Read/Write Interface
        3. 14.1.2.3 GPIO Input Glitch Filtering and Synchronization
        4. 14.1.2.4 GPIO Fast Wake
        5. 14.1.2.5 GPIO DMA Interface
        6. 14.1.2.6 Event Publishers
    2. 14.2 GPIO Registers
      1. 14.2.1 GPIO Base Address Table
      2. 14.2.2 GPIO_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 Features
      2. 15.1.2 ADC Related Collateral
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 ADC Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
        1. 15.2.4.1 Expected Conversion Results
        2. 15.2.4.2 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 ADC Sequencer
      2. 15.3.2 SOC Configuration
      3. 15.3.3 Trigger Operation
        1. 15.3.3.1 Global Software Trigger
      4. 15.3.4 ADC Acquisition (Sample and Hold) Window
      5. 15.3.5 Sample Capacitor Reset
      6. 15.3.6 ADC Input Models
      7. 15.3.7 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion fromMCPWM Trigger
      2. 15.4.2 Oversampled Conversion from MCPWM Trigger
      3. 15.4.3 Software Triggering of SOCs
    5. 15.5  EOC and Interrupt Operation
      1. 15.5.1 Interrupt Overflow
      2. 15.5.2 Continue to Interrupt Mode
      3. 15.5.3 Early Interrupt Configuration Mode
    6. 15.6  Post-Processing Blocks
      1. 15.6.1 PPB Offset Correction
      2. 15.6.2 PPB Error Calculation
      3. 15.6.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.6.4 PPB Sample Delay Capture
      5. 15.6.5 PPB Oversampling
        1. 15.6.5.1 Accumulation and Average Functions
        2. 15.6.5.2 Outlier Rejection
    7. 15.7  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.7.1 Open Short Detection Implementation
      2. 15.7.2 Detecting an Open Input Pin
      3. 15.7.3 Detecting a Shorted Input Pin
    8. 15.8  Power-Up Sequence
    9. 15.9  ADC Calibration
    10. 15.10 ADC Timings
      1. 15.10.1 ADC Timing Diagrams
      2. 15.10.2 Post-Processing Block Timings
    11. 15.11 Additional Information
      1. 15.11.1  Ensuring Synchronous Operation
        1. 15.11.1.1 Basic Synchronous Operation
        2. 15.11.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.11.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.11.1.4 Non-overlapping Conversions
      2. 15.11.2  Choosing an Acquisition Window Duration
      3. 15.11.3  Achieving Simultaneous Sampling
      4. 15.11.4  Result Register Mapping
      5. 15.11.5  Internal Temperature Sensor
      6. 15.11.6  Designing an External Reference Circuit
      7. 15.11.7  ADC-DAC Loopback Testing
      8. 15.11.8  Internal Test Mode
      9. 15.11.9  ADC Gain and Offset Calibration
      10. 15.11.10 ADC Zero Offset Calibration
    12. 15.12 ADC Registers
      1. 15.12.1 ADC Base Address Table
      2. 15.12.2 ADC_LITE_REGS Registers
      3. 15.12.3 ADC_LITE_RESULT_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 CMPSS Related Collateral
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Digital Filter
      1. 16.4.1 Filter Initialization Sequence
    5. 16.5 Using the CMPSS
      1. 16.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 16.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.5.3 Calibrating the CMPSS
      4. 16.5.4 Enabling and Disabling the CMPSS Clock
    6. 16.6 CMPSS DAC Output
    7. 16.7 CMPSS Registers
      1. 16.7.1 CMPSS Base Address Table
      2. 16.7.2 CMPSS_LITE_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
        1. 17.1.2.1 PGA Mux Selection Options
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 PGA Registers
      1. 17.12.1 PGA Base Address Table
      2. 17.12.2 PGA_REGS Registers
  20. 18Multi-Channel Pulse Width Modulator (MCPWM)
    1. 18.1  Introduction
      1. 18.1.1 PWM Related Collateral
      2. 18.1.2 MCPWM Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  MCPWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 MCPWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 18.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 18.4.6 Global Load
        1. 18.4.6.1 One-Shot Load Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-Band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  Trip-Zone (TZ) Submodule
      1. 18.8.1 Purpose of the Trip-Zone Submodule
      2. 18.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.8.2.1 Trip-Zone Configurations
      3. 18.8.3 Generating Trip Event Interrupts
    9. 18.9  Event-Trigger (ET) Submodule
      1. 18.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 18.10 PWM Crossbar (X-BAR)
    11. 18.11 MCPWM Registers
      1. 18.11.1 MCPWM Base Address Table
      2. 18.11.2 MCPWM_6CH_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1 Event Prescaler
      2. 19.5.2 Edge Polarity Select and Qualifier
      3. 19.5.3 Continuous/One-Shot Control
      4. 19.5.4 32-Bit Counter and Phase Control
      5. 19.5.5 CAP1-CAP4 Registers
      6. 19.5.6 eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7 Interrupt Control
      8. 19.5.8 Shadow Load and Lockout Control
      9. 19.5.9 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 ECAP Registers
      1. 19.8.1 ECAP Base Address Table
      2. 19.8.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 PWM Frequency Measurement using EQEP via XBAR connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Crossbar (X-BAR)
    1. 21.1 INPUTXBAR
    2. 21.2 MCPWM and GPIO Output X-BAR
      1. 21.2.1 MCPWM X-BAR
        1. 21.2.1.1 MCPWM X-BAR Architecture
      2. 21.2.2 GPIO Output X-BAR
        1. 21.2.2.1 GPIO Output X-BAR Architecture
      3. 21.2.3 X-BAR Flags
    3. 21.3 XBAR Registers
      1. 21.3.1 XBAR Base Address Table
      2. 21.3.2 INPUT_XBAR_REGS Registers
      3. 21.3.3 EPWM_XBAR_REGS Registers
      4. 21.3.4 OUTPUTXBAR_REGS Registers
      5. 21.3.5 SYNC_SOC_REGS Registers
      6. 21.3.6 OUTPUTXBAR_FLAG_REGS Registers
      7. 21.3.7 INPUT_FLAG_XBAR_REGS Registers
  24. 22Unified Communication Peripheral (UNICOMM)
    1. 22.1 Overview
      1. 22.1.1 Block Diagram
    2. 22.2 Unicomm Architecture
      1. 22.2.1 Scalable Peripheral Group (SPG) Configurations
        1. 22.2.1.1 Loopback Operation
        2. 22.2.1.2 I2C Pairings
      2. 22.2.2 FIFO Operation
        1. 22.2.2.1 Receive FIFO Levels
        2. 22.2.2.2 Transmitter FIFO Levels
        3. 22.2.2.3 Clearing FIFO Contents
        4. 22.2.2.4 FIFO Status Flags
      3. 22.2.3 Interrupts
        1. 22.2.3.1 Receive Interrupt Sequence
        2. 22.2.3.2 Transmit Interrupt Sequence
      4. 22.2.4 DMA Operation
    3. 22.3 High-Level Initialization
    4. 22.4 Enables & Resets
    5. 22.5 Suspending Communication
    6. 22.6 UNICOMM Registers
      1. 22.6.1 UNICOMM Base Address Table
      2. 22.6.2 UNICOMM_REGS Registers
    7. 22.7 SPG Registers
      1. 22.7.1 SPG Base Address Table
      2. 22.7.2 SPGSS_REGS Registers
  25. 23Universal Asychronous Receiver/Transmitter (UART)
    1. 23.1 Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
    2. 23.2 Peripheral Functional Description
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture and Protocol
        1. 23.2.2.1 Signal Descriptions
        2. 23.2.2.2 Transmit and Receive Logic
        3. 23.2.2.3 Bit Sampling
        4. 23.2.2.4 Baud Rate Generation
        5. 23.2.2.5 Data Transmission
        6. 23.2.2.6 Error and Status
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Internal Loopback Operation
      3. 23.2.3 Additional Protocol and Feature Support
        1. 23.2.3.1 Local Interconnect Network (LIN) Support
          1. 23.2.3.1.1 LIN Commander Transmit
          2. 23.2.3.1.2 LIN Responder Receive
          3. 23.2.3.1.3 LIN Wakeup
        2. 23.2.3.2 Flow Control
        3. 23.2.3.3 RS485 Support
        4. 23.2.3.4 Idle-Line Multiprocessor
        5. 23.2.3.5 9-Bit UART Mode
        6. 23.2.3.6 ISO7816 Smart Card Support
        7. 23.2.3.7 Address Detection
      4. 23.2.4 Initialization
      5. 23.2.5 Interrupt and Events Support
        1. 23.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.5.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      6. 23.2.6 Emulation Modes
    3. 23.3 UNICOMM-UART Registers
      1. 23.3.1 UNICOMM-UART Base Address Table
      2. 23.3.2 UNICOMMUART_REGS Registers
  26. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
    2. 24.2 Peripheral Functional Description
      1. 24.2.1 Clock Control
        1. 24.2.1.1 Clock Select and I2C Speed
        2. 24.2.1.2 Clock Startup
      2. 24.2.2 Signal Descriptions
      3. 24.2.3 General Architecture
        1. 24.2.3.1  I2C Bus Functional Overview
        2. 24.2.3.2  START and STOP Conditions
        3. 24.2.3.3  7-Bit Address Format
        4. 24.2.3.4  10-Bit Address Format
        5. 24.2.3.5  General Call
        6. 24.2.3.6  Dual Address
        7. 24.2.3.7  Acknowledge
        8. 24.2.3.8  Repeated Start
        9. 24.2.3.9  Clock Low Timeout
        10. 24.2.3.10 Clock Stretching
        11. 24.2.3.11 Arbitration
        12. 24.2.3.12 Multiple Controller Mode
        13. 24.2.3.13 Glitch Suppression
        14. 24.2.3.14 Burst Mode
        15. 24.2.3.15 DMA Operation
        16. 24.2.3.16 SMBus 3.0 Support
          1. 24.2.3.16.1 Quick Command
          2. 24.2.3.16.2 Acknowledge Control
          3. 24.2.3.16.3 Clock Low Timeout Detection
          4. 24.2.3.16.4 Clock High Timeout Detection
          5. 24.2.3.16.5 Cumulative clock low extended timeout for controller and target
          6. 24.2.3.16.6 Packet Error Checking (PEC)
          7. 24.2.3.16.7 Host Notify Protocol
          8. 24.2.3.16.8 Alert Response Protocol
          9. 24.2.3.16.9 Address Resolution Protocol
      4. 24.2.4 Protocol Descriptions
        1. 24.2.4.1 I2C Controller Mode
          1. 24.2.4.1.1 I2C Controller Initialization
          2. 24.2.4.1.2 I2C Controller Status
          3. 24.2.4.1.3 I2C Controller Receive Mode
          4. 24.2.4.1.4 I2C Controller Transmitter Mode
          5. 24.2.4.1.5 Controller Configuration
        2. 24.2.4.2 I2C Target Mode
          1. 24.2.4.2.1 I2C Target Initialization
          2. 24.2.4.2.2 I2C Target Status
          3. 24.2.4.2.3 I2C Target Receiver Mode
          4. 24.2.4.2.4 I2C Target Transmitter Mode
      5. 24.2.5 Reset Considerations
      6. 24.2.6 Interrupt and Events Support
        1. 24.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 24.2.7 Emulation Modes
    3. 24.3 UNICOMM-I2C Registers
      1. 24.3.1 UNICOMM-I2C Base Address Table
      2. 24.3.2 UNICOMMI2CC_REGS Registers
      3. 24.3.3 UNICOMMI2CT_REGS Registers
  27. 25Serial Peripheral Interface (SPI)
    1. 25.1 Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 Peripheral Functional Description
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed Data Sampling
        4. 25.2.2.4 Clock Generation
        5. 25.2.2.5 SPI FIFO Operation
        6. 25.2.2.6 DMA Operation
      3. 25.2.3 Internal Loopback Operation
      4. 25.2.4 Protocol Descriptions
        1. 25.2.4.1 Motorola SPI Frame Format
        2. 25.2.4.2 Texas Instruments Synchronous Serial Frame Format
      5. 25.2.5 Status Flags
      6. 25.2.6 Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMM-SPI Registers
      1. 25.3.1 UNICOMM-SPI Base Address Table
      2. 25.3.2 UNICOMMSPI_REGS Registers
  28. 26Modular Controller Area Network (MCAN)
    1. 26.1 CAN-FD
      1. 26.1.1 MCAN Overview
        1. 26.1.1.1 MCAN Features
      2. 26.1.2 MCAN Environment
      3. 26.1.3 CAN Network Basics
      4. 26.1.4 MCAN Functional Description
        1. 26.1.4.1  Clock Setup
        2. 26.1.4.2  Module Clocking Requirements
        3. 26.1.4.3  Interrupt Requests
        4. 26.1.4.4  Operating Modes
          1. 26.1.4.4.1 Normal Operation
          2. 26.1.4.4.2 CAN Classic
          3. 26.1.4.4.3 CAN FD Operation
        5. 26.1.4.5  Software Initialization
        6. 26.1.4.6  Transmitter Delay Compensation
          1. 26.1.4.6.1 Description
          2. 26.1.4.6.2 Transmitter Delay Compensation Measurement
        7. 26.1.4.7  Restricted Operation Mode
        8. 26.1.4.8  Bus Monitoring Mode
        9. 26.1.4.9  Disabled Automatic Retransmission (DAR) Mode
          1. 26.1.4.9.1 Frame Transmission in DAR Mode
        10. 26.1.4.10 Clock Stop Mode
          1. 26.1.4.10.1 Suspend Mode
          2. 26.1.4.10.2 Wakeup Request
        11. 26.1.4.11 Test Modes
          1. 26.1.4.11.1 External Loop Back Mode
          2. 26.1.4.11.2 Internal Loop Back Mode
        12. 26.1.4.12 Timestamp Generation
          1. 26.1.4.12.1 External Timestamp Counter
        13. 26.1.4.13 Timeout Counter
        14. 26.1.4.14 Safety
          1. 26.1.4.14.1 MCAN ECC Wrapper
          2. 26.1.4.14.2 MCAN ECC Aggregator
            1. 26.1.4.14.2.1 MCAN ECC Aggregator Overview
            2. 26.1.4.14.2.2 MCAN ECC Aggregator Registers
          3. 26.1.4.14.3 Reads to ECC Control and Status Registers
          4. 26.1.4.14.4 ECC Interrupts
        15. 26.1.4.15 Tx Handling
          1. 26.1.4.15.1 Transmit Pause
          2. 26.1.4.15.2 Dedicated Tx Buffers
          3. 26.1.4.15.3 Tx FIFO
          4. 26.1.4.15.4 Tx Queue
          5. 26.1.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.1.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.1.4.15.7 Transmit Cancellation
          8. 26.1.4.15.8 Tx Event Handling
          9. 26.1.4.15.9 FIFO Acknowledge Handling
        16. 26.1.4.16 Rx Handling
          1. 26.1.4.16.1 Acceptance Filtering
            1. 26.1.4.16.1.1 Range Filter
            2. 26.1.4.16.1.2 Filter for Specific IDs
            3. 26.1.4.16.1.3 Classic Bit Mask Filter
            4. 26.1.4.16.1.4 Standard Message ID Filtering
            5. 26.1.4.16.1.5 Extended Message ID Filtering
        17. 26.1.4.17 Rx FIFOs
          1. 26.1.4.17.1 Rx FIFO Blocking Mode
          2. 26.1.4.17.2 Rx FIFO Overwrite Mode
        18. 26.1.4.18 Dedicated Rx Buffers
          1. 26.1.4.18.1 Rx Buffer Handling
        19. 26.1.4.19 Message RAM
          1. 26.1.4.19.1 Message RAM Configuration
          2. 26.1.4.19.2 Rx Buffer and FIFO Element
          3. 26.1.4.19.3 Tx Buffer Element
          4. 26.1.4.19.4 Tx Event FIFO Element
          5. 26.1.4.19.5 Standard Message ID Filter Element
          6. 26.1.4.19.6 Extended Message ID Filter Element
      5. 26.1.5 MCAN Integration
      6. 26.1.6 Interrupt and Event Support
        1. 26.1.6.1 CPU Interrupt Event Publisher (CPU_INT)
    2. 26.2 MCAN Registers
      1. 26.2.1 MCAN Base Address Table
      2. 26.2.2 MCAN_REGS Registers
  29. 27External Peripheral Interface (EPI)
    1. 27.1 External Peripheral Interface (EPI)
      1. 27.1.1 Introduction
      2. 27.1.2 EPI Block Diagram
      3. 27.1.3 Functional Description
        1. 27.1.3.1 Controller Access to EPI
        2. 27.1.3.2 Nonblocking Reads
        3. 27.1.3.3 DMA Operation
      4. 27.1.4 Initialization and Configuration
        1. 27.1.4.1 EPI Interface Options
        2. 27.1.4.2 SDRAM Mode
          1. 27.1.4.2.1 External Signal Connections
          2. 27.1.4.2.2 Refresh Configuration
          3. 27.1.4.2.3 Bus Interface Speed
          4. 27.1.4.2.4 Nonblocking Read Cycle
          5. 27.1.4.2.5 Normal Read Cycle
          6. 27.1.4.2.6 Write Cycle
        3. 27.1.4.3 Host Bus Mode
          1. 27.1.4.3.1 Control Pins
          2. 27.1.4.3.2 PSRAM Support
          3. 27.1.4.3.3 Host Bus 16-Bit Muxed Interface
          4. 27.1.4.3.4 Speed of Transactions
          5. 27.1.4.3.5 Sub-Modes of Host Bus 8 and 16
          6. 27.1.4.3.6 Bus Operation
        4. 27.1.4.4 General-Purpose Mode
          1. 27.1.4.4.1 Bus Operation
            1. 27.1.4.4.1.1 FRAME Signal Operation
            2. 27.1.4.4.1.2 EPI Clock Operation
    2. 27.2 EPI Registers
      1. 27.2.1 EPI Base Address Table
      2. 27.2.2 EPI_REGS_GPCFG Registers
      3. 27.2.3 EPI_REGS_SDRAMCFG Registers
      4. 27.2.4 EPI_REGS_HB8CFG Registers
      5. 27.2.5 EPI_REGS_HB16CFG Registers
  30. 28Cyclic Redundancy Check (CRC)
    1. 28.1 CRC
      1. 28.1.1 CRC Overview
        1. 28.1.1.1 CRC16-CCITT
        2. 28.1.1.2 CRC32-ISO3309
      2. 28.1.2 CRC Operation
        1. 28.1.2.1 CRC Generator Implementation
        2. 28.1.2.2 Configuration
          1. 28.1.2.2.1 Polynomial Selection
          2. 28.1.2.2.2 Bit Order
          3. 28.1.2.2.3 Byte Swap
          4. 28.1.2.2.4 Byte Order
          5. 28.1.2.2.5 CRC C Library Compatibility
    2. 28.2 CRC Registers
      1. 28.2.1 CRC Base Address Table
      2. 28.2.2 CRCP_REGS Registers
  31. 29Advanced Encryption Standard (AES) Accelerator
    1. 29.1 AESADV
      1. 29.1.1 AES Overview
        1. 29.1.1.1 AESADV Performance
      2. 29.1.2 AESADV Operation
        1. 29.1.2.1 Loading the Key
        2. 29.1.2.2 Writing Input Data
        3. 29.1.2.3 Reading Output Data
        4. 29.1.2.4 Operation Descriptions
          1. 29.1.2.4.1 Single Block Operation
          2. 29.1.2.4.2 Electronic Codebook (ECB) Mode
            1. 29.1.2.4.2.1 ECB Encryption
            2. 29.1.2.4.2.2 ECB Decryption
          3. 29.1.2.4.3 Cipher Block Chaining (CBC) Mode
            1. 29.1.2.4.3.1 CBC Encryption
            2. 29.1.2.4.3.2 CBC Decryption
          4. 29.1.2.4.4 Output Feedback (OFB) Mode
            1. 29.1.2.4.4.1 OFB Encryption
            2. 29.1.2.4.4.2 OFB Decryption
          5. 29.1.2.4.5 Cipher Feedback (CFB) Mode
            1. 29.1.2.4.5.1 CFB Encryption
            2. 29.1.2.4.5.2 CFB Decryption
          6. 29.1.2.4.6 Counter (CTR) Mode
            1. 29.1.2.4.6.1 CTR Encryption
            2. 29.1.2.4.6.2 CTR Decryption
          7. 29.1.2.4.7 Galois Counter (GCM) Mode
            1. 29.1.2.4.7.1 GHASH Operation
            2. 29.1.2.4.7.2 GCM Operating Modes
              1. 29.1.2.4.7.2.1 Autonomous GCM Operation
                1. 29.1.2.4.7.2.1.1 GMAC
              2. 29.1.2.4.7.2.2 GCM With Pre-Calculations
              3. 29.1.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
          8. 29.1.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
            1. 29.1.2.4.8.1 CCM Operation
        5. 29.1.2.5 AES Events
          1. 29.1.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
          2. 29.1.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
          3. 29.1.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    2. 29.2 AES Registers
      1. 29.2.1 AES Base Address Table
      2. 29.2.2 AES_REGS Registers
  32. 30Keystore
    1. 30.1 Keystore
      1. 30.1.1 Overview
      2. 30.1.2 Detailed Description
    2. 30.2 KEYSTORE Registers
      1. 30.2.1 KEYSTORE Base Address Table
      2. 30.2.2 KEYSTORE_REGS Registers
  33. 31Timers
    1. 31.1 Timers (TIMx)
      1. 31.1.1 TIMx Overview
        1. 31.1.1.1 TIMx Instance Configuration
        2. 31.1.1.2 TIMG Features
        3. 31.1.1.3 Functional Block Diagram
      2. 31.1.2 TIMx Operation
        1. 31.1.2.1 Timer Counter
          1. 31.1.2.1.1 Clock Source Select and Prescaler
            1. 31.1.2.1.1.1 Internal Clock and Prescaler
            2. 31.1.2.1.1.2 External Signal Trigger
        2. 31.1.2.2 Counting Mode Control
          1. 31.1.2.2.1 One-shot and Periodic Modes
          2. 31.1.2.2.2 Down Counting Mode
          3. 31.1.2.2.3 Up/Down Counting Mode
          4. 31.1.2.2.4 Up Counting Mode
        3. 31.1.2.3 Capture/Compare Module
          1. 31.1.2.3.1 Capture Mode
            1. 31.1.2.3.1.1 Input Selection, Counter Conditions, and Inversion
              1. 31.1.2.3.1.1.1 CCP Input Edge Synchronization
              2. 31.1.2.3.1.1.2 Input Selection
              3. 31.1.2.3.1.1.3 CCP Input Filtering
              4. 31.1.2.3.1.1.4 CCP Input Pulse Conditions
              5. 31.1.2.3.1.1.5 Counter Control Operation
            2. 31.1.2.3.1.2 Capture Mode Use Cases
              1. 31.1.2.3.1.2.1 Edge Time Capture
              2. 31.1.2.3.1.2.2 Period Capture
              3. 31.1.2.3.1.2.3 Pulse Width Capture
              4. 31.1.2.3.1.2.4 Combined Pulse Width and Period Time
          2. 31.1.2.3.2 Compare Mode
            1. 31.1.2.3.2.1 Edge Count
        4. 31.1.2.4 Shadow Load and Shadow Compare
          1. 31.1.2.4.1 Shadow Load (TIMG4-7)
          2. 31.1.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13)
        5. 31.1.2.5 Output Generator
          1. 31.1.2.5.1 Configuration
          2. 31.1.2.5.2 Use Cases
            1. 31.1.2.5.2.1 Edge-Aligned PWM
            2. 31.1.2.5.2.2 Center-Aligned PWM
          3. 31.1.2.5.3 Forced Output
        6. 31.1.2.6 Synchronization With Cross Trigger
          1. 31.1.2.6.1 Main Timer Cross Trigger Configuration
          2. 31.1.2.6.2 Secondary Timer Cross Trigger Configuration
        7. 31.1.2.7 Low Power Operation
        8. 31.1.2.8 Interrupt and Event Support
          1. 31.1.2.8.1 CPU Interrupt Event Publisher (CPU_INT)
          2. 31.1.2.8.2 GEN_EVENT0 and GEN_EVENT1
        9. 31.1.2.9 944
    2. 31.2 TIMERS Registers
      1. 31.2.1 TIMERS Base Address Table
      2. 31.2.2 TIMG4_REGS Registers
      3. 31.2.3 TIMG12_REGS Registers
  34. 32Windowed Watchdog Timer (WWDT)
    1. 32.1 Window Watchdog Timer (WWDT)
      1. 32.1.1 WWDT Overview
        1. 32.1.1.1 Watchdog Mode
        2. 32.1.1.2 Interval Timer Mode
      2. 32.1.2 WWDT Operation
        1. 32.1.2.1 Mode Selection
        2. 32.1.2.2 Clock Configuration
        3. 32.1.2.3 Low-Power Mode Behavior
        4. 32.1.2.4 Debug Behavior
        5. 32.1.2.5 WWDT Events
          1. 32.1.2.5.1 CPU Interrupt Event (CPU_INT)
    2. 32.2 WWDT Registers
      1. 32.2.1 WWDT Base Address Table
      2. 32.2.2 WWDT_REGS Registers
  35. 33Debug Subsystem (DEBUGSS)
    1. 33.1 Debug Subsystem
      1. 33.1.1 DEBUGSS Overview
        1. 33.1.1.1 Debug Interconnect
        2. 33.1.1.2 Physical Interfaces
          1. 33.1.1.2.1 JTAG Debug Port (JTAG-DP)
          2. 33.1.1.2.2 Serial Wire Debug (SWD) Debug Port (SW-DP)
          3. 33.1.1.2.3 Serial Wire Debug and JTAG Debug Port (SWJ-DP)
          4. 33.1.1.2.4 Debug Wake Up and Interrupts
        3. 33.1.1.3 Debug Access Ports
      2. 33.1.2 DEBUGSS Operation
        1. 33.1.2.1 Debug Features
          1. 33.1.2.1.1 Processor Debug
            1. 33.1.2.1.1.1 Breakpoint Unit (BPU)
            2. 33.1.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
            3. 33.1.2.1.1.3 Processor Trace (MTB)
            4. 33.1.2.1.1.4 External Trace (ETM)
          2. 33.1.2.1.2 Peripheral Debug
          3. 33.1.2.1.3 EnergyTrace Technology
        2. 33.1.2.2 Behavior in Low Power Modes
        3. 33.1.2.3 Restricting Debug Access
        4. 33.1.2.4 Mailbox (DSSM)
          1. 33.1.2.4.1 DSSM Events
            1. 33.1.2.4.1.1 CPU Interrupt Event (CPU_INT)
          2. 33.1.2.4.2 DSSM Commands
    2. 33.2 DEBUGSS Registers
      1. 33.2.1 DEBUGSS Base Address Table
      2. 33.2.2 DEBUGSS_REGS Registers
  36. 34Revision History

27.2.4 EPI_REGS_HB8CFG Registers

Table 27-46 lists the memory-mapped registers for the EPI_REGS_HB8CFG registers. All register offset addresses not listed in Table 27-46 should be considered as reserved locations and the register contents should not be modified.

Table 27-46 EPI_REGS_HB8CFG Registers
OffsetAcronymRegister NameWrite ProtectionSection
10hEPIHB8CFGEPI Host-Bus 8 ConfigurationGo
14hEPIHB8CFG2EPI Host-Bus 8 Configuration 2Go
308hEPIHB8CFG3EPI Host-Bus 8 Configuration 3Go
30ChEPIHB8CFG4EPI Host-Bus 8 Configuration 4Go
310hEPIHB8TIMEEPI Host-Bus 8 Timing ExtensionGo
314hEPIHB8TIME2EPI Host-Bus 8 Timing ExtensionGo
318hEPIHB8TIME3EPI Host-Bus 8 Timing ExtensionGo
31ChEPIHB8TIME4EPI Host-Bus 8 Timing ExtensionGo
360hEPIHBPSRAMEPI Host-Bus PSRAMGo

Complex bit access types are encoded to fit into small table cells. Table 27-47 shows the codes that are used for access types in this section.

Table 27-47 EPI_REGS_HB8CFG Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

27.2.4.1 EPIHB8CFG Register (Offset = 10h) [Reset = 0008FF00h]

EPIHB8CFG is shown in Figure 27-59 and described in Table 27-48.

Return to the Summary Table.

EPI Host-Bus 8 Configuration

Figure 27-59 EPIHB8CFG Register
3130292827262524
CLKGATECLKGATEICLKINVRDYENIRDYINVRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
2322212019181716
XFFENXFEENWRHIGHRDHIGHALEHIGHRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR-0h
15141312111098
MAXWAIT
R/W-FFh
76543210
WRWSRDWSRESERVEDMODE
R/W-0hR/W-0hR-0hR/W-0h
Table 27-48 EPIHB8CFG Register Field Descriptions
BitFieldTypeResetDescription
31CLKGATER/W0hA software application should only set the CLKGATE bit when there are no pending transfers or no EPI register access has been issued.

Reset type: SYSRSn


0h (R/W) = The EPI clock is free running.
1h (R/W) = The EPI clock is held low.
30CLKGATEIR/W0hNote that EPI0S32 is an iRDY signal if RDYEN is set. CLKGATEI is ignored if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD register is cleared.

Reset type: SYSRSn


0h (R/W) = The EPI clock is free running.
1h (R/W) = The EPI clock is output only when there is data to write or read (current transaction)
otherwise the EPI clock is held low.
29CLKINVR/W0hInvert Output Clock Enable

Reset type: SYSRSn


0h (R/W) = No effect.
1h (R/W) = Invert EPI clock to ensure the rising edge is centered for outbound signal's setup and hold. Inbound signal is captured on rising edge EPI clock.
28RDYENR/W0hInput Ready Enable

Reset type: SYSRSn


0h (R/W) = No effect.
1h (R/W) = An external ready can be used to control the continuation of the current access. If this bit is set and the iRDY signal (EPIS032) is low, the current access is stalled.
27IRDYINVR/W0hInput Ready Invert

Reset type: SYSRSn


0h (R/W) = No effect.
1h (R/W) = Invert the polarity of incoming external ready (iRDY signal). If this bit is set and the iRDY signal (EPIS032) is high the current access is stalled.
26-24RESERVEDR0hReserved

Reset type: SYSRSn

23XFFENR/W0hExternal FIFO FULL Enable

Reset type: SYSRSn


0h (R/W) = No effect.
1h (R/W) = An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL full signal is high, XFIFO writes are stalled.
22XFEENR/W0hExternal FIFO EMPTY Enable

Reset type: SYSRSn


0h (R/W) = No effect.
1h (R/W) = An external FIFO empty signal can be used to control read cycles. If this bit is set and the FEMPTY signal is high, XFIFO reads are stalled.
21WRHIGHR/W0hWRITE Strobe Polarity

Reset type: SYSRSn


0h (R/W) = The WRITE strobe for CS0n is WRn (active Low).
1h (R/W) = The WRITE strobe for CS0n is WR (active High).
20RDHIGHR/W0hREAD Strobe Polarity

Reset type: SYSRSn


0h (R/W) = The READ strobe for CS0n is RDn (active Low).
1h (R/W) = The READ strobe for CS0n is RD (active High).
19ALEHIGHR/W1hALE Strobe Polarity

Reset type: SYSRSn


0h (R/W) = The address latch strobe for CS0n accesses is ALEn (active Low).
1h (R/W) = The address latch strobe for CS0n accesses is ALE (active High).
18-17RESERVEDR/W0hReserved
16RESERVEDR0hReserved

Reset type: SYSRSn

15-8MAXWAITR/WFFhThis field defines the maximum number of external clocks to wait while an external FIFO ready signal is holding off a transaction (FFULL and FEMPTY). When the MAXWAIT value is reached the ERRRIS interrupt status bit is set in the EPIRIS register. When this field is clear, the transaction can be held off forever without a system interrupt. When the MODE field is configured to be 0x2 and the BLKEN bit is set in the EPICFG register, enabling HB8 mode, this field defaults to 0xFF.

Reset type: SYSRSn

7-6WRWSR/W0hThis field adds wait states to the data phase of CS0n (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity. This field is not applicable in BURST mode. This field is used in conjunction with the EPIBAUD register.

Reset type: SYSRSn


0h (R/W) = Active WRn is 2 EPI clocks.
1h (R/W) = Active WRn is 4 EPI clocks.
2h (R/W) = Active WRn is 6 EPI clocks.
3h (R/W) = Active WRn is 8 EPI clocks.
5-4RDWSR/W0hThis field adds wait states to the data phase of CS0n (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. The RDWSM bit in the EPIHB8TIME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity. This field is not applicable in BURST mode. This field is used in conjunction with the EPIBAUD register

Reset type: SYSRSn


0h (R/W) = Active RDn is 2 EPI clocks.
1h (R/W) = Active RDn is 4 EPI clocks.
2h (R/W) = Active RDn is 6 EPI clocks.
3h (R/W) = Active RDn is 8 EPI clocks.
3-2RESERVEDR0hReserved

Reset type: SYSRSn

1-0MODER/W0hThis field determines which of four Host Bus 8 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See for information on how this bit field affects the operation of the EPI signals. When used with multiple chip select option and the CSBAUD bit is set to 1 in the EPIHB8CFG2 register, this configuration is for CS0n. If the multiple chip select option is enabled and CSBAUD is clear, all chip-selects use the MODE encoding programmed in this register.

Reset type: SYSRSn


0h (R/W) = ADMUX - AD[7:0]. Data and Address are muxed.
1h (R/W) = ADNONMUX - D[7:0]. Data and address are separate.
2h (R/W) = Continuous Read - D[7:0]. This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OEn strobing.
3h (R/W) = XFIFO - D[7:0]. This mode adds XFIFO controls with sense of XFIFO full and XFIFO empty. This mode uses no address or ALE. The XFIFO can only be used in asynchronous mode.

27.2.4.2 EPIHB8CFG2 Register (Offset = 14h) [Reset = 00080000h]

EPIHB8CFG2 is shown in Figure 27-60 and described in Table 27-49.

Return to the Summary Table.

EPI Host-Bus 8 Configuration 2

Figure 27-60 EPIHB8CFG2 Register
3130292827262524
RESERVEDCSCFGEXTCSBAUDCSCFG
R-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDWRHIGHRDHIGHALEHIGHRESERVEDRESERVED
R-0hR/W-0hR/W-0hR/W-1hR/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
WRWSRDWSRESERVEDRESERVEDMODE
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 27-49 EPIHB8CFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved

Reset type: SYSRSn

27CSCFGEXTR/W0hThis field is used in conjunction with CSCFG, to extend the chip select options, and ALE format. The values 0x0 through 0x3 are from the CSCFG field. The CSCFGEXT bit extends the values to 0x7.

Reset type: SYSRSn


0h (R/W) = CSCFG bit field is used in chip select configuration.
1h (R/W) = The CSCFG bit field is extended with CSCFGEXT representing the MSB.
26CSBAUDR/W0hThis bit is only valid when the CSCFGEXT + CSCFG field is programmed to 0x2 or 0x3, 0x5 or 0x6. This bit configures the baud rate settings for CS0n, CS1n, CS2n, and CS3n. This bit must also be set to allow different sub-mode configurations on chip-selects. If this bit is clear, all chip-select sub-modes are based on the MODE encoding defined in the EPI8HBCFG register. If the CSBAUD bit is set in the EPIHBnCFG2 register and dual- or quad-chip selects are enabled, then the individual chip selects can use different clock frequencies, wait states and strobe polarity.

Reset type: SYSRSn


0h (R/W) = Same Baud Rate and Same Sub-ModeAll CSn use the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register and the sub-mode programmed in the MODE field of the EPIHB8CFG register.
1h (R/W) = Different Baud RatesCS0n uses the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register. CS1n uses the baud rate defined by the COUNT1 field in the EPIBAUD register.CS2n uses the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD2 register. CS3n uses the baud rate defined by the COUNT1 field in the EPIBAUD2 register.In addition, the sub-modes for each chip select are individually programmed in their respective EPIHB8CFGn registers.
25-24CSCFGR/W0hThis field controls the chip select options, including an ALE format, a single chip select, two chip selects, and an ALE combined with two chip selects. These bits are also used in combination with the CSCFGEXT bit for further configurations, including quad- chip select.

Reset type: SYSRSn


0h (R/W) = ALE Configuration. EPI0S30 is used as an address latch (ALE). The ALE signal is generally used when the address and data are muxed (HB8MODE field in the EPIHB8CFG register is 0x0). The ALE signal is used by an external latch to hold the address through the bus cycle.
1h (R/W) = CSn Configuration. EPI0S30 is used as a Chip Select (CSn). When using this mode, the address and data are generally not muxed (HB8MODE field in the EPIHB8CFG register is 0x1). However, if address and data muxing is needed, the WR signal (EPI0S29) and the RD signal (EPI0S28) can be used to latch the address when CSn is low.
2h (R/W) = Dual CSn Configuration. EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined by two methods. If only external RAM or external PER is enabled in the address map, the most significant address bit for a respective external address map controls CS0n or CS1n. If both external RAM and external PER is enabled, CS0n is mapped to PER and CS1n is mapped to RAM. This configuration can be used for a RAM bank split between 2 devices as well as when using both an external RAM and an external peripheral.
3h (R/W) = ALE with Dual CSn Configuration. EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map.
23-22RESERVEDR0hReserved

Reset type: SYSRSn

21WRHIGHR/W0hThis field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled.

Reset type: SYSRSn


0h (R/W) = The WRITE strobe for CS1n accesses is WRn (active Low).
1h (R/W) = The WRITE strobe for CS1n accesses is WR (active High).
20RDHIGHR/W0hThis field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled.

Reset type: SYSRSn


0h (R/W) = The READ strobe for CS1n accesses is RDn (active Low).
1h (R/W) = The READ strobe for CS1n accesses is RD (active High).
19ALEHIGHR/W1hThis field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled.

Reset type: SYSRSn


0h (R/W) = The address latch strobe for CS1n accesses is ALEn (active Low).
1h (R/W) = The address latch strobe for CS1n accesses is ALE (active High).
18-17RESERVEDR/W0hReserved
16-8RESERVEDR0hReserved

Reset type: SYSRSn

7-6WRWSR/W0hThis field adds wait states to the data phase of CS1n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state encoding adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME2 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity. This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is used in conjunction with the EPIBAUD register and is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = Active WRn is 2 EPI clocks.
1h (R/W) = Active WRn is 4 EPI clocks
2h (R/W) = Active WRn is 6 EPI clocks
3h (R/W) = Active WRn is 8 EPI clocks
5-4RDWSR/W0hThis field adds wait states to the data phase of CS1n accesses (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state encoding adds 2 EPI clock cycles to the access time. The RDWSM bit in the EPIHB8TIME2 register can decrease the number of states by 1 EPI clock cycle for greater granularity. This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is used in conjunction with the EPIBAUD register and is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = Active RDn is 2 EPI clocks
1h (R/W) = Active RDn is 4 EPI clocks
2h (R/W) = Active RDn is 6 EPI clocks
3h (R/W) = Active RDn is 8 EPI clocks
3RESERVEDR/W0hReserved
2RESERVEDR0hReserved

Reset type: SYSRSn

1-0MODER/W0hThis field determines which Host Bus 8 sub-mode to use for CS1. Sub-mode use is determined by the externally connected peripheral or memory. The CSBAUD bit must be set to enable this CS1 MODE field. If CSBAUD is clear, all chip- selects use the MODE configuration defined in the EPIHB8CFG register.

Reset type: SYSRSn


0h (R/W) = ADMUX - AD[7:0] Data and Address are muxed.
1h (R/W) = ADNONMUX - D[7:0]Data and address are separate.
2h (R/W) = Continuous Read - D[7:0] This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OE strobing.
3h (R/W) = Reserved

27.2.4.3 EPIHB8CFG3 Register (Offset = 308h) [Reset = 00080000h]

EPIHB8CFG3 is shown in Figure 27-61 and described in Table 27-50.

Return to the Summary Table.

EPI Host-Bus 8 Configuration 3

Figure 27-61 EPIHB8CFG3 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDWRHIGHRDHIGHALEHIGHRESERVED
R-0hR/W-0hR/W-0hR/W-1hR/W-0h
15141312111098
RESERVED
R-0h
76543210
WRWSRDWSRESERVEDRESERVEDMODE
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 27-50 EPIHB8CFG3 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved

Reset type: SYSRSn

21WRHIGHR/W0hThis field is used if the CSBAUD bit is enabled in EPIHB8CFG2.

Reset type: SYSRSn


0h (R/W) = The WRITE strobe for CS2n accesses is WRn (active Low).
1h (R/W) = The WRITE strobe for CS2n accesses is WR (active High).
20RDHIGHR/W0hThis field is used if the CSBAUD bit is enabled in EPIHB8CFG2.

Reset type: SYSRSn


0h (R/W) = The READ strobe for CS2n accesses is RDn (active Low).
1h (R/W) = The READ strobe for CS2n accesses is RD (active High).
19ALEHIGHR/W1hThis field is used if the CSBAUD bit is enabled in EPIHB8CFG2.

Reset type: SYSRSn


0h (R/W) = The address latch strobe for CS2n accesses is ADVn (active Low).
1h (R/W) = The address latch strobe for CS2n accesses is ALE (active High).
18-16RESERVEDR/W0hReserved
15-8RESERVEDR0hReserved

Reset type: SYSRSn

7-6WRWSR/W0hThis field adds wait states to the data phase of CS2n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME3 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity. This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is not applicable in BURST mode. This field is used in conjunction with the EPIBAUD2 register.

Reset type: SYSRSn


0h (R/W) = Active WRn is 2 EPI clocks
1h (R/W) = Active WRn is 4 EPI clocks
2h (R/W) = Active WRn is 6 EPI clocks
3h (R/W) = Active WRn is 8 EPI clocks
5-4RDWSR/W0hThis field adds wait states to the data phase of CS2n accesses (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. The RDWSM bit in the EPIHB8TIME3 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity. This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is not applicable in BURST mode. This field is used in conjunction with the EPIBAUD2 register.

Reset type: SYSRSn


0h (R/W) = Active RDn is 2 EPI clocks
1h (R/W) = Active RDn is 4 EPI clocks
2h (R/W) = Active RDn is 6 EPI clocks
3h (R/W) = Active RDn is 8 EPI clocks
3RESERVEDR/W0hReserved
2RESERVEDR0hReserved

Reset type: SYSRSn

1-0MODER/W0hThis field determines which Host Bus 8 sub-mode to use for CS2n in multiple chip-select mode. Sub-mode use is determined by the connected external peripheral. See for information on how this bit field affects the operation of the EPI signals. The CSBAUD bit must be set to enable this CS2n MODE field. If CSBAUD is clear, all chip-selects use the MODE configuration defined in the EPIHB8CFG register.

Reset type: SYSRSn


0h (R/W) = ADMUX - AD[7:0] Data and Address are muxed.
1h (R/W) = ADNONMUX - D[7:0]Data and address are separate.
2h (R/W) = Continuous Read - D[7:0] This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OE strobing.
3h (R/W) = Reserved

27.2.4.4 EPIHB8CFG4 Register (Offset = 30Ch) [Reset = 00080000h]

EPIHB8CFG4 is shown in Figure 27-62 and described in Table 27-51.

Return to the Summary Table.

EPI Host-Bus 8 Configuration 4

Figure 27-62 EPIHB8CFG4 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDWRHIGHRDHIGHALEHIGHRESERVED
R-0hR/W-0hR/W-0hR/W-1hR/W-0h
15141312111098
RESERVED
R-0h
76543210
WRWSRDWSRESERVEDRESERVEDMODE
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 27-51 EPIHB8CFG4 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved

Reset type: SYSRSn

21WRHIGHR/W0hThis field is used if the CSBAUD bit is enabled in EPIHB8CFG2.

Reset type: SYSRSn


0h (R/W) = The WRITE strobe for CS3n accesses is WRn (active low).
1h (R/W) = The WRITE strobe for CS3n accesses is WR (active high).
20RDHIGHR/W0hThis field is used if the CSBAUD bit is enabled in EPIHB8CFG2.

Reset type: SYSRSn


0h (R/W) = The READ strobe for CS3n accesses is RDn (active low).
1h (R/W) = The READ strobe for CS3n accesses is RD (active high).
19ALEHIGHR/W1hThis field is used if the CSBAUD bit is enabled in EPIHB8CFG2

Reset type: SYSRSn


0h (R/W) = The address latch strobe for CS3n accesses is ADVn (active low).
1h (R/W) = The address latch strobe for CS3n accesses is ALE (active high).
18-16RESERVEDR/W0hReserved
15-8RESERVEDR0hReserved

Reset type: SYSRSn

7-6WRWSR/W0hThis field adds wait states to the data phase of CS3n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME4 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity. This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is not applicable in BURST mode. This field is used in conjunction with the EPIBAUD2 register.

Reset type: SYSRSn


0h (R/W) = Active WRn is 2 EPI clocks
1h (R/W) = Active WRn is 4 EPI clocks
2h (R/W) = Active WRn is 6 EPI clocks
3h (R/W) = Active WRn is 8 EPI clocks
5-4RDWSR/W0hThis field adds wait states to the data phase of CS3n accesses (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. The RDWSM bit in the EPIHB8TIME4 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity. This field is used when the CSBAUD bit is set in the EPIHB8CFG2 register. This field is not applicable in BURST mode. This field is used in conjunction with the EPIBAUD2 register.

Reset type: SYSRSn


0h (R/W) = Active RDn is 2 EPI clocks
1h (R/W) = Active RDn is 4 EPI clocks
2h (R/W) = Active RDn is 6 EPI clocks
3h (R/W) = Active RDn is 8 EPI clocks
3RESERVEDR/W0hReserved
2RESERVEDR0hReserved

Reset type: SYSRSn

1-0MODER/W0hThis field determines which Host Bus 8 sub-mode to use for CS3n in multiple chip select mode. Sub-mode use is determined by the connected external peripheral. See for information on how this bit field affects the operation of the EPI signals. The CSBAUD bit must be set to enable this CS3n MODE field. If CSBAUD is clear, all chip-selects use the MODE configuration defined in the EPIHB8CFG register.

Reset type: SYSRSn


0h (R/W) = ADMUX - AD[7:0] Data and Address are muxed.
1h (R/W) = ADNONMUX - D[7:0]Data and address are separate.
2h (R/W) = Continuous Read - D[7:0] This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OE strobing.
3h (R/W) = Reserved

27.2.4.5 EPIHB8TIME Register (Offset = 310h) [Reset = 00422000h]

EPIHB8TIME is shown in Figure 27-63 and described in Table 27-52.

Return to the Summary Table.

EPI Host-Bus 8 Timing Extension

Figure 27-63 EPIHB8TIME Register
3130292827262524
RESERVEDIRDYDLY
R-0hR/W-0h
2322212019181716
RESERVEDRESERVED
R-8hR/W-2h
15141312111098
RESERVEDCAPWIDTHRESERVED
R-0hR/W-2hR-0h
76543210
RESERVEDWRWSMRESERVEDRDWSM
R-0hR/W-0hR-0hR/W-0h
Table 27-52 EPIHB8TIME Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved

Reset type: SYSRSn

25-24IRDYDLYR/W0hCS0n Input Ready Delay

Reset type: SYSRSn


0h (R/W) = reserved
1h (R/W) = Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
2h (R/W) = Stall begins two EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
3h (R/W) = Stall begins three EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
23-19RESERVEDR8hReserved

Reset type: SYSRSn

18-16RESERVEDR/W2hReserved
15-14RESERVEDR0hReserved

Reset type: SYSRSn

13-12CAPWIDTHR/W2hControls the delay between Host- Bus transfers.

Reset type: SYSRSn


0h (R/W) = Reserved
1h (R/W) = 1 EPI clock.
2h (R/W) = 2 EPI clock.
3h (R/W) = Reserved
11-5RESERVEDR0hReserved

Reset type: SYSRSn

4WRWSMR/W0hThis bit is used with the WRWS field in EPIHB8CFG. This field is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB8CFG register.
1h (R/W) = Wait state value is now (WRWS - 1) where the WRWS field is programmed in EPIHB8CFG.
3-1RESERVEDR0hReserved

Reset type: SYSRSn

0RDWSMR/W0hUse with RDWS field in the EPIHB8CFG register. This field is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG.
1h (R/W) = Wait state value is now (RDWS - 1) where the RDWS field is programmed in EPIHB8CFG.

27.2.4.6 EPIHB8TIME2 Register (Offset = 314h) [Reset = 0002A000h]

EPIHB8TIME2 is shown in Figure 27-64 and described in Table 27-53.

Return to the Summary Table.

EPI Host-Bus 8 Timing Extension

Figure 27-64 EPIHB8TIME2 Register
3130292827262524
RESERVEDIRDYDLY
R-0hR/W-0h
2322212019181716
RESERVEDRESERVED
R-0hR/W-2h
15141312111098
RESERVEDCAPWIDTHRESERVED
R-2hR/W-2hR-0h
76543210
RESERVEDWRWSMRESERVEDRDWSM
R-0hR/W-0hR-0hR/W-0h
Table 27-53 EPIHB8TIME2 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved

Reset type: SYSRSn

25-24IRDYDLYR/W0hCS1n Input Ready Delay

Reset type: SYSRSn


0h (R/W) = reserved
1h (R/W) = Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
2h (R/W) = Stall begins two EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
3h (R/W) = Stall begins three EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
23-19RESERVEDR0hReserved

Reset type: SYSRSn

18-16RESERVEDR/W2hReserved
15-14RESERVEDR2hReserved

Reset type: SYSRSn


3h (R/W) = Reserved
13-12CAPWIDTHR/W2hControls the delay between Host- Bus transfers.

Reset type: SYSRSn


0h (R/W) = Reserved
1h (R/W) = 1 EPI clock.
2h (R/W) = 2 EPI clock.
11-5RESERVEDR0hReserved

Reset type: SYSRSn

4WRWSMR/W0hThis bit is used with the WRWS field in EPIHB8CFG2. This field is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB8CFG register.
1h (R/W) = Wait state value is now (WRWS - 1) where the WRWS field is programmed in EPIHB8CFG.
3-1RESERVEDR0hReserved

Reset type: SYSRSn

0RDWSMR/W0hThis field is used with RDWS field in EPIHB8CFG2. This bit is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG.
1h (R/W) = Wait state value is now (RDWS - 1) where the RDWS field is programmed in EPIHB8CFG.

27.2.4.7 EPIHB8TIME3 Register (Offset = 318h) [Reset = 0002A000h]

EPIHB8TIME3 is shown in Figure 27-65 and described in Table 27-54.

Return to the Summary Table.

EPI Host-Bus 8 Timing Extension

Figure 27-65 EPIHB8TIME3 Register
3130292827262524
RESERVEDIRDYDLY
R-0hR/W-0h
2322212019181716
RESERVEDRESERVED
R-0hR/W-2h
15141312111098
RESERVEDCAPWIDTHRESERVED
R-2hR/W-2hR-0h
76543210
RESERVEDWRWSMRESERVEDRDWSM
R-0hR/W-0hR-0hR/W-0h
Table 27-54 EPIHB8TIME3 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved

Reset type: SYSRSn

25-24IRDYDLYR/W0hCS2n Input Ready Delay

Reset type: SYSRSn


0h (R/W) = reserved
1h (R/W) = Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
2h (R/W) = Stall begins two EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
3h (R/W) = Stall begins three EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
23-19RESERVEDR0hReserved

Reset type: SYSRSn

18-16RESERVEDR/W2hReserved
15-14RESERVEDR2hReserved

Reset type: SYSRSn

13-12CAPWIDTHR/W2hControls the delay between Host- Bus transfers.

Reset type: SYSRSn


0h (R/W) = Reserved
1h (R/W) = 1 EPI clock.
2h (R/W) = 2 EPI clock.
11-5RESERVEDR0hReserved

Reset type: SYSRSn

4WRWSMR/W0hThis bit is used with the WRWS field in EPIHB8CFG3. This field is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB8CFG register.
1h (R/W) = Wait state value is now (WRWS - 1) where the WRWS field is programmed in EPIHB8CFG.
3-1RESERVEDR0hReserved

Reset type: SYSRSn

0RDWSMR/W0hThis field is used with RDWS field in EPIHB8CFG3. This bit is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG.
1h (R/W) = Wait state value is now (RDWS - 1) where the RDWS field is programmed in EPIHB8CFG.

27.2.4.8 EPIHB8TIME4 Register (Offset = 31Ch) [Reset = 0002A000h]

EPIHB8TIME4 is shown in Figure 27-66 and described in Table 27-55.

Return to the Summary Table.

EPI Host-Bus 8 Timing Extension

Figure 27-66 EPIHB8TIME4 Register
3130292827262524
RESERVEDIRDYDLY
R-0hR/W-0h
2322212019181716
RESERVEDRESERVED
R-0hR/W-2h
15141312111098
RESERVEDCAPWIDTHRESERVED
R-2hR/W-2hR-0h
76543210
RESERVEDWRWSMRESERVEDRDWSM
R-0hR/W-0hR-0hR/W-0h
Table 27-55 EPIHB8TIME4 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved

Reset type: SYSRSn

25-24IRDYDLYR/W0hCS3n Input Ready Delay

Reset type: SYSRSn


0h (R/W) = reserved
1h (R/W) = Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
2h (R/W) = Stall begins two EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
3h (R/W) = Stall begins three EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
23-19RESERVEDR0hBits [18:16] have the same RTL implementation as the HB16TIMEn register, even though this is not used in HB8 mode. Thus, the reset value of 0x2 is carried over from the PSRAMSZ bits of HB16TIMEn.

Reset type: SYSRSn

18-16RESERVEDR/W2hReserved
15-14RESERVEDR2hBits [18:16] have the same RTL implementation as the HB16TIMEn register, even though this is not used in HB8 mode. Thus, the reset value of 0x2 is carried over from the PSRAMSZ bits of HB16TIMEn.

Reset type: SYSRSn

13-12CAPWIDTHR/W2hControls the delay between Host- Bus transfers.

Reset type: SYSRSn


0h (R/W) = Reserved
1h (R/W) = 1 EPI clock.
2h (R/W) = 2 EPI clock.
11-5RESERVEDR0hReserved

Reset type: SYSRSn

4WRWSMR/W0hThis bit is used with the WRWS field in EPIHB8CFG4. This field is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB8CFG register.
1h (R/W) = Wait state value is now (WRWS - 1) where the WRWS field is programmed in EPIHB8CFG.
3-1RESERVEDR0hReserved

Reset type: SYSRSn

0RDWSMR/W0hThis field is used with RDWS field in EPIHB8CFG4. This bit is not applicable in BURST mode.

Reset type: SYSRSn


0h (R/W) = No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG.
1h (R/W) = Wait state value is now (RDWS - 1) where the RDWS field is programmed in EPIHB8CFG.

27.2.4.9 EPIHBPSRAM Register (Offset = 360h) [Reset = 00000000h]

EPIHBPSRAM is shown in Figure 27-67 and described in Table 27-56.

Return to the Summary Table.

EPI Host-Bus PSRAM

Figure 27-67 EPIHBPSRAM Register
313029282726252423222120191817161514131211109876543210
RESERVEDCR
R-0hR/W-0h
Table 27-56 EPIHBPSRAM Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved

Reset type: SYSRSn

20-0CRR/W0hDuring a configuration write, all 21 bits of the CR bit field are written to the PSRAM. During configuration reads, CR bits [15:0] of this register contain the configuration read of the PSRAM. CR[20:16] will not contain valid data.

Reset type: SYSRSn