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基于 Arm 的处理器
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AM69A

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32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX

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AM69A

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产品详情

Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 2.5Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Automotive Operating temperature range (°C) -40 to 105
Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 2.5Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Automotive Operating temperature range (°C) -40 to 105
FCBGA (ALY) 1414 961 mm² 31 x 31

Processor cores:

  • Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 2MB shared L2 cache per quad-core Cortex®-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core
  • Up to Four Deep Learning Accelerators:
    • Each with up to 8 Trillion Operations Per Second (TOPS)
    • Total of 32 Trillion Operations Per Second (32 TOPS)
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL
  • GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s

  • Multimedia:

    • Display subsystem supports:
      • Up to 4 displays
      • Up to two DSI 4L TX (up to 2.5K)
      • One eDP 4L
      • One DPI 24-bit RGB parallel interface
      • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
      • Safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • IMG BSX-64-4, up to 800 MHz
      • 50 GFLOPS, 4 GTexels/s
      • >500 MTexels/s, >8 GFLOPs
      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
      • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
      • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
    • Two Video Encoder/Decoder Modules
      • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
      • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
      • Support for up to 4K UHD resolution (3840 × 2160) per module
      • Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.
  • Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD

    Ethernet

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 2MB shared L2 cache per quad-core Cortex®-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core
  • Up to Four Deep Learning Accelerators:
    • Each with up to 8 Trillion Operations Per Second (TOPS)
    • Total of 32 Trillion Operations Per Second (32 TOPS)
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL
  • GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s

  • Multimedia:

    • Display subsystem supports:
      • Up to 4 displays
      • Up to two DSI 4L TX (up to 2.5K)
      • One eDP 4L
      • One DPI 24-bit RGB parallel interface
      • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
      • Safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • IMG BSX-64-4, up to 800 MHz
      • 50 GFLOPS, 4 GTexels/s
      • >500 MTexels/s, >8 GFLOPs
      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
      • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
      • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
    • Two Video Encoder/Decoder Modules
      • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
      • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
      • Support for up to 4K UHD resolution (3840 × 2160) per module
      • Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.
  • Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD

    Ethernet

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The AM69A scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69A provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the AM69A class of processors.

The AM69A scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69A provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the AM69A class of processors.
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类型 项目标题 下载最新的英语版本 日期
* 数据表 AM69Ax Processors, Silicon Revision 1.0 数据表 PDF | HTML 2023年 2月 28日
* 勘误表 J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH Processors Silicon Revision 1.0 PDF | HTML 2022年 2月 15日
更多文献资料 AM6xA ISP 调优指南 PDF | HTML 2023年 3月 2日
更多文献资料 Jacinto7 AM6x/DRA8x/TDA4x 原理图检查清单 PDF | HTML 下载英文版本 PDF | HTML 2023年 2月 24日
用户指南 J784S4/TDA4AP/TDA4VP/TDA4AH/TDA4VH Processors Technical Reference Manual -Public (Rev. B) 2022年 11月 9日
技术文章 How to simplify your embedded edge AI application development 2022年 1月 28日

设计和开发

如需其他信息或资源，请查看下方列表，点击标题即可进入详情页面。

评估板

SK-AM69 — AM69x starter kit for Sitara™ processors

The SK-AM69 Starter Kit/Evaluation Module (EVM) is based on the AM69x AI vision processor which includes an image signal processor (ISP) supporting up to 1440MP/s, 32 tera-operations-per-second (TOPS) AI accelerator, eight 64-bit Arm®-Cortex® A72 microprocessor, and H.264/H.265 video (...)

用户指南: PDF | HTML
下载英文版本: PDF | HTML
发送申请
IDE、配置、编译器或调试器

C7000-CGT — C7000 code generation tools (CGT) - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
TDA4VM — 具有深度学习、视觉功能和多媒体加速器的双核 Arm® Cortex®-A72 SoC 和 C7x DSP TDA4VM-Q1 — 适用于 L2、L3 和近场分析系统且采用深度学习的汽车片上系统 AM62A3 — 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power system, video doorbell, security camera AM62A7 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, video surveillance, lawn robot AM62A3-Q1 — Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7-Q1 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras AM69A — 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX AM68A — 8 TOPS vision SoC for 1-8 cameras, machine vision, smart traffic, retail automation
下载选项
IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页，验证是否能提供支持。

产品
汽车毫米波雷达传感器
AWR1243 — 76GHz 至 81GHz 高性能汽车类 MMIC AWR1443 — 集成 MCU 和硬件加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1642 — 集成 DSP 和 MCU 的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843 — 集成 DSP、MCU 和雷达加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843AOP — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 — 76GHz 至 81GHz 汽车类第二代高性能 MMIC AWR2944 — 适用于角雷达和远距离雷达的汽车类第二代 76GHz 至 81GHz 高性能 SoC AWR6443 — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 — 集成 DSP、MCU 和雷达加速器的单芯片 60GHz 至 64GHz 汽车雷达传感器 AWR6843AOP — 集成封装天线、DSP 和 MCU 的单芯片 60GHz 至 64GHz 汽车雷达传感器
工业毫米波雷达传感器
IWR1443 — 集成 MCU 和硬件加速器的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1642 — 集成 DSP 和 MCU 的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1843 — 集成 DSP、MCU 和雷达加速器的 76GHz 至 81GHz 单芯片工业雷达传感器 IWR6443 — 集成 MCU 和硬件加速器的 60GHz 至 64GHz 单芯片毫米波传感器 IWR6843 — 集成有处理功能的 60GHz 至 64GHz 单芯片智能毫米波传感器 IWR6843AOP — 具有集成封装天线 (AoP) 的单芯片 60GHz 至 64GHz 智能毫米波传感器
在云端开发 下载选项
IDE、配置、编译器或调试器

SYSCONFIG — 系统配置工具

SysConfig 是一款配置工具，旨在简化硬件和软件配置挑战，从而加速软件开发。

SysConfig 可作为 Code Composer Studio™ 集成开发环境的一部分以及作为独立应用提供。此外，可以通过访问 TI 开发人员专区，在云中运行 SysConfig。

SysConfig 提供直观的图形用户界面，用于配置引脚、外设、无线电、软件栈、RTOS、时钟树和其他元件。SysConfig 将自动检测、发现和解决冲突，来加快软件开发。

了解详情
软件编程工具

TI-EDGE-AI-CLOUD — 针对 Jacinto 处理器上 AI 推理的云工具评估

TI Edge AI Cloud 是一项免费在线服务，可用于评估 TDA4x 处理器的加速深度学习推理性能。您不需要购买评估板。该服务基于 Python；只需几分钟即可登录、部署模型并获得各种性能基准。

使用业界通用 API（包括 TensorFlow Lite、ONNX Runtime、TVM、GStreamer、Docker、ROS 和 OpenGL ES）轻松编译和部署模型并加速推理。无需使用手动工具即可加速 TDA4x 处理器的深度学习推理性能。

在云中评估
设计工具

PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具

TI 已与多家公司合作，提供各种使用 TI 处理器的软件、工具和 SOM，从而加快您的量产速度。下载此搜索工具，快速浏览我们的第三方解决方案，并寻找合适的第三方来满足您的需求。此处所列的软件、工具和模块由独立的第三方生产和管理，而非德州仪器 (TI)。

搜索工具按产品类型划分为以下类别：

  • 工具包括 IDE/编译器、调试和跟踪、仿真和建模软件以及闪存编程器。
  • 操作系统包括 TI 处理器支持的操作系统。
  • 应用软件是指应用特定的软件，包括在 TI 处理器上运行的中间件和库。
  • SoM 是模块上系统解决方案
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封装 引脚数 下载
FCBGA (ALY) 1414 了解详情

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

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