SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
| Register | Type | Combination |
|---|---|---|
| PSR | R/W (2)(1) | APSR, EPSR, and IPSR |
| IEPSR | RO | EPSR and IPSR |
| IAPSR | R/W | APSR and IPSR |
| EAPSR | R/W | APSR and EPSR |
| Address Offset | Reset | 0x0100 0000 | |
| Physical Address | Instance | ||
| Description | |||
| Also referred to as xPSR | |||
The Program Status Register (PSR) has three functions,
and the register bits are assigned to the different functions:
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| The PSR, IPSR, and EPSR registers can be accessed only in privileged mode; the APSR register can be accessed in privileged or unprivileged mode. | |||
| APSR contains the current state of the condition flags from previous instruction executions. | |||
| EPSR contains the Thumb state bit and the execution state bits for the if-then (IT) instruction or the interruptible-continuable instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return 0. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see Section 6.1.7). | |||
| IPSR contains the exception type number of the current ISR. | |||
| These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. Table 3-20 shows the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in Cortex-M3/M4F Instruction Set Technical User's Manual for more information about how to access the program status registers. | |||
| Type | R/W | ||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| N | Z | C | V | Q | ICI / IT | THUMB | RESERVED | ICI / IT | RESERVED | ISRNUM | |||||||||||||||||||||
| Bits | Field Name | Description | Type | Reset | |
|---|---|---|---|---|---|
| 31 | N | APSR Negative or Less Flag | R/W | 0 | |
| Value | Description | ||||
| 1 | The previous operation result was negative or less than. | ||||
| 0 | The previous operation result was positive, zero, greater than, or equal | ||||
| The value of this bit is meaningful only when accessing PSR or APSR. | |||||
| 30 | Z | APSR Zero Flag | R/W | 0 | |
| Value | Description | ||||
| 1 | The previous operation result was zero. | ||||
| 0 | The previous operation result was nonzero. | ||||
| The value of this bit is meaningful only when accessing PSR or APSR. | |||||
| 29 | C | APSR Carry or Borrow Flag | R/W | 0 | |
| Value | Description | ||||
| 1 | The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. | ||||
| 0 | The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. | ||||
| The value of this bit is meaningful only when accessing PSR or APSR. | |||||
| 28 | V | APSR Overflow Flag | R/W | 0 | |
| Value | Description | ||||
| 1 | The previous operation resulted in an overflow. | ||||
| 0 | The previous operation did not result in an overflow. | ||||
| The value of this bit is meaningful only when accessing PSR or APSR. | |||||
| 27 | Q | APSR Sticky Overflow and Saturation Flag | R/W | 0 | |
| Value | Description | ||||
| 1 | Overflow or saturation has occurred. (set by SSAT or USAT instructions). | ||||
| 0 | Overflow or saturation has not occurred since reset or since the bit was last cleared. | ||||
| The value of this
bit is meaningful only when accessing PSR or APSR. This flag is sticky, in that, when set by an instruction it remains set until explicitly cleared using an MSR instruction. |
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| 26–25 | ICI / IT | EPSR
ICI / IT status These bits, along with bits 15:10, contain the ICI field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are 0. The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex-M3/M4F Instruction Set Technical User's Manual for more information. The value of this field is meaningful only when accessing PSR or EPSR. |
R/O | 0x0 | |
| 24 | THUMB | EPSR
Thumb state This bit indicates the Thumb state and must always be set. The following can clear the THUMB bit:
|
R/O | 1 | |
| 23–16 | RESERVED | Reserved | R/O | 0x00 | |
| 15–10 | ICI / IT | EPSR ICI / IT
status These bits, along with bits 26:25, contain the ICI field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When an interrupt occurs during the execution of an LDM, STM, PUSH, or POP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. When EPSR holds the ICI execution state, bits 11:10 are 0. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See Cortex-M3/M4F Instruction Set Technical User's Manual for more information. The value of this field is meaningful only when accessing PSR or EPSR. |
R/O | 0x0 | |
| 9–7 | RESERVED | Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation. | R/O | 0x0 | |
| 6–0 | ISRNUM | IPSR ISR
Number This field contains the exception type number of the current ISR. |
R/O | 0x00 | |
| Value | Description | ||||
| 0x00 | Thread mode | ||||
| 0x01 | Reserved | ||||
| 0x02 | NMI | ||||
| 0x03 | Hard fault | ||||
| 0x04 | Memory management fault | ||||
| 0x05 | Bus fault | ||||
| 0x06 | Usage fault | ||||
| 0x07–0x0A | Reserved | ||||
| 0x0B | SVCall | ||||
| 0x0C | Reserved for debug | ||||
| 0x0D | Reserved | ||||
| 0x0E | PendSV | ||||
| 0x0F | SysTick | ||||
| 0x10 | Interrupt vector 0 | ||||
| 0x11 | Interrupt vector 1 | ||||
| ... | ... | ||||
| 0x31 | Interrupt vector 33 | ||||
| 0x32-0x7F | Reserved | ||||
| For more
information, see Section 6.1.2. The value of this field is meaningful only when accessing PSR or IPSR. |
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