SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
Figure 23-7 and Figure 23-8 show single and continuous transmission signal sequences, respectively, for Motorola SPI format with SPO = 1 and SPH = 0.
Figure 23-8 Motorola SPI Frame Format (Continuous Transfer) With SPO = 1 and SPH = 0
In this configuration, the following occurs during idle periods:
- SSIn_CLK is forced high
- SSIn_FSS is forced high
- The transmit data line SSIn_TX is arbitrarily forced low
- When the SSI is configured as a master, the SSI enables the SSIn_CLK DIO
- When the SSI is configured as a slave, the SSI disables the SSIn_CLK DIO
If the SSI is enabled and valid data is in the TX FIFO, the SSIFss master signal goes low at the start of transmission and transfers slave data onto the SSIn_RX line of the master immediately. The master SSIn_TX output DIO is enabled.
One-half SSIn_CLK period later, valid master data is transferred to the SSIn_TX line. When both the master and slave data have been set, the SSIn_CLK master clock pin becomes low after one additional half SSIn_CLK period. Data is captured on the falling edges and propagated on the rising edges of the SSIn_CLK signal.
For a single-word transmission after all bits of the data word are transferred, the SSIn_FSS line is returned to its IDLE high state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SSIn_FSS signal must pulse high between each data word transfer as the slave-select pin freezes the data in its serial peripheral register and keeps it from being altered if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the slave device between each data transfer to enable the serial peripheral data write. When the continuous transfer completes, the SSIn_FSS pin returns to its IDLE state one SSIn_CLK period after the last bit is captured.