SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Table 7-21 lists the secondary debug TAP register (SDTR). Table 7-22 lists the reset control.
| Bit | Field | Width | Type | Reset | Description |
|---|---|---|---|---|---|
| 23–21 | Reserved | 3 | R/W | 0 | Reserved |
| 20 | InhibitSleep | 1 | W | 0 | When 0, this bit does not influence the clock and the power settings to the module. While this bit is 1, power or clock for the module of the TAP is not allowed to be turned off once it is turned on. If the target does not have power or clock when setting this bit, InhibitSleep does not change the power/clock state until the target is powered and clocked again. |
| R | — | The value read does not reflect the value written until the power and clock controller has acted upon a change in the written value. | |||
| 19–18 | Reserved | 2 | R | — | Reserved |
| 17 | InReset | 1 | R | — | The InReset status and the ReleaseFromWIR control share the same bit. When 1, the module or modules controlled by the secondary TAP is in the reset state. When 0, the module or modules is not in reset. |
| ReleaseFromWIR | W | 0 | The InReset status and the ReleaseFromWIR control share the same bit. When a 1 is written to this bit and the module is held in reset due to the WaitInReset bit, the module reset is released. This only occurs if WaitInReset is 1 and it is the only cause for holding the module in reset. This is a self-clearing bit. Writing a 0 has no effect. | ||
| 16–14 | ResetControl | 3 | R/W | 0 | Override the application controls of the functional warm reset to a module. See Table 7-22. |
| 13–10 | Reserved | 4 | R/W | 0 | Reserved |
| 9 | VisibleTAP | 1 | R | — | When 1, the TAP is currently selected and visible in the active scan chain. The VisibleTap bit indicates that the TAP, which was previously selected with the SelectTap bit, is now part of the device master scan path. The VisibleTap bit is set by ICEPick when the Run‑Test‑Idle state is reached. |
| 8 | SelectTAP | 1 | R/W | 0 | The SelectTap bit allows scan controller software to change which secondary TAPs are included in the device level master scan path. When this bit is set to 1, the TAP is selected for inclusion in the master scan path when the TAP state advances to the Run‑Test‑Idle state. When this bit is changed to 0, the TAP is deselected from the master scan path when the TAP state advances to the Run‑Test‑Idle state. Selection or deselection occurs in the Run‑Test‑Idle state regardless of the current IR instruction. Writes to the SelectTap bit are blocked, and the bit is held at 0, if TapPresent is 0. |
| 7–4 | Reserved | 4 | R/W | 0 | Reserved |
| 3 | ForceActive (ForcePowerAndClock) | 1 | W | — | When ForceActive is 0, the module’s clock and power settings follow the normal application settings unless one of the other emulation controls is affecting the state. Setting the ForceActive bit causes the power and clock held on and to be turned on if necessary. In this sense, the ForceActive bit could be named ForcePowerAndClock. Clearing the ForceActive bit returns control of the power and clock settings to the application. If the application controls indicate that the power and clock must be off, the power and clock to the module is turned off. |
| R | — | The value read does not reflect the value written until the power and clock controller has acted upon a change in the written value. | |||
| 2 | Reserved | 1 | R | — | Reserved |
| 1 | TapAccessible | 1 | R | — | When 0, the TAP cannot be accessed due to security. When 1, the TAP can be accessed. |
| 0 | TapPresent | 1 | R | — | When 0, there is not a TAP assigned to this spot. When 1, this TAP exists in the device. If a TAP does not exist, the rest of the controls and status bits in this register are considered to be nonoperational. |
| Value | Command | Description |
|---|---|---|
| 000 | Normal Operation | Reset operates under the normal control of the application or device controls. |
| 001 | Wait in reset (Extend reset) | The module or modules controlled by this secondary TAP remain in the reset state when the reset is asserted. This bit alone does not reset the processor. |
| 010 | Reserved | Reserved |
| 011 | Reserved | Reserved |
| 1xx | Cancel | Cancels reset command lockout |