SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_TABLE_1 lists the memory-mapped registers for the CRYPTO registers. All register offset addresses not listed in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C |
Write 1 to clear |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
| Register Array Variables | ||
| i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
| y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. | |
DMACH0CTL is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH0CTL_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH0CTL_TABLE.
Return to the Summary Table.
Channel 0 Control
This register is used for channel enabling and
priority selection. When a channel is disabled, it becomes inactive only when all
ongoing requests are finished.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRIO | EN | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | PRIO | R/W | 0h | Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests. |
| 0 | EN | R/W | 0h | Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested. |
DMACH0EXTADDR is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH0EXTADDR_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH0EXTADDR_TABLE.
Return to the Summary Table.
Channel 0 External Address
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | ADDR | R/W | 0h | Channel external address value When read during operation, it holds the last updated external address after being sent to the master interface. Note: The crypto DMA copies out upto 3 bytes until it hits a word boundary, thus the address need not be word aligned. |
DMACH0LEN is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH0LEN_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH0LEN_TABLE.
Return to the Summary Table.
Channel 0 DMA Length
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMALEN | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-0 | DMALEN | R/W | 0h | Channel DMA length in bytes During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Note: Setting this register to a nonzero value starts the transfer if the channel is enabled. Therefore, this register must be written last when setting up a DMA channel. |
DMASTAT is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMASTAT_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMASTAT_TABLE.
Return to the Summary Table.
DMAC Status
This register provides the actual state of each DMA
channel. It also reports port errors in case these were received by the master
interface module during the data transfer.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PORT_ERR | RESERVED | |||||
| R-0h | R-0h | R-0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CH1_ACT | CH0_ACT | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R | 0h | Reserved |
| 17 | PORT_ERR | R | 0h | Reflects possible transfer errors on the AHB port. |
| 16-2 | RESERVED | R | 0h | Reserved |
| 1 | CH1_ACT | R | 0h | A value of 1 indicates that channel 1 is active (DMA transfer on-going). |
| 0 | CH0_ACT | R | 0h | A value of 1 indicates that channel 0 is active (DMA transfer on-going). |
DMASWRESET is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMASWRESET_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMASWRESET_TABLE.
Return to the Summary Table.
DMAC Software Reset
Software reset is used to reset the DMAC to stop all
transfers and clears the port error status register. After the software reset is
performed, all the channels are disabled and no new requests are performed by the
channels. The DMAC waits for the existing (active) requests to finish and
accordingly sets the DMASTAT.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SWRES | ||||||
| R-0h | W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | SWRES | W | 0h | Software reset enable 0 : Disabled 1 : Enabled (self-cleared to 0) Completion of the software reset must be checked through the DMASTAT |
DMACH1CTL is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH1CTL_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH1CTL_TABLE.
Return to the Summary Table.
Channel 1 Control
This register is used for channel enabling and
priority selection. When a channel is disabled, it becomes inactive only when all
ongoing requests are finished.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRIO | EN | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | PRIO | R/W | 0h | Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests. |
| 0 | EN | R/W | 0h | Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested. |
DMACH1EXTADDR is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH1EXTADDR_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH1EXTADDR_TABLE.
Return to the Summary Table.
Channel 1 External Address
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | ADDR | R/W | 0h | Channel external address value. When read during operation, it holds the last updated external address after being sent to the master interface. Note: The crypto DMA copies out upto 3 bytes until it hits a word boundary, thus the address need not be word aligned. |
DMACH1LEN is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH1LEN_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMACH1LEN_TABLE.
Return to the Summary Table.
Channel 1 DMA Length
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMALEN | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-0 | DMALEN | R/W | 0h | Channel DMA length in bytes. During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Note: Setting this register to a nonzero value starts the transfer if the channel is enabled. Therefore, this register must be written last when setting up a DMA channel. |
DMABUSCFG is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMABUSCFG_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMABUSCFG_TABLE.
Return to the Summary Table.
DMAC Master Run-time Parameters
This register defines all the run-time parameters for
the AHB master interface port. These parameters are required for the proper
functioning of the EIP-101m AHB master adapter.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| AHB_MST1_BURST_SIZE | AHB_MST1_IDLE_EN | AHB_MST1_INCR_EN | AHB_MST1_LOCK_EN | AHB_MST1_BIGEND | |||
| R/W-2h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-12 | AHB_MST1_BURST_SIZE | R/W | 2h | Maximum burst size that can be performed on the AHB
bus 2h = 4_BYTE : 4 bytes 3h = 8_BYTE : 8 bytes 4h = 16_BYTE : 16 bytes 5h = 32_BYTE : 32 bytes 6h = 64_BYTE : 64 bytes |
| 11 | AHB_MST1_IDLE_EN | R/W | 0h | Idle insertion between consecutive burst transfers on
AHB 0h = Do not insert idle transfers. 1h = Idle transfer insertion enabled |
| 10 | AHB_MST1_INCR_EN | R/W | 1h | Burst length type of AHB transfer 0h = Unspecified length burst transfers 1h = Fixed length bursts or single transfers |
| 9 | AHB_MST1_LOCK_EN | R/W | 0h | Locked transform on AHB 0h = Transfers are not locked 1h = Transfers are locked |
| 8 | AHB_MST1_BIGEND | R/W | 0h | Endianess for the AHB master 0h = Little Endian 1h = Big Endian |
| 7-0 | RESERVED | R | 0h | Reserved |
DMAPORTERR is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMAPORTERR_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMAPORTERR_TABLE.
Return to the Summary Table.
DMAC Port Error Raw Status
This register provides the actual status of individual
port errors. It also indicates which channel is serviced by an external AHB port
(which is frozen by a port error). A port error aborts operations on all serviced
channels (channel enable bit is forced to 0) and prevents further transfers via that
port until the error is cleared by writing to the DMASWRESET register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PORT1_AHB_ERROR | RESERVED | PORT1_CHANNEL | RESERVED | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-13 | RESERVED | R | 0h | Reserved |
| 12 | PORT1_AHB_ERROR | R | 0h | A value of 1 indicates that the EIP-101 has detected an AHB bus error |
| 11-10 | RESERVED | R | 0h | Reserved |
| 9 | PORT1_CHANNEL | R | 0h | Indicates which channel has serviced last (channel 0 or channel 1) by AHB master port. |
| 8-0 | RESERVED | R | 0h | Reserved |
DMAHWVER is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMAHWVER_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMAHWVER_TABLE.
Return to the Summary Table.
DMAC Version
This register contains an indication (or signature) of
the EIP type of this DMAC, as well as the hardware version/patch numbers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | HW_MAJOR_VERSION | ||||||
| R-0h | R-1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| HW_MINOR_VERSION | HW_PATCH_LEVEL | ||||||
| R-0h | R-1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EIP_NUMBER_COMPL | |||||||
| R-2Eh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EIP_NUMBER | |||||||
| R-D1h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R | 0h | Reserved |
| 27-24 | HW_MAJOR_VERSION | R | 1h | Major version number |
| 23-20 | HW_MINOR_VERSION | R | 0h | Minor version number |
| 19-16 | HW_PATCH_LEVEL | R | 1h | Patch level Starts at 0 at first delivery of this version |
| 15-8 | EIP_NUMBER_COMPL | R | 2Eh | Bit-by-bit complement of the EIP_NUMBER field bits. |
| 7-0 | EIP_NUMBER | R | D1h | Binary encoding of the EIP-number of this DMA controller (209) |
KEYWRITEAREA is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_KEYWRITEAREA_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_KEYWRITEAREA_TABLE.
Return to the Summary Table.
Key Store Write Area
This register defines where the keys should be written
in the key store RAM. After writing this register, the key store module is ready to
receive the keys through a DMA operation. In case the key data transfer triggered an
error in the key store, the error will be available in the interrupt status register
after the DMA is finished. The key store write-error is asserted when the
programmed/selected area is not completely written. This error is also asserted when
the DMA operation writes to ram areas that are not selected.
The key store RAM is divided into 8 areas of 128
bits.
192-bit keys written in the key store RAM
should start on boundaries of 256 bits. This means that writing a 192-bit key to the
key store RAM must be done by writing 256 bits of data with the 64 most-significant
bits set to 0. These bits are ignored by the AES engine.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAM_AREA7 | RAM_AREA6 | RAM_AREA5 | RAM_AREA4 | RAM_AREA3 | RAM_AREA2 | RAM_AREA1 | RAM_AREA0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7 | RAM_AREA7 | R/W | 0h | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA7 is not selected to be written. 1: RAM_AREA7 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written |
| 6 | RAM_AREA6 | R/W | 0h | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA6 is not selected to be written. 1: RAM_AREA6 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written |
| 5 | RAM_AREA5 | R/W | 0h | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA5 is not selected to be written. 1: RAM_AREA5 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written |
| 4 | RAM_AREA4 | R/W | 0h | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA4 is not selected to be written. 1: RAM_AREA4 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written |
| 3 | RAM_AREA3 | R/W | 0h | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA3 is not selected to be written. 1: RAM_AREA3 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written |
| 2 | RAM_AREA2 | R/W | 0h | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA2 is not selected to be written. 1: RAM_AREA2 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written |
| 1 | RAM_AREA1 | R/W | 0h | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA1 is not selected to be written. 1: RAM_AREA1 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written |
| 0 | RAM_AREA0 | R/W | 0h | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA0 is not selected to be written. 1: RAM_AREA0 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written |
KEYWRITTENAREA is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_KEYWRITTENAREA_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_KEYWRITTENAREA_TABLE.
Return to the Summary Table.
Key Store Written Area
This register shows which areas of the key store RAM
contain valid written keys.
When a new key needs to be
written to the key store, on a location that is already occupied by a valid key,
this key area must be cleared first. This can be done by writing this register
before the new key is written to the key store memory.
Attempting to write to a key area that already contains a valid key is not allowed
and results in an error.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAM_AREA_WRITTEN7 | RAM_AREA_WRITTEN6 | RAM_AREA_WRITTEN5 | RAM_AREA_WRITTEN4 | RAM_AREA_WRITTEN3 | RAM_AREA_WRITTEN2 | RAM_AREA_WRITTEN1 | RAM_AREA_WRITTEN0 |
| R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7 | RAM_AREA_WRITTEN7 | R/W1C | 0h | On read this bit returns the key area written
status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information |
| 6 | RAM_AREA_WRITTEN6 | R/W1C | 0h | On read this bit returns the key area written
status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information |
| 5 | RAM_AREA_WRITTEN5 | R/W1C | 0h | On read this bit returns the key area written
status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information |
| 4 | RAM_AREA_WRITTEN4 | R/W1C | 0h | On read this bit returns the key area written
status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information |
| 3 | RAM_AREA_WRITTEN3 | R/W1C | 0h | On read this bit returns the key area written
status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information |
| 2 | RAM_AREA_WRITTEN2 | R/W1C | 0h | On read this bit returns the key area written
status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information |
| 1 | RAM_AREA_WRITTEN1 | R/W1C | 0h | On read this bit returns the key area written
status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information |
| 0 | RAM_AREA_WRITTEN0 | R/W1C | 0h | On read this bit returns the key area written
status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. |
KEYSIZE is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_KEYSIZE_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_KEYSIZE_TABLE.
Return to the Summary Table.
Key Store Size
This register defines the size of the keys that are
written with DMA. This register should be configured before writing to the
KEY_STORE_WRITE_AREA register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SIZE | ||||||||||||||
| R-0h | R/W-1h | ||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1-0 | SIZE | R/W | 1h | Key size: 00: Reserved When writing this to this register, the KEY_STORE_WRITTEN_AREA register is reset. 1h = 128_BIT : 128 bits 2h = 192_BIT : 192 bits 3h = 256_BIT : 256 bits |
KEYREADAREA is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_KEYREADAREA_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_KEYREADAREA_TABLE.
Return to the Summary Table.
Key Store Read Area
This register selects the key store RAM area from
where the key needs to be read that will be used for an AES operation. The operation
directly starts after writing this register. When the operation is finished, the
status of the key store read operation is available in the interrupt status
register. Key store read error is asserted when a RAM area is selected which does
not contain valid written key.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| BUSY | RESERVED | ||||||
| R-0h | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RAM_AREA | ||||||
| R-0h | R/W-8h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | BUSY | R | 0h | Key store operation busy status flag (read only): 0: Operation is complete. 1: Operation is not completed and the key store is busy. |
| 30-4 | RESERVED | R | 0h | Reserved |
| 3-0 | RAM_AREA | R/W | 8h | Selects the area of the key store RAM from where the
key needs to be read that will be writen to the AES engine RAM_AREA: RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes. Only RAM areas that contain valid written keys can be selected. 0h = RAM Area 0 1h = RAM Area 1 2h = RAM Area 2 3h = RAM Area 3 4h = RAM Area 4 5h = RAM Area 5 6h = RAM Area 6 7h = RAM Area 7 8h = No RAM |
AESKEY2_y is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESKEY2_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESKEY2_TABLE.
Return to the Summary Table.
AES_KEY2_0 / AES_GHASH_H_IN_0
Second Key / GHASH Key (internal, but clearable)
The following registers are not accessible through the
host for reading and writing. They are used to store internally calculated key
information and intermediate results. However, when the host performs a write to the
any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole
128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s.
The AES_GHASH_H_IN_n registers (required for GHASH,
which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate)
authentication result for GCM and CCM is stored in the AES_KEY3_n register.
Offset = 500h + (y * 4h); where y = 0h to 3h
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_KEY2 | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AES_KEY2 | W | 0h | AES_KEY2/AES_GHASH_H[31:0] For GCM: -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM). -[255:128] - This register is used to store intermediate values and is initialized with 0s when loading a new key. For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. |
AESKEY3_y is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESKEY3_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESKEY3_TABLE.
Return to the Summary Table.
AES_KEY3_0 / AES_KEY2_4
Third Key / Second Key (internal, but clearable)
The following registers are not accessible through the
host for reading and writing. They are used to store internally calculated key
information and intermediate results. However, when the host performs a write to the
any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole
128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s.
The AES_GHASH_H_IN_n registers (required for GHASH,
which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate)
authentication result for GCM and CCM is stored in the AES_KEY3_n register.
Offset = 510h + (y * 4h); where y = 0h to 3h
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_KEY3 | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AES_KEY3 | W | 0h | AES_KEY3[31:0]/AES_KEY2[159:128] For GCM: -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM). -[255:128] - This register is used to store intermediate values and is initialized with 0s when loading a new key. For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. |
AESIV_y is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESIV_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESIV_TABLE.
Return to the Summary Table.
AES initialization vector registers
These registers are used to provide and read the IV
from the AES engine.
Offset = 540h + (y * 4h); where y = 0h to 3h
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_IV | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AES_IV | R/W | 0h | AES_IV[31:0] Initialization vector Used for regular non-ECB modes (CBC/CTR): -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers must be written with a new 128-bit IV. After an operation, these registers contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode is selected, this value is incremented with 0x1: After first use - When a new data block is submitted to the engine For GCM: -[127:0] - AES_IV - For GCM operations, these registers must be written with a new 128-bit IV. After an operation, these registers contain the updated 128-bit result IV, generated by the EIP-120t. Note that bits [127:96] of the IV represent the initial counter value (which is 1 for GCM) and must therefore be initialized to 0x01000000. This value is incremented with 0x1: After first use - When a new data block is submitted to the engine. For CCM: -[127:0] - A0: For CCM this field must be written with value A0, this value is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and counter value. 'L' must be a copy from the 'L' value of the AES_CTRL register. This 'L' indicates the width of the Nonce and counter. The loaded counter must be initialized to 0. The total width of A0 is 128-bit. For CBC-MAC: -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the start of each operation. After an operation, these registers contain the 128-bit TAG output, generated by the EIP-120t. |
AESCTL is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESCTL_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESCTL_TABLE.
Return to the Summary Table.
AES Control
AES input/output buffer control and mode register
This register specifies the AES mode of operation for
the EIP-120t.
Electronic codebook (ECB) mode is
automatically selected if bits [28:5] of this register are all 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CONTEXT_READY | SAVED_CONTEXT_RDY | SAVE_CONTEXT | RESERVED | CCM_M | |||
| R-1h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CCM_M | CCM_L | CCM | GCM | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CBC_MAC | RESERVED | CTR_WIDTH | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CTR_WIDTH | CTR | CBC | KEY_SIZE | DIR | INPUT_READY | OUTPUT_READY | |
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CONTEXT_READY | R | 1h | If 1, this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context. |
| 30 | SAVED_CONTEXT_RDY | R/W | 0h | If 1, this status bit indicates that an AES
authentication TAG and/or IV block(s) is/are available for the host
to retrieve. This bit is only asserted if the save_context bit is
set to 1. The bit is mutual exclusive with the context_ready bit. Writing one clears the bit to 0, indicating the AES core can start its next operation. This bit is also cleared when the 4th word of the output TAG and/or IV is read. Note: All other mode bit writes are ignored when this mode bit is written with 1. Note: This bit is controlled automatically by the EIP-120t for TAG read DMA operations. |
| 29 | SAVE_CONTEXT | R/W | 0h | This bit indicates that an authentication TAG or
result IV needs to be stored as a result context. Typically this bit must be set for authentication modes returning a TAG (CBC-MAC, GCM and CCM), or for basic encryption modes that require future continuation with the current result IV. If this bit is set, the engine retains its full context until the TAG and/or IV registers are read. The TAG or IV must be read before the AES engine can start a new operation. |
| 28-25 | RESERVED | R | 0h | Reserved |
| 24-22 | CCM_M | R/W | 0h | Defines M, which indicates the length of the
authentication field for CCM operations the authentication field length equals two times (the value of CCM-M plus one). Note: The EIP-120t always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported. |
| 21-19 | CCM_L | R/W | 0h | Defines L, which indicates the width of the length
field for CCM operations the length field in bytes equals the value of CMM-L plus one. All values are supported. |
| 18 | CCM | R/W | 0h | If set to 1, AES-CCM is selected AES-CCM is a combined mode, using AES for authentication and encryption. Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR selecting other AES modes than CTR mode is invalid. |
| 17-16 | GCM | R/W | 0h | Set these bits to 11 to select AES-GCM mode. AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR Bit combination description: 00 = No GCM mode 01 = Reserved, do not select 10 = Reserved, do not select 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), other GCM modes are not allowed. |
| 15 | CBC_MAC | R/W | 0h | Set to 1 to select AES-CBC MAC mode. The direction bit must be set to 1 for this mode. Selecting this mode requires writing the length register after all other registers. |
| 14-9 | RESERVED | R | 0h | Reserved |
| 8-7 | CTR_WIDTH | R/W | 0h | Specifies the counter width for AES-CTR mode 00 = 32-bit counter 01 = 64-bit counter 10 = 96-bit counter 11 = 128-bit counter 0h = 32_BIT : 32 bits 1h = 64_BIT : 64 bits 2h = 96_BIT : 96 bits 3h = 128_BIT : 128 bits |
| 6 | CTR | R/W | 0h | If set to 1, AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM, when encryption/decryption is required. |
| 5 | CBC | R/W | 0h | If set to 1, cipher-block-chaining (CBC) mode is selected. |
| 4-3 | KEY_SIZE | R | 0h | This read-only field specifies the key size. The key size is automatically configured when a new key is loaded through the key store module. 00 = N/A - Reserved 01 = 128-bit 10 = 192-bit 11 = 256-bit |
| 2 | DIR | R/W | 0h | If set to 1 an encrypt operation is performed. If set to 0 a decrypt operation is performed. This bit must be written with a 1 when CBC-MAC is selected. |
| 1 | INPUT_READY | R/W | 0h | If 1, this status bit indicates that the 16-byte AES
input buffer is empty. The host is permitted to write the next block
of data. Writing 0 clears the bit to 0 and indicates that the AES core can use the provided input data block. Writing 1 to this bit is ignored. Note: For DMA operations, this bit is automatically controlled by the EIP-120t. After reset, this bit is 0. After writing a context, this bit becomes 1. |
| 0 | OUTPUT_READY | R/W | 0h | If 1, this status bit indicates that an AES output
block is available to be retrieved by the host. Writing 0 clears the bit to 0 and indicates that output data is read by the host. The AES core can provide a next output data block. Writing 1 to this bit is ignored. Note: For DMA operations, this bit is automatically controlled by the EIP-120t. |
AESDATALEN0 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATALEN0_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATALEN0_TABLE.
Return to the Summary Table.
AES Crypto Length 0 (LSW)
These registers are used to write the Length values to
the EIP-120t. While processing, the length values decrement to 0. If both lengths
are 0, the data stream is finished and a new context is requested. For basic AES
modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams
need to be processed with the same key. Writing 0 length results in continued data
requests until a new context is written. For the other modes (CBC-MAC, GCM, and CCM)
no (new) data requests are done if the length decrements to or equals 0.
It is advised to write a new length per packet. If the
length registers decrement to 0, no new data is processed until a new context or
length value is written.
When writing a new mode
without writing the length registers, the length register values from the previous
context is reused.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| C_LENGTH | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | C_LENGTH | W | 0h | C_LENGTH[31:0] Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to 0. Data lengths up to (261: 1) bytes are allowed. For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note: For the combined modes (GCM and CCM), this length does not include the authentication only data the authentication length is specified in the AESAUTHLEN register All modes must have a length greater than 0. For the combined modes, it is allowed to have one of the lengths equal to 0. For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program zero to the length field in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes bit aligned data streams are not supported by the EIP-120t. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. For a host read operation, these registers return all-0s. |
AESDATALEN1 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATALEN1_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATALEN1_TABLE.
Return to the Summary Table.
AES Crypto Length 1 (MSW)
These registers are used to write the Length values to
the EIP-120t. While processing, the length values decrement to 0. If both lengths
are 0, the data stream is finished and a new context is requested. For basic AES
modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams
need to be processed with the same key. Writing 0 length results in continued data
requests until a new context is written. For the other modes (CBC-MAC, GCM and CCM)
no (new) data requests are done if the length decrements to or equals 0.
It is advised to write a new length per packet. If the
length registers decrement to 0, no new data is processed until a new context or
length value is written.
When writing a new mode
without writing the length registers, the length register values from the previous
context is reused.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | C_LENGTH | ||||||||||||||
| R-0h | W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| C_LENGTH | |||||||||||||||
| W-0h | |||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R | 0h | Reserved |
| 28-0 | C_LENGTH | W | 0h | C_LENGTH[60:32] Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to 0. Data lengths up to (261: 1) bytes are allowed. For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note: For the combined modes (GCM and CCM), this length does not include the authentication only data the authentication length is specified in the AESAUTHLEN register All modes must have a length greater than 0. For the combined modes, it is allowed to have one of the lengths equal to 0. For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program zero to the length field in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes bit aligned data streams are not supported by the EIP-120t. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. For a host read operation, these registers return all-0s. |
AESAUTHLEN is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESAUTHLEN_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESAUTHLEN_TABLE.
Return to the Summary Table.
AES Authentication Length
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AUTH_LENGTH | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AUTH_LENGTH | W | 0h | Bits [31:0] of the authentication length register
store the authentication data length in bytes for combined modes
only (GCM or CCM). Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. For GCM any value up to (232 - 1) bytes can be used. Once processing with this context is started, this length decrements to 0. A write to this register triggers the engine to start using this context for GCM and CCM. For a host read operation, these registers return all-0s. |
AESDATAOUT0 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAOUT0_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAOUT0_TABLE.
Return to the Summary Table.
Data Input/Output
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R | 0h | Data register 0 for output block data from the Crypto
peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
AESDATAIN0 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAIN0_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAIN0_TABLE.
Return to the Summary Table.
AES Data Input_Output 0
The data registers are typically accessed through the
DMA and not with host writes and/or reads. However, for debugging purposes the data
input/output registers can be accessed via host write and read operations. The
registers are used to buffer the input/output data blocks to/from the EIP-120t.
Note: The data input buffer (AES_DATA_IN_n) and data
output buffer (AES_DATA_OUT_n) are mapped to the same address locations.
Writes (both DMA and host) to these addresses load the
Input Buffer while reads pull from the Output Buffer. Therefore, for write access,
the data input buffer is written
for read access, the
data output buffer is read. The data input buffer must be written before starting an
operation. The data output buffer contains valid data on completion of an operation.
Therefore, any 128-bit data block can be split over multiple 32-bit word
transfers
these can be mixed with other host
transfers over the external interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_DATA_IN_OUT | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AES_DATA_IN_OUT | W | 0h | AES input data[31:0] / AES output data[31:0] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
AESDATAOUT1 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAOUT1_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAOUT1_TABLE.
Return to the Summary Table.
Data Input/Output
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R | 0h | Data register 0 for output block data from the Crypto
peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
AESDATAIN1 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAIN1_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAIN1_TABLE.
Return to the Summary Table.
AES Data Input_Output 0
The data registers are typically accessed through the
DMA and not with host writes and/or reads. However, for debugging purposes the data
input/output registers can be accessed via host write and read operations. The
registers are used to buffer the input/output data blocks to/from the EIP-120t.
Note: The data input buffer (AES_DATA_IN_n) and data
output buffer (AES_DATA_OUT_n) are mapped to the same address locations.
Writes (both DMA and host) to these addresses load the
Input Buffer while reads pull from the Output Buffer. Therefore, for write access,
the data input buffer is written
for read access, the
data output buffer is read. The data input buffer must be written before starting an
operation. The data output buffer contains valid data on completion of an operation.
Therefore, any 128-bit data block can be split over multiple 32-bit word
transfers
these can be mixed with other host
transfers over the external interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_DATA_IN_OUT | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AES_DATA_IN_OUT | W | 0h | AES input data[31:0] / AES output data[63:32] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
AESDATAOUT2 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAOUT2_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAOUT2_TABLE.
Return to the Summary Table.
Data Input/Output
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R | 0h | Data register 0 for output block data from the Crypto
peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
AESDATAIN2 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAIN2_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAIN2_TABLE.
Return to the Summary Table.
AES Data Input_Output 2
The data registers are typically accessed via DMA and
not with host writes and/or reads. However, for debugging purposes the Data
Input/Output Registers can be accessed via host write and read operations. The
registers are used to buffer the input/output data blocks to/from the EIP-120t.
Note: The data input buffer (AES_DATA_IN_n) and data
output buffer (AES_DATA_OUT_n) are mapped to the same address locations.
Writes (both DMA and host) to these addresses load the
Input Buffer while reads pull from the Output Buffer. Therefore, for write access,
the data input buffer is written
for read access, the
data output buffer is read. The data input buffer must be written before starting an
operation. The data output buffer contains valid data on completion of an operation.
Therefore, any 128-bit data block can be split over multiple 32-bit word
transfers
these can be mixed with other host
transfers over the external interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_DATA_IN_OUT | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AES_DATA_IN_OUT | W | 0h | AES input data[95:64] / AES output data[95:64] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
AESDATAOUT3 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAOUT3_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAOUT3_TABLE.
Return to the Summary Table.
Data Input/Output
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R | 0h | Data register 0 for output block data from the Crypto
peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
AESDATAIN3 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAIN3_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESDATAIN3_TABLE.
Return to the Summary Table.
AES Data Input_Output 3
The data registers are typically accessed via DMA and
not with host writes and/or reads. However, for debugging purposes the Data
Input/Output Registers can be accessed via host write and read operations. The
registers are used to buffer the input/output data blocks to/from the EIP-120t.
Note: The data input buffer (AES_DATA_IN_n) and data
output buffer (AES_DATA_OUT_n) are mapped to the same address locations.
Writes (both DMA and host) to these addresses load the
Input Buffer while reads pull from the Output Buffer. Therefore, for write access,
the data input buffer is written
for read access, the
data output buffer is read. The data input buffer must be written before starting an
operation. The data output buffer contains valid data on completion of an operation.
Therefore, any 128-bit data block can be split over multiple 32-bit word
transfers
these can be mixed with other host
transfers over the external interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_DATA_IN_OUT | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AES_DATA_IN_OUT | W | 0h | AES input data[127:96] / AES output data[127:96] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
AESTAGOUT_y is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESTAGOUT_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_AESTAGOUT_TABLE.
Return to the Summary Table.
AES Tag Out 0
The tag registers can be accessed via DMA or directly
with host reads.
These registers buffer the TAG from
the EIP-120t. The registers are shared with the intermediate authentication result
registers, but cannot be read until the processing is finished. While processing, a
read from these registers returns 0s. If an operation does not return a TAG, reading
from these registers returns an IV. If an operation returns a TAG plus an IV and
both need to be read by the host, the host must first read the TAG followed by the
IV. Reading these in reverse order will return the IV twice.
Offset = 570h + (y * 4h); where y = 0h to 3h
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AES_TAG | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AES_TAG | R | 0h | AES_TAG[31:0] Bits [31:0] of this register stores the authentication value for the combined and authentication only modes. For a host read operation, these registers contain the last 128-bit TAG output of the EIP-120t the TAG is available until the next context is written. This register will only contain valid data if the TAG is available and when the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for operations/modes that do not return a TAG, reads from this register return data from the IV register. |
HASHDATAIN1 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN1_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN1_TABLE.
Return to the Summary Table.
HASH Data Input 1
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[63:32] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN2 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN2_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN2_TABLE.
Return to the Summary Table.
HASH Data Input 2
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[95:64] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN3 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN3_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN3_TABLE.
Return to the Summary Table.
HASH Data Input 3
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[127:96] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when the rfd_in bit of the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN4 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN4_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN4_TABLE.
Return to the Summary Table.
HASH Data Input 4
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[159:128] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN5 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN5_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN5_TABLE.
Return to the Summary Table.
HASH Data Input 5
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[191:160] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN6 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN6_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN6_TABLE.
Return to the Summary Table.
HASH Data Input 6
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[223:192] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN7 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN7_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN7_TABLE.
Return to the Summary Table.
HASH Data Input 7
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[255:224] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN8 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN8_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN8_TABLE.
Return to the Summary Table.
HASH Data Input 8
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[287:256] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN9 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN9_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN9_TABLE.
Return to the Summary Table.
HASH Data Input 9
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[319:288] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN10 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN10_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN10_TABLE.
Return to the Summary Table.
HASH Data Input 10
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[351:320] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN11 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN11_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN11_TABLE.
Return to the Summary Table.
HASH Data Input 11
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[383:352] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN12 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN12_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN12_TABLE.
Return to the Summary Table.
HASH Data Input 12
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[415:384] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN13 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN13_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN13_TABLE.
Return to the Summary Table.
HASH Data Input 13
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[447:416] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN14 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN14_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN14_TABLE.
Return to the Summary Table.
HASH Data Input 14
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[479:448] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN15 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN15_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN15_TABLE.
Return to the Summary Table.
HASH Data Input 15
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[511:480] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN16 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN16_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN16_TABLE.
Return to the Summary Table.
HASH Data Input 16
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[543:512] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN17 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN17_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN17_TABLE.
Return to the Summary Table.
HASH Data Input 17
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[575:544] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN18 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN18_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN18_TABLE.
Return to the Summary Table.
HASH Data Input 18
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[607:576] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN19 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN19_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN19_TABLE.
Return to the Summary Table.
HASH Data Input 19
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[639:608] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN20 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN20_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN20_TABLE.
Return to the Summary Table.
HASH Data Input 20
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[671:640] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN21 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN21_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN21_TABLE.
Return to the Summary Table.
HASH Data Input 21
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[703:672] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN22 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN22_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN22_TABLE.
Return to the Summary Table.
HASH Data Input 22
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[735:704] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN23 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN23_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN23_TABLE.
Return to the Summary Table.
HASH Data Input 23
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[767:736] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN24 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN24_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN24_TABLE.
Return to the Summary Table.
HASH Data Input 24
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[799:768] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN25 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN25_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN25_TABLE.
Return to the Summary Table.
HASH Data Input 25
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[831:800] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN26 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN26_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN26_TABLE.
Return to the Summary Table.
HASH Data Input 26
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[863:832] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN27 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN27_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN27_TABLE.
Return to the Summary Table.
HASH Data Input 27
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[895:864] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN28 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN28_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN28_TABLE.
Return to the Summary Table.
HASH Data Input 28
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[923:896] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN29 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN29_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN29_TABLE.
Return to the Summary Table.
HASH Data Input 29
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[959:924] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN30 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN30_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN30_TABLE.
Return to the Summary Table.
HASH Data Input 30
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[991:960] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHDATAIN31 is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN31_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDATAIN31_TABLE.
Return to the Summary Table.
HASH Data Input 31
The data input registers should be used to provide
input data to the hash module through the slave interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DATA_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DATA_IN | W | 0h | HASH_DATA_IN[1023:992] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
HASHIOBUFCTRL is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHIOBUFCTRL_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHIOBUFCTRL_TABLE.
Return to the Summary Table.
HASH Input_Output Buffer Control
This register pair shares a single address location
and contains bits that control and monitor the data flow between the host and the
hash engine.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PAD_DMA_MESSAGE | GET_DIGEST | PAD_MESSAGE | RESERVED | RFD_IN | DATA_IN_AV | OUTPUT_FULL | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7 | PAD_DMA_MESSAGE | R/W | 0h | Note: This bit must only be used when data is supplied
through the DMA. It should not be used when data is supplied through
the slave interface. This bit indicates whether the hash engine has to pad the message, received through the DMA and finalize the hash. When set to 1, the hash engine pads the last block using the programmed length. After padding, the final hash result is calculated. When set to 0, the hash engine treats the last written block as block-size aligned and calculates the intermediate digest. This bit is automatically cleared when the last DMA data block is arrived in the hash engine. |
| 6 | GET_DIGEST | R/W | 0h | Note: The bit description below is only applicable
when data is sent through the slave interface. This bit must be set
to 0 when data is received through the DMA. This bit indicates whether the hash engine should provide the hash digest. When provided simultaneously with data_in_av, the hash digest is provided after processing the data that is currently in the HASHDATAINn register. When provided without data_in_av, the current internal digest buffer value is copied to the HASHDIGESTn registers. The host must write a 1 to this bit to make the intermediate hash digest available. Writing 0 to this bit has no effect. This bit is automatically cleared (that is, reads 0) when the hash engine has processed the contents of the HASHDATAINn register. In the period between this bit is set by the host and the actual HASHDATAINn processing, this bit reads 1. |
| 5 | PAD_MESSAGE | R/W | 0h | Note: The bit description below is only applicable
when data is sent through the slave interface. This bit must be set
to 0 when data is received through the DMA. This bit indicates that the HASHDATAINn registers hold the last data of the message and hash padding must be applied. The host must write this bit to 1 in order to indicate to the hash engine that the HASHDATAINn register currently holds the last data of the message. When pad_message is set to 1, the hash engine will add padding bits to the data currently in the HASHDATAINn register. When the last message block is smaller than 512 bits, the pad_message bit must be set to 1 together with the data_in_av bit. When the last message block is equal to 512 bits, pad_message may be set together with data_in_av. In this case the pad_message bit may also be set after the last data block has been written to the hash engine (so when the rfd_in bit has become 1 again after writing the last data block). Writing 0 to this bit has no effect. This bit is automatically cleared (i.e. reads 0) by the hash engine. This bit reads 1 between the time it was set by the host and the hash engine interpreted its value. |
| 4-3 | RESERVED | R/W | 0h | Write 0s and ignore on reading |
| 2 | RFD_IN | R/W | 1h | Note: The bit description below is only applicable
when data is sent through the slave interface. This bit can be
ignored when data is received through the DMA. Read-only status of the input buffer of the hash engine. When 1, the input buffer of the hash engine can accept new data the HASHDATAINn registers can safely be populated with new data. When 0, the input buffer of the hash engine is processing the data that is currently in HASHDATAINn writing new data to these registers is not allowed. |
| 1 | DATA_IN_AV | R/W | 0h | Note: The bit description below is only applicable
when data is sent through the slave interface. This bit must be set
to 0 when data is received through the DMA. This bit indicates that the HASHDATAINn registers contain new input data for processing. The host must write a 1 to this bit to start processing the data in HASHDATAINn the hash engine will process the new data as soon as it is ready for it (rfd_in bit is 1). Writing 0 to this bit has no effect. This bit is automatically cleared (i.e. reads as 0) when the hash engine starts processing the HASHDATAINn contents. This bit reads 1 between the time it was set by the host and the hash engine actually starts processing the input data block. |
| 0 | OUTPUT_FULL | R/W | 0h | Indicates that the output buffer registers
(HASHDIGESTn) are available for reading by the host. When this bit reads 0, the output buffer registers are released the hash engine is allowed to write new data to it. In this case, the registers should not be read by the host. When this bit reads 1, the hash engine has stored the result of the latest hash operation in the output buffer registers. As long as this bit reads 1, the host may read output buffer registers and the hash engine is prevented from writing new data to the output buffer. After retrieving the hash result data from the output buffer, the host must write a 1 to this bit to clear it. This makes the digest output buffer available for the hash engine to store new hash results. Writing 0 to this bit has no effect. Note: If this bit is asserted (1) no new operation should be started before the digest is retrieved from the hash engine and this bit is cleared (0). |
HASHMODE is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHMODE_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHMODE_TABLE.
Return to the Summary Table.
HASH Mode
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SHA384_MODE | SHA512_MODE | SHA224_MODE | SHA256_MODE | RESERVED | NEW_HASH | |
| W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-7 | RESERVED | W | 0h | Write 0s and ignore on reading |
| 6 | SHA384_MODE | W | 0h | The host must write this bit with 1 prior to processing a SHA 384 session. |
| 5 | SHA512_MODE | W | 0h | The host must write this bit with 1 prior to processing a SHA 512 session. |
| 4 | SHA224_MODE | W | 0h | The host must write this bit with 1 prior to processing a SHA 224 session. |
| 3 | SHA256_MODE | W | 0h | The host must write this bit with 1 prior to processing a SHA 256 session. |
| 2-1 | RESERVED | W | 0h | Write 0s and ignore on reading |
| 0 | NEW_HASH | W | 0h | When set to 1, it indicates that the hash engine must
start processing a new hash session. The [HASHDIGESTn.* ] registers
will automatically be loaded with the initial hash algorithm
constants of the selected hash algorithm. When this bit is 0 while the hash processing is started, the initial hash algorithm constants are not loaded in the HASHDIGESTn registers. The hash engine will start processing with the digest that is currently in its internal HASHDIGESTn registers. This bit is automatically cleared when hash processing is started. |
HASHINLENL is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHINLENL_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHINLENL_TABLE.
Return to the Summary Table.
HASH Input Length LSB
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LENGTH_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | LENGTH_IN | W | 0h | LENGTH_IN[31:0] Message length registers. The content of these registers is used by the hash engine during the message padding phase of the hash session. The data lines of this registers are directly connected to the interface of the hash engine. For a write operation by the host, these registers should be written with the message length in bits. Final hash operations: The total input data length must be programmed for new hash operations that require finalization (padding). The input data must be provided through the slave or DMA interface. Continued hash operations (finalized): For continued hash operations that require finalization, the total message length must be programmed, including the length of previously hashed data that corresponds to the written input digest. Non-final hash operations: For hash operations that do not require finalization (input data length is multiple of 512-bits which is SHA-256 data block size), the length field does not need to be programmed since not used by the operation. If the message length in bits is below (232-1), then only this register needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in this case. The host may write the length register at any time during the hash session when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written before the last data of the active hash session is written into the hash engine. host read operations from these register locations will return 0s. Note: When getting data from DMA, this register must be programmed before DMA is programmed to start. |
HASHINLENH is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHINLENH_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHINLENH_TABLE.
Return to the Summary Table.
HASH Input Length MSB
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LENGTH_IN | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | LENGTH_IN | W | 0h | LENGTH_IN[63:32] Message length registers. The content of these registers is used by the hash engine during the message padding phase of the hash session. The data lines of this registers are directly connected to the interface of the hash engine. For a write operation by the host, these registers should be written with the message length in bits. Final hash operations: The total input data length must be programmed for new hash operations that require finalization (padding). The input data must be provided through the slave or DMA interface. Continued hash operations (finalized): For continued hash operations that require finalization, the total message length must be programmed, including the length of previously hashed data that corresponds to the written input digest. Non-final hash operations: For hash operations that do not require finalization (input data length is multiple of 512-bits which is SHA-256 data block size), the length field does not need to be programmed since not used by the operation. If the message length in bits is below (232-1), then only HASHINLENL needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in this case. The host may write the length register at any time during the hash session when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written before the last data of the active hash session is written into the hash engine. host read operations from these register locations will return 0s. Note: When getting data from DMA, this register must be programmed before DMA is programmed to start. |
HASHDIGESTA is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTA_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTA_TABLE.
Return to the Summary Table.
HASH Digest A
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[31:0] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTB is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTB_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTB_TABLE.
Return to the Summary Table.
HASH Digest B
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[63:32] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTC is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTC_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTC_TABLE.
Return to the Summary Table.
HASH Digest C
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[95:64] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTD is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTD_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTD_TABLE.
Return to the Summary Table.
HASH Digest D
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[127:96] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTE is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTE_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTE_TABLE.
Return to the Summary Table.
HASH Digest E
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[159:128] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTF is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTF_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTF_TABLE.
Return to the Summary Table.
HASH Digest F
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[191:160] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTG is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTG_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTG_TABLE.
Return to the Summary Table.
HASH Digest G
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[223:192] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTH is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTH_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTH_TABLE.
Return to the Summary Table.
HASH Digest H
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[255:224] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTI is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTI_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTI_TABLE.
Return to the Summary Table.
HASH Digest I
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[287:256] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTJ is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTJ_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTJ_TABLE.
Return to the Summary Table.
HASH Digest J
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[319:288] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTK is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTK_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTK_TABLE.
Return to the Summary Table.
HASH Digest K
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[351:320] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTL is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTL_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTL_TABLE.
Return to the Summary Table.
HASH Digest L
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[383:352] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTM is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTM_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTM_TABLE.
Return to the Summary Table.
HASH Digest M
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[415:384] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTN is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTN_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTN_TABLE.
Return to the Summary Table.
HASH Digest N
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[447:416] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTO is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTO_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTO_TABLE.
Return to the Summary Table.
HASH Digest 0
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[479:448] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
HASHDIGESTP is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTP_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HASHDIGESTP_TABLE.
Return to the Summary Table.
HASH Digest P
The hash digest registers consist of eight 32-bit
registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the
output digest can be read from these registers. These registers can be written with
an intermediate hash result for continued hash operations.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH_DIGEST | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH_DIGEST | R/W | 0h | HASH_DIGEST[511:480] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
ALGSEL is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_ALGSEL_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_ALGSEL_TABLE.
Return to the Summary Table.
Algorithm Select
This algorithm selection register configures the
internal destination of the DMA controller.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TAG | RESERVED | ||||||
| R/W-0h | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | HASH_SHA_256 | AES | KEY_STORE | |||
| R-0h | R/W- | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 32 | HASH_SHA_512 | R/W | 0h | If set to one, selects the hash engine in 512B mode as
destination for the DMA The maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out through the DMA). |
| 31 | TAG | R/W | 0h | If this bit is cleared to 0, the DMA operation
involves only data. If this bit is set, the DMA operation includes a TAG (Authentication Result / Digest). For SHA-256 operation, a DMA must be set up for both input data and TAG. For any other selected module, setting this bit only allows a DMA that reads the TAG. No data allowed to be transferred to or from the selected module via the DMA. |
| 30-4 | RESERVED | R | 0h | Reserved |
| 3 | RESERVED | R/W | 0h | |
| 2 | HASH_SHA_256 | R/W | 0h | If set to one, selects the hash engine in 256B mode as
destination for the DMA The maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out through the DMA). |
| 1 | AES | R/W | 0h | If set to one, selects the AES engine as
source/destination for the DMA The read and write maximum transfer size to the DMA engine is set to 16 bytes. |
| 0 | KEY_STORE | R/W | 0h | If set to one, selects the Key Store as destination
for the DMA The maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16, 24 and 32 bytes are allowed) |
DMAPROTCTL is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMAPROTCTL_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_DMAPROTCTL_TABLE.
Return to the Summary Table.
DMA Protection Control
Master PROT privileged access enable
This register enables the second bit (bit [1]) of the
AHB HPROT bus of the AHB master interface when a read action of key(s) is performed
on the AHB master interface for writing keys into the store module.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PROT_EN | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | PROT_EN | R/W | 0h | Select AHB transfer protection control for DMA
transfers using the key store area as destination. 0 : transfers use 'USER' type access. 1 : transfers use 'PRIVILEGED' type access. |
SWRESET is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_SWRESET_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_SWRESET_TABLE.
Return to the Summary Table.
Software Reset
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SW_RESET | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | SW_RESET | R/W | 0h | If this bit is set to 1, the following modules are
reset: - Master control internal state is reset. That includes interrupt, error status register, and result available interrupt generation FSM. - Key store module state is reset. That includes clearing the written area flags therefore, the keys must be reloaded to the key store module. Writing 0 has no effect. The bit is self cleared after executing the reset. |
IRQTYPE is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQTYPE_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQTYPE_TABLE.
Return to the Summary Table.
Control Interrupt Configuration
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LEVEL | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | LEVEL | R/W | 0h | If this bit is 0, the interrupt output is a pulse. If this bit is set to 1, the interrupt is a level interrupt that must be cleared by writing the interrupt clear register. This bit is applicable for both interrupt output signals. |
IRQEN is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQEN_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQEN_TABLE.
Return to the Summary Table.
Control Interrupt Enable
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMA_IN_DONE | RESULT_AVAIL | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | DMA_IN_DONE | R/W | 0h | If this bit is set to 0, the DMA input done
(irq_dma_in_done) interrupt output is disabled and remains 0. If this bit is set to 1, the DMA input done interrupt output is enabled. |
| 0 | RESULT_AVAIL | R/W | 0h | If this bit is set to 0, the result available
(irq_result_av) interrupt output is disabled and remains 0. If this bit is set to 1, the result available interrupt output is enabled. |
IRQCLR is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQCLR_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQCLR_TABLE.
Return to the Summary Table.
Control Interrupt Clear
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DMA_BUS_ERR | KEY_ST_WR_ERR | KEY_ST_RD_ERR | RESERVED | ||||
| W-0h | W-0h | W-0h | R-0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMA_IN_DONE | RESULT_AVAIL | |||||
| R-0h | W-0h | W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | DMA_BUS_ERR | W | 0h | If 1 is written to this bit, the DMA bus error status
is cleared. Writing 0 has no effect. |
| 30 | KEY_ST_WR_ERR | W | 0h | If 1 is written to this bit, the key store write error
status is cleared. Writing 0 has no effect. |
| 29 | KEY_ST_RD_ERR | W | 0h | If 1 is written to this bit, the key store read error
status is cleared. Writing 0 has no effect. |
| 28-2 | RESERVED | R | 0h | Reserved |
| 1 | DMA_IN_DONE | W | 0h | If 1 is written to this bit, the DMA in done
(irq_dma_in_done) interrupt output is cleared. Writing 0 has no effect. Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE). |
| 0 | RESULT_AVAIL | W | 0h | If 1 is written to this bit, the result available
(irq_result_av) interrupt output is cleared. Writing 0 has no effect. Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE). |
IRQSET is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQSET_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQSET_TABLE.
Return to the Summary Table.
Control Interrupt Set
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMA_IN_DONE | RESULT_AVAIL | |||||
| R-0h | W-0h | W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | DMA_IN_DONE | W | 0h | If 1 is written to this bit, the DMA data in done
(irq_dma_in_done) interrupt output is set to one. Writing 0 has no effect. If the interrupt configuration register is programmed to pulse, clearing the DMA data in done (irq_dma_in_done) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (IRQCLR.DMA_IN_DONE). |
| 0 | RESULT_AVAIL | W | 0h | If 1 is written to this bit, the result available
(irq_result_av) interrupt output is set to one. Writing 0 has no effect. If the interrupt configuration register is programmed to pulse, clearing the result available (irq_result_av) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (IRQCLR.RESULT_AVAIL). |
IRQSTAT is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQSTAT_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_IRQSTAT_TABLE.
Return to the Summary Table.
Control Interrupt Status
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DMA_BUS_ERR | KEY_ST_WR_ERR | KEY_ST_RD_ERR | RESERVED | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMA_IN_DONE | RESULT_AVAIL | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | DMA_BUS_ERR | R | 0h | This bit is set when a DMA bus error is detected
during a DMA operation. The value of this register is held until it
is cleared through the IRQCLR.DMA_BUS_ERR Note: This error is asserted if an error is detected on the AHB master interface during a DMA operation. |
| 30 | KEY_ST_WR_ERR | R | 0h | This bit is set when a write error is detected during
the DMA write operation to the key store memory. The value of this
register is held until it is cleared through the
IRQCLR.KEY_ST_WR_ERR register. Note: This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected. |
| 29 | KEY_ST_RD_ERR | R | 0h | This bit is set when a read error is detected during
the read of a key from the key store, while copying it to the AES
core. The value of this register is held until it is cleared through
the IRQCLR.KEY_ST_RD_ERR register. Note: This error is asserted if a key location is selected in the key store that is not available. |
| 28-2 | RESERVED | R | 0h | Reserved |
| 1 | DMA_IN_DONE | R | 0h | This read only bit returns the actual DMA data in done (irq_data_in_done) interrupt status of the DMA data in done interrupt output pin (irq_data_in_done). |
| 0 | RESULT_AVAIL | R | 0h | This read only bit returns the actual result available (irq_result_av) interrupt status of the result available interrupt output pin (irq_result_av). |
HWVER is shown in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HWVER_FIGURE and described in #EIP120T1_HW2_0_EIP120T1_HW2_0_MMAP_EIP120T1_HW2_0_ALL_HWVER_TABLE.
Return to the Summary Table.
Hardware Version
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | HW_MAJOR_VER | HW_MINOR_VER | HW_PATCH_LVL | ||||||||||||
| R-0h | R-2h | R-0h | R-0h | ||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VER_NUM_COMPL | VER_NUM | ||||||||||||||
| R-87h | R-78h | ||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R | 0h | Reserved |
| 27-24 | HW_MAJOR_VER | R | 2h | Major version number |
| 23-20 | HW_MINOR_VER | R | 0h | Minor version number |
| 19-16 | HW_PATCH_LVL | R | 0h | Patch level Starts at 0 at first delivery of this version |
| 15-8 | VER_NUM_COMPL | R | 87h | These bits simply contain the complement of bits [7:0] (0x87), used by a driver to ascertain that the EIP-120t register is indeed read. |
| 7-0 | VER_NUM | R | 78h | These bits encode the EIP number for the EIP-120t, this field contains the value 120 (decimal) or 0x78. |