SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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11. 993
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997

14.10.1 AON_IOC Registers

#AON_IOC_AON_IOC_REGMAP_TABLE_1 lists the memory-mapped registers for the AON_IOC registers. All register offset addresses not listed in #AON_IOC_AON_IOC_REGMAP_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 14-4 AON_IOC Registers

Offset	Acronym	Register Name	Section
0h	IOSTRMIN	Internal	#AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMIN
4h	IOSTRMED	Internal	#AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMED
8h	IOSTRMAX	Internal	#AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMAX
10h	CLK32KCTL	SCLK_LF External Output Control	#AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_CLK32KCTL
14h	TCKCTL	TCK IO Pin Control	#AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_TCKCTL

Complex bit access types are encoded to fit into small table cells. #AON_IOC_AON_IOC_REGMAP_LEGEND shows the codes that are used for access types in this section.

Table 14-5 AON_IOC Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

14.10.1.1 IOSTRMIN Register (Offset = 0h) [Reset = 00000003h]

IOSTRMIN is shown in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMIN_FIGURE and described in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMIN_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 14-3 IOSTRMIN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													GRAY_CODE
R-0h													R/W-3h

Table 14-6 IOSTRMIN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	GRAY_CODE	R/W	3h	Internal. Only to be used through TI provided API.

14.10.1.2 IOSTRMED Register (Offset = 4h) [Reset = 00000006h]

IOSTRMED is shown in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMED_FIGURE and described in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMED_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 14-4 IOSTRMED Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													GRAY_CODE
R-0h													R/W-6h

Table 14-7 IOSTRMED Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	GRAY_CODE	R/W	6h	Internal. Only to be used through TI provided API.

14.10.1.3 IOSTRMAX Register (Offset = 8h) [Reset = 00000005h]

IOSTRMAX is shown in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMAX_FIGURE and described in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_IOSTRMAX_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 14-5 IOSTRMAX Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													GRAY_CODE
R-0h													R/W-5h

Table 14-8 IOSTRMAX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	GRAY_CODE	R/W	5h	Internal. Only to be used through TI provided API.

14.10.1.4 CLK32KCTL Register (Offset = 10h) [Reset = 00000001h]

CLK32KCTL is shown in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_CLK32KCTL_FIGURE and described in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_CLK32KCTL_TABLE.

Return to the Summary Table.

SCLK_LF External Output Control

Figure 14-6 CLK32KCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							OE_N
R-0h							R/W-1h

Table 14-9 CLK32KCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	OE_N	R/W	1h	0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (for example IOC:IOCFG0.PORT_ID) set to AON_CLK32K. 1: Output enable not active

14.10.1.5 TCKCTL Register (Offset = 14h) [Reset = 00000001h]

TCKCTL is shown in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_TCKCTL_FIGURE and described in #AON_IOC_AON_IOC_REGMAP_AON_IOC_ALL_TCKCTL_TABLE.

Return to the Summary Table.

TCK IO Pin Control

Figure 14-7 TCKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															EN
R-0h															R/W-1h

Table 14-10 TCKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EN	R/W	1h	0: Input driver for TCK disabled. 1: Input driver for TCK enabled.