SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_TABLE_1 lists the memory-mapped registers for the AON_PMCTL registers. All register offset addresses not listed in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C | Write 1 to clear |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
AUXSCECLK is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_AUXSCECLK_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_AUXSCECLK_TABLE.
Return to the Summary Table.
AUX SCE Clock Management
This register contains bitfields that are relevant for setting up the clock to the AUX domain.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PD_SRC | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SRC | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R | 0h | Reserved |
| 8 | PD_SRC | R/W | 0h | Selects the clock source for the AUX domain when AUX is in powerdown mode. Note: Switching the clock source is guaranteed to be glitch-free 0h = No clock 1h = LF clock (SCLK_LF ) |
| 7-1 | RESERVED | R | 0h | Reserved |
| 0 | SRC | R/W | 0h | Selects the clock source for the AUX domain when AUX is in active mode. Note: Switching the clock source is guaranteed to be glitch-free 0h = HF Clock divided by 2 (SCLK_HFDIV2) 1h = MF Clock (SCLK_MF) |
RAMCFG is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RAMCFG_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RAMCFG_TABLE.
Return to the Summary Table.
RAM Configuration
This register contains power management related configuration for the SRAM in the MCU and AUX domain.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | AUX_SRAM_PWR_OFF | AUX_SRAM_RET_EN | |||||
| R-0h | R/W-0h | R/W-1h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUS_SRAM_RET_EN | ||||||
| R-0h | R/W-Fh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R | 0h | Reserved |
| 17 | AUX_SRAM_PWR_OFF | R/W | 0h | Internal. Only to be used through TI provided API. |
| 16 | AUX_SRAM_RET_EN | R/W | 1h | Internal. Only to be used through TI provided API. |
| 15-4 | RESERVED | R | 0h | Reserved |
| 3-0 | BUS_SRAM_RET_EN | R/W | Fh | MCU SRAM is partitioned into 5 banks . This register controls which of the banks that has retention during MCU Bus domain power off
0h = Retention is disabled 3h = Retention on for SRAM:BANK0, SRAM:BANK1 and SRAM:BANK2 7h = Retention on for SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2 and SRAM:BANK3 Fh = Retention on for all banks SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4 |
PWRCTL is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_PWRCTL_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_PWRCTL_TABLE.
Return to the Summary Table.
Power Management Control
This register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DCDC_ACTIVE | EXT_REG_MODE | DCDC_EN | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R | 0h | Reserved |
| 2 | DCDC_ACTIVE | R/W | 0h | Select to use DCDC regulator for VDDR in active mode 0: Use GLDO for regulation of VDDR in active mode. 1: Use DCDC for regulation of VDDR in active mode. DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active mode |
| 1 | EXT_REG_MODE | R | 0h | Status of source for VDDRsupply: 0: DCDC or GLDO are generating VDDR 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR |
| 0 | DCDC_EN | R/W | 0h | Select to use DCDC regulator during recharge of VDDR 0: Use GLDO for recharge of VDDR 1: Use DCDC for recharge of VDDR Note: This bitfield should be set to the same as DCDC_ACTIVE |
PWRSTAT is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_PWRSTAT_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_PWRSTAT_TABLE.
Return to the Summary Table.
AON Power and Reset Status
This register is used to monitor various power management related signals in AON. All other signals than JTAG_PD_ON, AUX_BUS_RESET_DONE, and AUX_RESET_DONE are for test, calibration and debug purpose only.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | JTAG_PD_ON | AUX_BUS_RESET_DONE | AUX_RESET_DONE | ||||
| R-0h | R-0h | R-1h | R-1h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R | 0h | Reserved |
| 2 | JTAG_PD_ON | R | 0h | Indicates JTAG power state: 0: JTAG is powered off 1: JTAG is powered on |
| 1 | AUX_BUS_RESET_DONE | R | 1h | Indicates Reset Done from AUX Bus: 0: AUX Bus is being reset 1: AUX Bus reset is released |
| 0 | AUX_RESET_DONE | R | 1h | Indicates Reset Done from AUX: 0: AUX is being reset 1: AUX reset is released |
SHUTDOWN is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_SHUTDOWN_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_SHUTDOWN_TABLE.
Return to the Summary Table.
Shutdown Control
This register contains bitfields required for entering shutdown mode
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EN | ||||||||||||||
| R-0h | R/W-0h | ||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | EN | R/W | 0h | Shutdown control. 0: Do not write 0 to this bit. 1: Immediately start the process to enter shutdown mode |
RECHARGECFG is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RECHARGECFG_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RECHARGECFG_TABLE.
Return to the Summary Table.
Recharge Controller Configuration
This register sets all relevant parameters for controlling the recharge algorithm.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MODE | RESERVED | C2 | C1 | ||||||||||||
| R/W-3h | R-0h | R/W-0h | R/W-0h | ||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAX_PER_M | MAX_PER_E | PER_M | PER_E | ||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | MODE | R/W | 3h | Selects recharge algorithm for VDDR when the system is running on the uLDO
0h = Recharge disabled 1h = Static timer 2h = Adaptive timer 3h = External recharge comparator. |
| 29-24 | RESERVED | R | 0h | Reserved |
| 23-20 | C2 | R/W | 0h | Internal. Only to be used through TI provided API. |
| 19-16 | C1 | R/W | 0h | Internal. Only to be used through TI provided API. |
| 15-11 | MAX_PER_M | R/W | 0h | Internal. Only to be used through TI provided API. |
| 10-8 | MAX_PER_E | R/W | 0h | Internal. Only to be used through TI provided API. |
| 7-3 | PER_M | R/W | 0h | Internal. Only to be used through TI provided API. |
| 2-0 | PER_E | R/W | 0h | Internal. Only to be used through TI provided API. |
RECHARGESTAT is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RECHARGESTAT_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RECHARGESTAT_TABLE.
Return to the Summary Table.
Recharge Controller Status
This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | VDDR_SMPLS | ||||||||||||||
| R-0h | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAX_USED_PER | |||||||||||||||
| R/W-0h | |||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R | 0h | Reserved |
| 19-16 | VDDR_SMPLS | R | 0h | The last 4 VDDR samples. For each bit: 0: VDDR was below VDDR_OK threshold when recharge started 1: VDDR was above VDDR_OK threshold when recharge started The register is updated prior to every recharge period with a shift left, and bit 0 is updated with the last VDDR sample. |
| 15-0 | MAX_USED_PER | R/W | 0h | Shows the maximum number of 32kHz periods that have separated two recharge cycles and VDDR still was above VDDR_OK threshold when the latter recharge started. This register can be used as an indication of the leakage current during standby. This bitfield is cleared to 0 when writing this register. |
OSCCFG is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_OSCCFG_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_OSCCFG_TABLE.
Return to the Summary Table.
Oscillator Configuration
This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PER_M | PER_E | |||||||||||||
| R-0h | R/W-0h | R/W-0h | |||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-3 | PER_M | R/W | 0h | Internal. Only to be used through TI provided API. |
| 2-0 | PER_E | R/W | 0h | Internal. Only to be used through TI provided API. |
RESETCTL is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RESETCTL_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RESETCTL_TABLE.
Return to the Summary Table.
Reset Management
This register contains bitfields related to system reset such as reset source and reset request and control of brown out resets.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SYSRESET | RESERVED | BOOT_DET_1_CLR | BOOT_DET_0_CLR | ||||
| W-0h | R-0h | W-0h | W-0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | BOOT_DET_1_SET | BOOT_DET_0_SET | |||||
| R-0h | W-0h | W-0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| WU_FROM_SD | GPIO_WU_FROM_SD | BOOT_DET_1 | BOOT_DET_0 | RESERVED | VDDS_LOSS_EN | ||
| R-0h | R-0h | R-0h | R-0h | R-0h | R/W-1h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VDDR_LOSS_EN | VDD_LOSS_EN | CLK_LOSS_EN | MCU_WARM_RESET | RESET_SRC | RESERVED | ||
| R/W-1h | R/W-1h | R/W-0h | R/W1C-0h | R-0h | R-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | SYSRESET | W | 0h | Cold reset register. Writing 1 to this bitfield will reset the entire chip and cause boot code to run again. 0: No effect 1: Generate system reset. Appears as SYSRESET in RESET_SRC |
| 30-26 | RESERVED | R | 0h | Reserved |
| 25 | BOOT_DET_1_CLR | W | 0h | Internal. Only to be used through TI provided API. |
| 24 | BOOT_DET_0_CLR | W | 0h | Internal. Only to be used through TI provided API. |
| 23-18 | RESERVED | R | 0h | Reserved |
| 17 | BOOT_DET_1_SET | W | 0h | Internal. Only to be used through TI provided API. |
| 16 | BOOT_DET_0_SET | W | 0h | Internal. Only to be used through TI provided API. |
| 15 | WU_FROM_SD | R | 0h | A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low) Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources. 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC 1: A wakeup has occurred from SHUTDOWN Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. |
| 14 | GPIO_WU_FROM_SD | R | 0h | A wakeup from SHUTDOWN on an IO event has occurred Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources. 0: The wakeup did not occur from SHUTDOWN on an IO event 1: A wakeup from SHUTDOWN occurred from an IO event The case where WU_FROM_SD is asserted but this bitfield is not asserted will only occur in a debug session. The boot code will not proceed with wakeup from SHUTDOWN procedure until this bitfield is asserted as well. Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. |
| 13 | BOOT_DET_1 | R | 0h | Internal. Only to be used through TI provided API. |
| 12 | BOOT_DET_0 | R | 0h | Internal. Only to be used through TI provided API. |
| 11-9 | RESERVED | R | 0h | Reserved |
| 8 | VDDS_LOSS_EN | R/W | 1h | Controls reset generation in case VDDS is lost 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 1: Brown out detect of VDDS generates system reset |
| 7 | VDDR_LOSS_EN | R/W | 1h | Controls reset generation in case VDDR is lost 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 1: Brown out detect of VDDR generates system reset |
| 6 | VDD_LOSS_EN | R/W | 1h | Controls reset generation in case VDD is lost 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 1: Brown out detect of VDD generates system reset |
| 5 | CLK_LOSS_EN | R/W | 0h | Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] 0: Clock loss is ignored 1: Clock loss generates system reset Note: Clock loss reset generation must be disabled when changing clock source for SCLK_LF. Failure to do so may result in a spurious system reset. Clock loss reset generation is controlled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] |
| 4 | MCU_WARM_RESET | R/W1C | 0h | Internal. Only to be used through TI provided API. |
| 3-1 | RESET_SRC | R | 0h | Shows the root cause of the last system reset. More than the reported reset source can have been active during the last system reset but only the root cause is reported. The capture feature is not rearmed until all off the possible reset sources have been released and the result has been copied to AON_PMCTL. During the copy and rearm process it is one 2MHz period in which and eventual new system reset will be reported as Power on reset regardless of the root cause. 0h = Power on reset 1h = Reset pin 2h = Brown out detect on VDDS 4h = Brown out detect on VDDR 5h = SCLK_LF, SCLK_MF or SCLK_HF clock loss detect 6h = Software reset via SYSRESET or hardware power management timeout detection. 7h = Software reset via PRCM warm reset request |
| 0 | RESERVED | R | 0h | Reserved |
SLEEPCTL is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_SLEEPCTL_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_SLEEPCTL_TABLE.
Return to the Summary Table.
Sleep Control
This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | IO_PAD_SLEEP_DIS | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | IO_PAD_SLEEP_DIS | R/W | 0h | Controls the I/O pad sleep mode. The boot code will set this bitfield automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set). 0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations are latched. Inputs are transparent if pad is configured as input before IO_PAD_SLEEP_DIS is set to 1 1: I/O pad sleep mode is disabled Application software must reconfigure the state for all IO's before setting this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins. |
JTAGCFG is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_JTAGCFG_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_JTAGCFG_TABLE.
Return to the Summary Table.
JTAG Configuration
This register contains control for configuration of the JTAG domain. This includes permissions for each TAP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | JTAG_PD_FORCE_ON | ||||||
| R-0h | R/W-1h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R | 0h | Reserved |
| 8 | JTAG_PD_FORCE_ON | R/W | 1h | Controls JTAG Power domain power state: 0: Controlled exclusively by debug subsystem. (JTAG Power domain will be powered off unless a debugger is attached) 1: JTAG Power Domain is forced on, independent of debug subsystem. Note: The reset value causes JTAG Power domain to be powered on by default. Software must clear this bit to turn off the JTAG Power domain |
| 7-0 | RESERVED | R | 0h | Reserved |
JTAGUSERCODE is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_JTAGUSERCODE_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_JTAGUSERCODE_TABLE.
Return to the Summary Table.
JTAG USERCODE
Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| USER_CODE | |||||||||||||||||||||||||||||||
| R/W-0B99A02Fh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | USER_CODE | R/W | 0B99A02Fh | 32-bit JTAG USERCODE register feeding main JTAG TAP Note: This field can be locked by LOCKCFG.LOCK |