SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
7.1 Top-Level Debug System
In the CC13x2x7 and CC26x2x7 device platform, the debug subsystem implements two IEEE standards for debug and test purposes:
- IEEE standard 1149.1: Standard Test Access Port and Boundary Scan Architecture Test Access Port (TAP) [JTAG 1]. This standard is known by the acronym JTAG.
- Class 4 IEEE 1149.7: Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary-scan Architecture [JTAG 2]. This is known by acronym cJTAG (compact JTAG). This standard serializes the IEEE 1149.1 transactions using a variety of compression formats to reduce the number of pins needed to implement a JTAG debug port.
The debug subsystem also implements a firewall for unauthorized access to debug/test ports. Figure 7-1 shows a block diagram of debug subsystem.
Figure 7-1 Top-Level Debug SystemThe IEEE 1149.1 TAP uses the following signals to support the operation:
- TCK (Test Clock): This signal synchronizes the internal state machine operations.
- TMS (Test Mode Select): This signal is sampled at the rising edge of TCK to determine the next state.
- TDI (Test Data In): This signal represents the data shifted into the test or programming logic of the device. TDI is sampled at the rising edge of TCK when the internal state machine is in the correct state.
- TDO (Test Data Out): This signal represents the data shifted out of the test or programming logic of the device and is valid on the falling edge of TCK when the internal state machine is in the correct state.
There is no dedicated I/O pin for TRST. The debug subsystem is reset with system-wide resets and power-on reset.
The TAP controller, a state machine whose transitions are controlled by the TMS signal, controls the behavior of the JTAG system. Figure 7-2 shows the state-transition diagram for JTAG.
Figure 7-2 JTAG State MachineEvery state has two exits, so all transitions can be controlled by the single TMS signal sampled on TCK. The two main paths allow for setting or retrieving information from either a data register (DR) or the instruction register (IR) of the device. The data register depends on the value loaded into the instruction register.