SWCU192 November   2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

 

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    9.     402
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  14.   404
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    4.     448
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    5.     454
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  16.   456
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    3.     459
      1.      460
      2.      461
        1.       462
        2.       463
        3.       464
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        5.       466
      3.      467
      4.      468
    4.     469
      1.      470
      2.      471
      3.      472
      4.      473
      5.      474
    5.     475
      1.      476
  17.   477
    1.     478
    2.     479
      1.      480
      2.      481
      3.      482
        1.       483
      4.      484
    3.     485
      1.      486
      2.      487
      3.      488
    4.     489
      1.      490
  18.   491
    1.     492
    2.     493
    3.     494
    4.     495
      1.      496
  19.   497
    1.     498
    2.     499
    3.     500
    4.     501
    5.     502
      1.      503
      2.      504
      3.      505
    6.     506
      1.      507
        1.       508
        2.       509
        3.       510
          1.        511
          2.        512
    7.     513
      1.      514
  20.   515
    1.     516
      1.      517
    2.     518
      1.      519
        1.       520
      2.      521
        1.       522
        2.       523
      3.      524
      4.      525
    3.     526
      1.      527
        1.       528
        2.       529
        3.       530
        4.       531
      2.      532
        1.       533
          1.        534
        2.       535
          1.        536
          2.        537
        3.       538
          1.        539
        4.       540
          1.        541
          2.        542
          3.        543
        5.       544
        6.       545
        7.       546
        8.       547
        9.       548
        10.       549
    4.     550
      1.      551
        1.       552
      2.      553
        1.       554
        2.       555
          1.        556
          2.        557
          3.        558
          4.        559
          5.        560
      3.      561
        1.       562
        2.       563
        3.       564
      4.      565
        1.       566
        2.       567
          1.        568
          2.        569
          3.        570
      5.      571
        1.       572
        2.       573
          1.        574
          2.        575
          3.        576
          4.        577
            1.         578
            2.         579
          5.        580
          6.        581
        3.       582
          1.        583
          2.        584
          3.        585
            1.         586
            2.         587
            3.         588
            4.         589
          4.        590
      6.      591
        1.       592
        2.       593
      7.      594
        1.       595
        2.       596
          1.        597
          2.        598
          3.        599
          4.        600
          5.        601
            1.         602
              1.          603
            2.         604
              1.          605
            3.         606
              1.          607
          6.        608
    5.     609
      1.      610
        1.       611
        2.       612
      2.      613
        1.       614
        2.       615
          1.        616
          2.        617
          3.        618
          4.        619
          5.        620
          6.        621
          7.        622
          8.        623
      3.      624
        1.       625
        2.       626
          1.        627
          2.        628
          3.        629
          4.        630
      4.      631
        1.       632
        2.       633
          1.        634
          2.        635
          3.        636
            1.         637
            2.         638
      5.      639
        1.       640
        2.       641
          1.        642
          2.        643
          3.        644
            1.         645
            2.         646
            3.         647
          4.        648
            1.         649
            2.         650
            3.         651
            4.         652
          5.        653
          6.        654
      6.      655
        1.       656
        2.       657
          1.        658
          2.        659
          3.        660
          4.        661
          5.        662
    6.     663
      1.      664
        1.       665
        2.       666
          1.        667
            1.         668
            2.         669
      2.      670
      3.      671
      4.      672
      5.      673
      6.      674
      7.      675
    7.     676
    8.     677
      1.      678
      2.      679
      3.      680
      4.      681
      5.      682
      6.      683
      7.      684
      8.      685
      9.      686
      10.      687
      11.      688
      12.      689
  21.   690
    1.     691
    2.     692
    3.     693
      1.      694
  22.   695
    1.     696
    2.     697
    3.     698
    4.     699
      1.      700
      2.      701
      3.      702
      4.      703
        1.       704
        2.       705
          1.        706
          2.        707
      5.      708
      6.      709
      7.      710
    5.     711
    6.     712
    7.     713
      1.      714
  23.   715
    1.     716
    2.     717
    3.     718
    4.     719
      1.      720
      2.      721
        1.       722
        2.       723
      3.      724
      4.      725
        1.       726
        2.       727
          1.        728
          2.        729
        3.       730
        4.       731
        5.       732
        6.       733
        7.       734
    5.     735
    6.     736
    7.     737
      1.      738
  24.   739
    1.     740
    2.     741
    3.     742
      1.      743
        1.       744
        2.       745
        3.       746
        4.       747
        5.       748
      2.      749
        1.       750
      3.      751
        1.       752
        2.       753
      4.      754
      5.      755
        1.       756
        2.       757
    4.     758
    5.     759
      1.      760
  25.   761
    1.     762
    2.     763
    3.     764
    4.     765
      1.      766
        1.       767
      2.      768
      3.      769
      4.      770
        1.       771
      5.      772
        1.       773
      6.      774
        1.       775
      7.      776
        1.       777
      8.      778
        1.       779
        2.       780
    5.     781
      1.      782
      2.      783
      3.      784
      4.      785
        1.       786
        2.       787
        3.       788
    6.     789
      1.      790
      2.      791
      3.      792
      4.      793
    7.     794
    8.     795
      1.      796
      2.      797
    9.     798
      1.      799
  26.   800
    1.     801
      1.      802
    2.     803
      1.      804
      2.      805
      3.      806
        1.       807
        2.       808
        3.       809
      4.      810
        1.       811
        2.       812
        3.       813
    3.     814
      1.      815
      2.      816
        1.       817
        2.       818
        3.       819
        4.       820
        5.       821
          1.        822
          2.        823
          3.        824
        6.       825
          1.        826
        7.       827
          1.        828
          2.        829
          3.        830
          4.        831
        8.       832
      3.      833
        1.       834
          1.        835
          2.        836
          3.        837
          4.        838
          5.        839
          6.        840
          7.        841
          8.        842
          9.        843
          10.        844
          11.        845
          12.        846
          13.        847
          14.        848
        2.       849
          1.        850
          2.        851
          3.        852
          4.        853
          5.        854
          6.        855
          7.        856
          8.        857
          9.        858
          10.        859
          11.        860
          12.        861
          13.        862
          14.        863
          15.        864
          16.        865
          17.        866
          18.        867
          19.        868
          20.        869
      4.      870
        1.       871
        2.       872
        3.       873
        4.       874
        5.       875
    4.     876
      1.      877
        1.       878
        2.       879
        3.       880
        4.       881
        5.       882
      2.      883
        1.       884
        2.       885
    5.     886
      1.      887
        1.       888
        2.       889
        3.       890
        4.       891
      2.      892
      3.      893
        1.       894
        2.       895
      4.      896
        1.       897
          1.        898
            1.         899
            2.         900
          2.        901
          3.        902
          4.        903
          5.        904
        2.       905
        3.       906
        4.       907
        5.       908
        6.       909
      5.      910
        1.       911
        2.       912
        3.       913
        4.       914
        5.       915
        6.       916
    6.     917
      1.      918
        1.       919
          1.        920
        2.       921
        3.       922
        4.       923
      2.      924
    7.     925
      1.      926
      2.      927
    8.     928
      1.      929
      2.      930
      3.      931
      4.      932
      5.      933
      6.      934
      7.      935
      8.      936
        1.       937
        2.       938
        3.       939
        4.       940
      9.      941
        1.       942
        2.       943
        3.       944
      10.      945
        1.       946
        2.       947
        3.       948
        4.       949
        5.       950
      11.      951
        1.       952
        2.       953
        3.       954
        4.       955
        5.       956
      12.      957
      13.      958
      14.      959
      15.      960
      16.      961
      17.      962
    9.     963
      1.      964
    10.     965
      1.      966
      2.      967
        1.       968
          1.        969
        2.       970
        3.       971
      3.      972
      4.      973
        1.       974
        2.       975
      5.      976
        1.       977
        2.       978
          1.        979
        3.       980
          1.        981
          2.        982
        4.       983
          1.        984
          2.        985
        5.       986
          1.        987
          2.        988
          3.        989
      6.      990
        1.       991
        2.       992
    11.     993
      1.      994
      2.      995
      3.      996
  27.   997

20.8.2 AUX_AIODIO Registers

#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_TABLE_1 lists the memory-mapped registers for the AUX_AIODIO registers. All register offset addresses not listed in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 20-54 AUX_AIODIO Registers
OffsetAcronymRegister NameSection
0hIOMODEInput Output Mode#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODE
4hGPIODIEGeneral Purpose Input Output Digital Input Enable#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODIE
8hIOPOEInput Output Peripheral Output Enable#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOPOE
ChGPIODOUTGeneral Purpose Input Output Data Out#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUT
10hGPIODINGeneral Purpose Input Output Data In#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODIN
14hGPIODOUTSETGeneral Purpose Input Output Data Out Set#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTSET
18hGPIODOUTCLRGeneral Purpose Input Output Data Out Clear#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTCLR
1ChGPIODOUTTGLGeneral Purpose Input Output Data Out Toggle#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTTGL
20hIO0PSELInput Output 0 Peripheral Select#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO0PSEL
24hIO1PSELInput Output 1 Peripheral Select#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO1PSEL
28hIO2PSELInput Output 2 Peripheral Select#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO2PSEL
2ChIO3PSELInput Output 3 Peripheral Select#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO3PSEL
30hIO4PSELInput Output 4 Peripheral Select#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO4PSEL
34hIO5PSELInput Output 5 Peripheral Select#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO5PSEL
38hIO6PSELInput Output 6 Peripheral Select#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO6PSEL
3ChIO7PSELInput Output 7 Peripheral Select#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO7PSEL
40hIOMODELInput Output Mode Low#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODEL
44hIOMODEHInput Output Mode High#AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODEH

Complex bit access types are encoded to fit into small table cells. #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_LEGEND shows the codes that are used for access types in this section.

Table 20-55 AUX_AIODIO Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

20.8.2.1 IOMODE Register (Offset = 0h) [Reset = 00000000h]

IOMODE is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODE_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODE_TABLE.

Return to the Summary Table.

Input Output Mode
This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-48 IOMODE Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
IO7IO6IO5IO4IO3IO2IO1IO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-56 IOMODE Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14IO7R/W0hSelects mode for AUXIO[8i+7].

0h = Output Mode:
When IOPOE bit 7 is 0: GPIODOUT bit 7 drives AUXIO[8i+7].
When IOPOE bit 7 is 1: The signal selected by IO7PSEL.SRC drives AUXIO[8i+7].

1h = Input Mode:
When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer.
When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input.

2h = Open-Drain Mode:
When IOPOE bit 7 is 0:
- If GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low.
- If GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 7 is 1:
- If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low.
- If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

3h = Open-Source Mode:
When IOPOE bit 7 is 0:
- If GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high.
When IOPOE bit 7 is 1:
- If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high.

13-12IO6R/W0hSelects mode for AUXIO[8i+6].

0h = Output Mode:
When IOPOE bit 6 is 0: GPIODOUT bit 6 drives AUXIO[8i+6].
When IOPOE bit 6 is 1: The signal selected by IO6PSEL.SRC drives AUXIO[8i+6].

1h = Input Mode:
When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer.
When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input.

2h = Open-Drain Mode:
When IOPOE bit 6 is 0:
- If GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low.
- If GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 6 is 1:
- If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low.
- If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

3h = Open-Source Mode:
When IOPOE bit 6 is 0:
- If GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high.
When IOPOE bit 6 is 1:
- If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high.

11-10IO5R/W0hSelects mode for AUXIO[8i+5].

0h = Output Mode:
When IOPOE bit 5 is 0: GPIODOUT bit 5 drives AUXIO[8i+5].
When IOPOE bit 5 is 1: The signal selected by IO5PSEL.SRC drives AUXIO[8i+5].

1h = Input Mode:
When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer.
When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input.

2h = Open-Drain Mode:
When IOPOE bit 5 is 0:
- If GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low.
- If GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 5 is 1:
- If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low.
- If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

3h = Open-Source Mode:
When IOPOE bit 5 is 0:
- If GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high.
When IOPOE bit 5 is 1:
- If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high.

9-8IO4R/W0hSelects mode for AUXIO[8i+4].

0h = Output Mode:
When IOPOE bit 4 is 0: GPIODOUT bit 4 drives AUXIO[8i+4].
When IOPOE bit 4 is 1: The signal selected by IO4PSEL.SRC drives AUXIO[8i+4].

1h = Input Mode:
When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer.
When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input.

2h = Open-Drain Mode:
When IOPOE bit 4 is 0:
- If GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low.
- If GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 4 is 1:
- If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low.
- If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

3h = Open-Source Mode:
When IOPOE bit 4 is 0:
- If GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high.
When IOPOE bit 4 is 1:
- If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high.

7-6IO3R/W0hSelects mode for AUXIO[8i+3].

0h = Output Mode:
When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3].
When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3].

1h = Input Mode:
When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer.
When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input.

2h = Open-Drain Mode:
When IOPOE bit 3 is 0:
- If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low.
- If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 3 is 1:
- If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low.
- If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

3h = Open-Source Mode:
When IOPOE bit 3 is 0:
- If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high.
When IOPOE bit 3 is 1:
- If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high.

5-4IO2R/W0hSelect mode for AUXIO[8i+2].

0h = Output Mode:
When IOPOE bit 2 is 0: GPIODOUT bit 2 drives AUXIO[8i+2].
When IOPOE bit 2 is 1: The signal selected by IO2PSEL.SRC drives AUXIO[8i+2].

1h = Input Mode:
When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer.
When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input.

2h = Open-Drain Mode:
When IOPOE bit 2 is 0:
- If GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low.
- If GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 2 is 1:
- If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low.
- If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

3h = Open-Source Mode:
When IOPOE bit 2 is 0:
- If GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high.
When IOPOE bit 2 is 1:
- If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high.

3-2IO1R/W0hSelect mode for AUXIO[8i+1].

0h = Output Mode:
When IOPOE bit 1 is 0: GPIODOUT bit 1 drives AUXIO[8i+1].
When IOPOE bit 1 is 1: The signal selected by IO1PSEL.SRC drives AUXIO[8i+1].

1h = Input Mode:
When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer.
When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input.

2h = Open-Drain Mode:
When IOPOE bit 1 is 0:
- If GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low.
- If GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 1 is 1:
- If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low.
- If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

3h = Open-Source Mode:
When IOPOE bit 1 is 0:
- If GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high.
When IOPOE bit 1 is 1:
- If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high.

1-0IO0R/W0hSelect mode for AUXIO[8i+0].

0h = Output Mode:
When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0].
When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0].

1h = Input Mode:
When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer.
When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input.

2h = Open-Drain Mode:
When IOPOE bit 0 is 0:
- If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low.
- If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 0 is 1:
- If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low.
- If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

3h = Open-Source Mode:
When IOPOE bit 0 is 0:
- If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high.
When IOPOE bit 0 is 1:
- If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high.

20.8.2.2 GPIODIE Register (Offset = 4h) [Reset = 00000000h]

GPIODIE is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODIE_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODIE_TABLE.

Return to the Summary Table.

General Purpose Input Output Digital Input Enable
This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-49 GPIODIE Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-57 GPIODIE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n].
Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n].
You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN.
You must disable the digital input buffer for analog input or pins that float to avoid current leakage.

20.8.2.3 IOPOE Register (Offset = 8h) [Reset = 00000000h]

IOPOE is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOPOE_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOPOE_TABLE.

Return to the Summary Table.

Input Output Peripheral Output Enable
This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-50 IOPOE Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-58 IOPOE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*].
Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT.

20.8.2.4 GPIODOUT Register (Offset = Ch) [Reset = 00000000h]

GPIODOUT is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUT_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUT_TABLE.

Return to the Summary Table.

General Purpose Input Output Data Out
The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-51 GPIODOUT Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-59 GPIODOUT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to set AUXIO[8i+n].
Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].
You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n].

20.8.2.5 GPIODIN Register (Offset = 10h) [Reset = 00000000h]

GPIODIN is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODIN_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODIN_TABLE.

Return to the Summary Table.

General Purpose Input Output Data In
This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth

Figure 20-52 GPIODIN Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR-0h
Table 20-60 GPIODIN Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R0hBit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0.

20.8.2.6 GPIODOUTSET Register (Offset = 14h) [Reset = 00000000h]

GPIODOUTSET is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTSET_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTSET_TABLE.

Return to the Summary Table.

General Purpose Input Output Data Out Set
Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-53 GPIODOUTSET Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-61 GPIODOUTSET Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to set GPIODOUT bit n.
Read value is 0.

20.8.2.7 GPIODOUTCLR Register (Offset = 18h) [Reset = 00000000h]

GPIODOUTCLR is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTCLR_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTCLR_TABLE.

Return to the Summary Table.

General Purpose Input Output Data Out Clear
Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-54 GPIODOUTCLR Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-62 GPIODOUTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to clear GPIODOUT bit n.
Read value is 0.

20.8.2.8 GPIODOUTTGL Register (Offset = 1Ch) [Reset = 00000000h]

GPIODOUTTGL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTTGL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_GPIODOUTTGL_TABLE.

Return to the Summary Table.

General Purpose Input Output Data Out Toggle
Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-55 GPIODOUTTGL Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-63 GPIODOUTTGL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to toggle GPIODOUT bit n.
Read value is 0.

20.8.2.9 IO0PSEL Register (Offset = 20h) [Reset = 00000000h]

IO0PSEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO0PSEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO0PSEL_TABLE.

Return to the Summary Table.

Input Output 0 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1.
To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-56 IO0PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-64 IO0PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set.

0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG

1h = Peripheral output mux selects AUX_SPIM SCLK.

2h = Peripheral output mux selects AUX_SPIM MOSI.

3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.

4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.

5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.

6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.10 IO1PSEL Register (Offset = 24h) [Reset = 00000000h]

IO1PSEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO1PSEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO1PSEL_TABLE.

Return to the Summary Table.

Input Output 1 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1.
To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-57 IO1PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-65 IO1PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set.

0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG

1h = Peripheral output mux selects AUX_SPIM SCLK.

2h = Peripheral output mux selects AUX_SPIM MOSI.

3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.

4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.

5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.

6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.11 IO2PSEL Register (Offset = 28h) [Reset = 00000000h]

IO2PSEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO2PSEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO2PSEL_TABLE.

Return to the Summary Table.

Input Output 2 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1.
To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-58 IO2PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-66 IO2PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set.

0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG

1h = Peripheral output mux selects AUX_SPIM SCLK.

2h = Peripheral output mux selects AUX_SPIM MOSI.

3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.

4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.

5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.

6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.12 IO3PSEL Register (Offset = 2Ch) [Reset = 00000000h]

IO3PSEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO3PSEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO3PSEL_TABLE.

Return to the Summary Table.

Input Output 3 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1.
To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-59 IO3PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-67 IO3PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set.

0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG

1h = Peripheral output mux selects AUX_SPIM SCLK.

2h = Peripheral output mux selects AUX_SPIM MOSI.

3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.

4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.

5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.

6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.13 IO4PSEL Register (Offset = 30h) [Reset = 00000000h]

IO4PSEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO4PSEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO4PSEL_TABLE.

Return to the Summary Table.

Input Output 4 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1.
To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-60 IO4PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-68 IO4PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set.

0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG

1h = Peripheral output mux selects AUX_SPIM SCLK.

2h = Peripheral output mux selects AUX_SPIM MOSI.

3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.

4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.

5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.

6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.14 IO5PSEL Register (Offset = 34h) [Reset = 00000000h]

IO5PSEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO5PSEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO5PSEL_TABLE.

Return to the Summary Table.

Input Output 5 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1.
To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-61 IO5PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-69 IO5PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set.

0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG

1h = Peripheral output mux selects AUX_SPIM SCLK.

2h = Peripheral output mux selects AUX_SPIM MOSI.

3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.

4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.

5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.

6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.15 IO6PSEL Register (Offset = 38h) [Reset = 00000000h]

IO6PSEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO6PSEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO6PSEL_TABLE.

Return to the Summary Table.

Input Output 6 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1.
To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-62 IO6PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-70 IO6PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set.

0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG

1h = Peripheral output mux selects AUX_SPIM SCLK.

2h = Peripheral output mux selects AUX_SPIM MOSI.

3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.

4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.

5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.

6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.16 IO7PSEL Register (Offset = 3Ch) [Reset = 00000000h]

IO7PSEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO7PSEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IO7PSEL_TABLE.

Return to the Summary Table.

Input Output 7 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1.
To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-63 IO7PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-71 IO7PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set.

0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG

1h = Peripheral output mux selects AUX_SPIM SCLK.

2h = Peripheral output mux selects AUX_SPIM MOSI.

3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.

4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.

5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.

6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.17 IOMODEL Register (Offset = 40h) [Reset = 00000000h]

IOMODEL is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODEL_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODEL_TABLE.

Return to the Summary Table.

Input Output Mode Low
This is an alias register for IOMODE.IO0 thru IOMODE.IO3.

Figure 20-64 IOMODEL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDIO3IO2IO1IO0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-72 IOMODEL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-6IO3R/W0hSee IOMODE.IO3.
5-4IO2R/W0hSee IOMODE.IO2.
3-2IO1R/W0hSee IOMODE.IO1.
1-0IO0R/W0hSee IOMODE.IO0.

20.8.2.18 IOMODEH Register (Offset = 44h) [Reset = 00000000h]

IOMODEH is shown in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODEH_FIGURE and described in #AUX_AIODIO_AUX_AIODIO_MMAP_AUX_AIODIO_AUX_AIODIO_ALL_IOMODEH_TABLE.

Return to the Summary Table.

Input Output Mode High
This is an alias register for IOMODE.IO4 thru IOMODE.IO7.

Figure 20-65 IOMODEH Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDIO7IO6IO5IO4
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-73 IOMODEH Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-6IO7R/W0hSee IOMODE.IO7.
5-4IO6R/W0hSee IOMODE.IO6.
3-2IO5R/W0hSee IOMODE.IO5.
1-0IO4R/W0hSee IOMODE.IO4.