SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The registers listed in Table 13-4 and Table 13-5 are not accessible through the host for reading and writing. These registers are used to store internally calculated key information and intermediate results. However, when the host performs a write to any of the respective AESKEY2__0 to AESKEY2__3 or AESKEY3__0 to AESKEY3__3 addresses, respectively, the whole 128-bit AESKEY2__0 to AESKEY2__3 or AESKEY3__0 to AESKEY3__3 register is cleared to zeroes.
The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to AES_KEY2_n registers. The intermediate authentication result for GCM and CCM is stored in the AESKEY3_n register.
| AESKEY2__0 to AESKEY2__3 (Write Only), 32-bit Address Offset: 0x500 to 0x50C in 0x4-byte increments |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AESKEY2__0 to AESKEY2__3[31:0] AESKEY2__0 to AESKEY2__3[63:32] AESKEY2__0 to AESKEY2__3[95:64] AESKEY2__0 to AESKEY2__3[127:96] | |||||||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| AESKEY3__0 to AESKEY3__3 (Write Only), 32-bit Address Offset: 0x510 to 0x51C in 0x4-byte increments |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AESKEY3__0 to AESKEY3__3[31:0] / AESKEY2__0 to AESKEY2__3[159:128] AESKEY3__0 to AESKEY3__3[63:32] / AESKEY2__0 to AESKEY2__3[191:160] AESKEY3__0 to AESKEY3__3[95:64] / AESKEY2__0 to AESKEY2__3[223:192] AESKEY3__0 to AESKEY3__3[127:96] / AESKEY2__0 to AESKEY2__3[255:224] | |||||||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | Field Name | Function |
|---|---|---|
| 255–0 | – | This register is used to store intermediate values. |
| Bit | Field Name | Function |
|---|---|---|
| 255–0 | Zeroes | This register must remain zero. |
| Bit | Name | Function |
|---|---|---|
| 127–0 | GHASH_H | The internally-calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM). |
| 255–128 | – | This register is used to store intermediate values and is initialized with zeroes when loading a new key. |
Reusing the AES_KEYn registers is allowed for sequential operations; however for CBC-MAC, intermediate values must be cleared when programming the respective mode and length parameters.
When performing a GCM operation without loading a new key (through the key store), a write to one of the AES_KEY3 register locations is required to clear the register.
If a CBC-MAC operation is started without loading a new key (through the key store), and the previous operation was not a CBC-MAC operation, both AESKEY2__0 to AESKEY2__3 and
AESKEY3__0 to AESKEY3__3 register locations must be written before starting the CBC-MAC operation, which is required to clear these two key registers.